JPH0258263A - Logic integrated circuit of compound semiconductor - Google Patents

Abstract

PURPOSE:To increase the degree of integration and the speed of operation without decreasing a large noise margin by making the structure of a pull-down transistor different from the structure of a transistor constituting an invertor. CONSTITUTION:A logic circuit is provided with an invertor, a level shift diode 11 and a pull-down transistor 14. The invertor is composed of normally-ON transistor 13 for a load and a normally ON transistor 12 for driving. The level shift diode 11 is connected between a signal input terminal 15 and the gate 122 of the above transistor 12 for driving. The pull-down transistor 14 is connected with the gate 122 of the transistor 12 for driving, and biases it in the OFF-state. The structure of the transistors 13, 12 consisting the above invertor and the structure of the pull-down transistor 14 are made mutually different. For example, the transistor 14 has a structure wherein an ion implanted layer 230 is not formed. Said layer exists in the other transistors 13, 12, in order to reduce resistance between the source and the drain and between the gate and the drain.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a compound semiconductor logic integrated circuit in which the input stage of the logic integrated circuit is improved.

(Prior art) In recent years, GaAs, which can operate at higher speeds than Si integrated circuits, has been developed.
Integrated circuits have attracted attention, and currently there are 1000 logic integrated circuits.
In memory integrated circuits, 16 bits SR
AM (5tatic Random Access
LSI-level GaAs integrated circuits such as readwrite memory (readwrite memory) have been realized.

For example, BFL (Buffered FET Log
ic).

5DFL (Schottky Diode FET L
ogic) and DCF'L (Direct Coup
led FET Logic) etc. are widely used. One of the most important parameters to compare the performance of these logic integrated circuits is the power consumption per gate (Pd
), but among them, only DCFL can reduce the Pd limit to several W/chip, and has the potential to realize VLSI-class large-scale integrated circuits that are larger than IOK gates.

However, DCFL has a small noise margin of about 0.2 V, and requires careful design attention when increasing integration. Therefore, in order to ensure ease of design and stable operation of the entire circuit, a logic integrated circuit with a larger noise margin is desired.

What we came up with was 5L, which was developed from DCFL.
CF (Schottky Diode Level 5
hifter Capa-citor Coupled
FET Logic). Figure 5 shows this 5LCF
1 is a diagram illustrating an inverter provided on a GaAs substrate using a GaAs substrate. Normally-on Schottky gate field effect transistor for load (D.

MESFET) I3 and for driving, MESFET
I2 is connected to form the main part of this inverter.

For this drive, connect the drain to the gate of the MESFET, and connect the gate to the source for pull-down.

MESFET 14 is provided. 11 level shift diodes are used to pull down the cathode.
It is connected to the gate of MESFET 14.

This inba-ri! /iD, OV is applied to the drain 17 of MESFET 13, and a signal with a logic amplitude of 0 to 5 V is input from the logic input crab 5 with K-2 and OV applied to each of MESFET 14 and Noah's 18, From the logic output 16, the logic amplitude of the input signal and the opposite phase is 0 to 4.
It is designed to output an output signal of V.

The pull-down MESFET 14 is usually designed to have a sufficiently smaller current amount than the load MESFET 13 in order to reduce power consumption and improve fan-out characteristics.

The reason why the MESFET for pull-down affects the fan-out characteristics will be described below with reference to FIG.

Of the switching time, the startup 9 hours are used to drive the next stage inverter, use the charge of the gate capacitance of MESFET 22 as a load, and charge it with the current (Ir, ) of MESFET 13, but it is used for pull-down purposes. , MESFE
If there is a current (I PD ) flowing through T 24, it actually becomes Jt, -IPD...
... Charging will be performed with il+. Therefore, as the fan-out number (to) increases, the charging current becomes IL-N
φIPD decreases as shown in (2), and the rise time becomes slower.

FIG. 7 shows the relationship between the current ratio (IPD/IL) of the pull-down transistor and the load transistor and the switching time. It is clear from this figure that it is desirable to set the current ratio to 1/10 or less.

As a method of restricting the current, the dimensions are usually changed such as increasing the gate length (Lg) and decreasing the gate length (Lg).

The Wg can be reduced to at most 2 μm due to the limits of pattern formation and reproducibility.

The Wg of normally used load transistors is 5 μm to 20
Considering that IPD/IL≦1/10 in μm, the current cannot be reduced unless Wg is made smaller and Lg is also made larger.

However, increasing Lg increases the size of the MESFET pattern, which is not preferable in terms of high integration.

Furthermore, as shown in FIG. 8, it can be used for pull-down.

MESFET 34 has gate ψ drain capacitance (Cgd
) 40, a part of the input signal that passes through the junction capacitance 41 of the level shift diode is used to charge and discharge Cgd, and the gate of MESFET 12 is charged and discharged with a small current for driving. As a result, the transmission speed of the signal decreases, which poses a problem in terms of increasing the speed.

(Problems to be Solved by the Invention) As described above, the conventional logic integrated circuit using GaAs uses a level shift diode and a pull-down transistor provided in the input stage to control the amplitude of the signal input to the circuit. Since the noise level does not deteriorate, a wide noise margin can be secured.

However, in order to reduce power consumption and improve the 7 unout characteristics, it is necessary to reduce the current of the pull-down transistor, and if the gate length is designed to be large for this purpose, the pattern becomes narrow, making it difficult to achieve high integration. Ta.

In addition, since the capacitance between the gate and drain of the pull-down transistor becomes large, high-speed operation cannot be improved. The purpose of the present invention is to provide a compound semiconductor logic integrated circuit with improved processing speed and improved speed.

[Structure of the invention]

(Means for Solving the Problems) In order to achieve the above object, the present invention has a structure of a 5LCF pull-down transistor that is different from the structure of the transistors constituting the inno It is characterized by the fact that it does not have an ion-implanted layer to reduce the resistance between drains, and has a structure that prevents current from flowing.

(Function) The structure of the pull-down transistor used in the present invention does not have an ion-implanted layer to reduce the source-gate resistance and gate-drain resistance that are present in ordinary transistors. The conductance is smaller than that of a transistor.Therefore, the current can be sufficiently reduced without increasing Lg, so the size of the pull-down transistor pattern and the gate
It is possible to suppress an increase in capacitance between drains and achieve higher integration and higher speed.

(Example) The details of the present invention will be explained using an example. FIG. 1 is a pattern diagram of an inverter circuit provided on a GaAs substrate according to an embodiment of the present invention, and FIGS. 2 to 4 are diagrams showing the internal structure of the transistor shown in FIG. 1. This internal structure is shown in Figure 2 as the A-A' cross section shown in Figure 1.
FIG. 3 is a sectional view taken along line BB', and FIG. 4 is a sectional view taken along line cc'. Incidentally, since the inverter circuit in the pattern diagram shown in FIG. 1 is the same as that shown in FIG. 5, the explanation thereof will be omitted. Gate width and gate length of each transistor,
The transconductance (per 1 μm gate width) and saturation current are set as shown in Table 1.

In addition, the level shift diode needs to have a large junction area in order to maintain its high speed, and in this case, the junction area is 50
It is set to μm2.

The internal structure of each MESFET is as shown in FIGS. 2 to 4, in which an n-type active layer exists to reduce the parasitic resistance between the source and gate and between the gate and drain. The structure shown in FIG. 3 and the non-existing structure, that is, the structure shown in FIG. 3, are used depending on the MESFET. In other words, M for load related to switching operation
ESFET 13 and drive MESFET 12 are
As shown in the figure, a structure with high transconductance is used to enable high-speed operation. In addition, MESF for pull-downs where you want to improve the fan-out characteristics by reducing the current.
For the ETI 4, a structure having a large parasitic resistance and a small transconductance, that is, the structure shown in FIG. 3 is used. The specific structure will be explained below.

An n-type active layer 22), 222, 223, 224 is formed by selective ion implantation into a semi-insulating GaAa substrate 2)0.
is formed. On these layers are provided Schottky gates 112, 122 consisting of gold #iWNx and an anode 132. Using this gate as a mask, high-concentration ion implantation using the cell 7 alignment method is performed to form an n-type layer 230 that will become a source region, a drain region, and a cathode region of the diode. This n+
Source 113, 123, drain 1 provided on the mold layer
11, 12) and anode 131 are each ohmic electrodes.

The pull-down D-MESFET does not have an n-type layer 230 and only has an n-type active layer 224. 260.15.16
17 and 18 are aluminum first-layer wiring lines, and 260 is a wiring line for connecting the cathode 131 and the gate 122.

At this time, as shown in FIGS. 2 to 4, the cathode 131 uses an n-type active layer 223, and the thickness is set so that the depletion layer does not extend below the bottom of the n-type active layer 223 within the operating voltage range. It is set.

Specifically, the n-type active layer 223 of the level shift diode 11 is implanted with ions to form the n-type active layer 22) of the load D-MESFET 13, and the n-type of the drive D-MESFET 120, which is different from this condition. It was formed by performing double ion implantation, overlapping the ion implantation for forming the mold active layer 222. The implantation conditions were a constant acceleration voltage of 50 KeV,
The dose is for load, 3.5 for MESFET.
X I Q12/7. For driving, MESFET and pull-down, 3.0X1 for MESFET
0.7m. These ion-implanted layers were activated by capless annealing in an As atmosphere at 800° C. for 15 minutes.

Next, the ring oscillator configured by connecting 15 stages of this inverter circuit is set to VDD= , 5V, V, = -1,
As a result of operating with the power supply voltage of OV and measuring its oscillation frequency, the gate delay time was t, , = 4q, , /gate, and the power consumption was Pd = 0.8 m w /gate. As shown in FIG. 3, the circuit pattern has a length of 23 μm and a width of 34 μm, and is 782 μm2. Among these, the pull-down MESFET is vertically 11μ
m, width 14 μm and 154 μm2, 19% of the total
occupies .

On the other hand, for comparison, a pattern diagram of a conventionally used inverter circuit and an internal structure of a pull-down transistor are shown in FIGS. 9 and 10. Table 2 shows the gate dimensions, transconductance per 1 μm gate width, and saturation current of each transistor.

Like the load and drive MESFETs, the internal structure of the pull-down MESFET has an n-type active layer as shown in Table 2, and has a large transconductance. Therefore,
The current is restricted by increasing Lg to 4 μm.

The size of the pattern is 26 μm vertically and 35 μm horizontally.
10Am". Of these, MESFE for pull-down
The area occupied by T is 14 μm vertically and 15 μm horizontally2)
They are 0μm2 and 23chi. Comparing the overall size with the above-mentioned embodiment of the present invention, it is found that the total size is as large as 9103 m2/782 μm2=16. For comparison, a similar ring oscillator was constructed using the conventional inverter shown in FIGS. 9 and 10, and the oscillation frequency was measured under the same conditions as above. Gate, Pd
=0.8mW/gate, for pull-down, ME
An increase in delay was observed due to the drain-gate capacitance of the SFET.

Note that an LDD structure is also used as a FET structure to reduce the parasitic resistance between the gate and source and between the gate and drain.
It goes without saying that the same effect can be achieved even when the n-layer structure shown in FIG. 4 is used for the FET and the pull-down MESFET. According to the structure, it is possible to provide a compound semiconductor logic integrated circuit with high integration and high speed without reducing the noise margin.

[Brief explanation of the drawings] Figure 4 is a sectional view taken along line c-c' in Figure 1, Figure 5 is a circuit diagram showing the basic circuit of a logic integrated circuit, and Figure 6 is a diagram for explaining fan-out characteristics. Figure 7 is a characteristic diagram showing the relationship between the current ratio of the pull-down transistor and the load transistor and the switching time, Figure 8 is a circuit diagram explaining the influence of the pull-down transistor capacitance, and Figure 9 is a conventional diagram. FIG. 10 is a plan view showing the logic integrated circuit of FIG.
It is a D' cross-sectional view. 13...For load, MESFET, 12...For drive, MESFET, 11...Level shift diode, 14...For pulldown, MESFET 0

Claims (5)

[Claims] (1) an inverter comprising a normally-on compound semiconductor load transistor and a normally-on compound semiconductor driving transistor; a level shifting diode connected between a signal input terminal and the gate of the driving transistor; In a logic circuit having a compound semiconductor pull-down transistor connected to the gate of the driving transistor and biasing the driving transistor to an off state, the structure of the transistor constituting the inverter and the structure of the pull-down transistor are different. Features of compound semiconductor logic integrated circuits. (2) The compound semiconductor logic integrated circuit according to claim 1, wherein the compound semiconductor is GaAs. (3) The compound semiconductor logic integrated circuit according to claim 1, wherein the load transistor, the driving transistor, and the pull-down transistor are Schottky gate field effect transistors. (4) The compound semiconductor logic integrated circuit according to claim 1, wherein the diode is a Schottky diode. (5) The compound semiconductor logic integrated circuit according to claim 1, wherein the level shifting diode has a matching capacitance that is at least twice the gate-source capacitance of the driving transistor.