JP4963489B2 - Drive device - Google Patents

Description

  The present invention relates to a drive device, and more particularly, to a drive device including a plurality of output circuits in which output polarity undergoes reverse transition.

  In general, an operational amplifier circuit (Rail to Rail amplifier) is known as a source amplifier that is an output circuit that outputs a source driver (see, for example, Patent Document 1).

  An example of the circuit configuration of such an operational amplifier circuit is shown in FIG. 7, and an example of operation waveforms of the operational amplifier circuit is shown in FIG. The operational amplifier circuit 52 includes a differential unit 56, a differential amplification unit 57, an output unit 58, and a phase compensation unit 59. Input data and feedback from the output are input to the differential unit 56, and the differential amplifier (differential unit 56) operates by the voltage difference to generate a current. The current is amplified by the differential amplifier 57, the P channel transistor and the N channel transistor (Pch / Nch) of the output unit are driven, and the same potential as the input is output to the output. The phase compensation unit 59 includes a phase compensation capacitor C1 installed between the output and the Pch / Nch gate (PG / NG) of the output unit, and compensates for the stability (phase margin) of the negative feedback.

  In a liquid crystal display using a source driver as a driving device, it is necessary to invert the pixel potential polarity of the liquid crystal cell in order to prevent image burn-in. Generally, dot inversion operation, line inversion operation, or the like is used as the method. As shown in FIG. 9, the dot inversion operation is an operation of switching the output polarity for each output terminal (out1 to outn) of the source driver. FIG. 10 shows a schematic configuration of the driving device in consideration of the inversion driving operation. VH1 to VHn / 2 are positive input levels, and VL1 to VLn / 2 are negative input levels. Positive polarity and negative polarity are polarities when the common voltage VCOM is used as a reference voltage, and show curves as shown in FIG. The voltage difference from the common voltage VCOM is the same on the positive electrode side and the negative electrode side. The signal REV is a polarity inversion signal. During the dot inversion operation (REV = fixed), the polarities of the odd number output (out1, 3,..., (N-1)) and the even number output (out2, 4,..., N) are reversed. That is, when a positive polarity is output to the output out1, a negative polarity is output to the adjacent output out2. During the line inversion operation, the signal REV is inverted for each line, and the polarities of the outputs out1 and out2 are inverted for each line.

The source amplifier used for the source driver is required to have a high slew rate and a phase margin. In general, a technique is known in which a switch is provided in a source amplifier circuit, and by switching the switch, the node connection of various compensation capacitors (capacitances) is changed at an arbitrary period to improve the slew rate ( For example, see Patent Document 2).
JP 05-063459 A JP 2006-094534 A

  However, since the increase in the phase margin required for the source amplifier and the increase in the slew rate are contradictory characteristics, it is difficult to achieve both the increase in the phase margin and the increase in the slew rate.

  At the time of output transition (H → L or L → H), the Pch / Nch gate potential (PG / NG) of the output unit 58 is suppressed by the influence of coupling via the phase compensation capacitor C1. Therefore, when the phase compensation capacitor C1 of the phase compensation unit 59 is increased, the phase margin increases but the slew rate decreases. In particular, in the case of the inversion driving operation, the output polarity is changed, so that the output amplitude becomes large (for example, when the VH63 / VL63 levels in FIG. 11 are alternately output for each line). For this reason, in the source amplifier, the influence of coupling via the phase compensation capacitor C1 of the phase compensation unit 59 becomes large, resulting in a slew rate delay (see FIG. 8).

  On the other hand, if the phase compensation capacitance C1 of the phase compensation unit 59 is reduced, the output fluctuation cannot be absorbed, so that the slew rate is increased but the phase margin is degraded.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a driving device including an output circuit capable of increasing the phase margin and increasing the slew rate.

  In order to achieve the above object, the drive device according to claim 1 is a first output unit that outputs a first output signal having a first polarity, and a difference between the input signal and the first output signal. A first differential unit that outputs a dynamic signal, and a first capacitive unit that is connected in parallel to the first differential unit and includes a plurality of series-connected first capacitive elements that input the differential signal And a first phase compensation capacitive element connected in parallel with the first capacitive section and provided in series between the first capacitive section and the first output section. A first output circuit including a phase compensation capacitor unit, a second output unit that outputs a second output signal having a phase opposite to the first polarity, an input signal, and the second output signal. A second differential unit that outputs the differential signal, and a plurality of series connected in parallel to the second differential unit and the differential signal input. A plurality of directly connected second capacitors, which are connected in parallel with the second capacitor, and provided between the second capacitor and the second output unit. A second output circuit including a second phase compensation capacitor unit including two phase compensation capacitance elements, and between the plurality of first capacitance elements and the plurality of second phase compensation capacitors. The capacitor elements are connected to each other, and the plurality of second capacitor elements are connected to the plurality of first phase compensation capacitor elements.

  The drive device according to claim 2 is the drive device according to claim 1, wherein the first output circuit selects a grayscale voltage based on a data input signal and outputs the selected grayscale voltage to the first differential section. A first decoder is provided, and the second output circuit includes a second decoder that selects a gradation voltage based on a data input signal and outputs the selected gradation voltage to the second differential section.

  The drive device according to claim 3 is the drive device according to claim 1 or 2, wherein each of the first differential section and the second differential section is a differential amplifier.

  According to a fourth aspect of the present invention, in the drive device according to any one of the first to third aspects, the first output section includes a first P-channel transistor and a first P-channel transistor connected in series. A first N-channel transistor, a gate of the first P-channel transistor being connected to a first output side of the first differential section, and a second output section being connected in series. Two P-channel transistors and a second N-channel transistor, and the gate of the second P-channel transistor is connected to the first output side of the second differential section.

  The serial connection indicates a state in which the source of the P-channel transistor and the drain of the N-channel transistor are connected, and specifically includes a CMOS circuit.

  According to a fifth aspect of the present invention, in the driving device according to any one of the first to fourth aspects, the first output circuit includes a first differential amplifying unit as the first difference. The second output circuit includes a second differential amplifying unit between the second differential unit and the second capacitor unit. Is.

  According to the driving device of the present invention, it is possible to increase the phase margin and to increase the slew rate.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  First, a schematic configuration of the drive device according to the embodiment of the present invention will be described. FIG. 1 is a configuration diagram illustrating an example of a schematic configuration of a drive device 10 according to the present embodiment.

  The driving device 10 according to the present embodiment includes n (n is a multiple of 2) output circuits (driver cells) 121 to 12n. VH1 to VHn / 2 are positive input levels, and VL1 to VLn / 2 are negative input levels. The positive polarity and the negative polarity are polarities when the common voltage VCOM is used as a reference voltage (see FIG. 11). The signal REV is a polarity inversion signal.

  The drive device 10 performs dot inversion operation and line inversion operation in response to a signal REV, and outputs an odd number output (out1, 3,..., (N-1)) and an even number output (out2, 4,. , N) and the output polarity is opposite to each other (see FIG. 9B).

  Next, an outline of the output circuits (driver cells) 121 to 12n in the driving device 10 according to the embodiment of the present invention will be described. FIG. 2 is a configuration diagram illustrating an example of a schematic configuration of the driver cell 121 and the driver cell 122 according to the present embodiment. FIG. 3 is a configuration diagram showing a specific example of the differential units 161 and 162 and the output units 181 and 182 of the present embodiment. Note that odd-numbered driver cells (driver cells 121, 123,..., (N−1)) have substantially the same configuration, and therefore only the driver cell 121 is shown here. Further, since even-numbered driver cells (driver cells 122, 124,..., N) have substantially the same configuration, only the driver cell 122 is shown here.

  The driver cell 121 according to this embodiment includes a decoder 141, a differential unit 161, an output unit 181, two phase compensation capacitors C11, and two capacitors Ca1. The driver cell 122 includes a decoder 142, a differential unit 162, an output unit 182, two phase compensation capacitors C12, and two capacitors Ca2. The driver cell 122 has substantially the same configuration as the driver cell 121. ing.

  The decoders 141 and 142 select one of gradation voltages input based on a data input signal (not shown) for each raster period, and output the selected decoder voltage as a decoder output.

  The differential unit 161 is operated by a voltage difference between the input and the feedback from the output, and generates a current. As shown in FIG. 3, a specific example is a differential amplifier such as an operational amplifier.

  As shown in FIG. 3, the output units 181 and 182 are configured by a CMOS circuit including P-channel transistors P1 and P2 and N-channel transistors N1 and N2, as a specific example. The gates of the P-channel transistors P1 and P2 are connected to the first output sides 151 and 152 of the operational amplifiers 161 and 162, respectively.

  The phase compensation capacitors C11 and C12 are for compensating the stability (phase margin) of negative feedback, and a specific example is a capacitor.

  The capacitors Ca1 and Ca2 are for reducing the influence of coupling by the phase compensation capacitors C11 and C12, and a specific example is a capacitor.

  Next, the operation of the driver cells 121 and 122 of this embodiment will be described in detail using a specific example of the driver cells 121 and 122. FIG. 4 shows an example of a specific configuration of the driver cells (op-amp circuit) 121 and 122. Here, the decoders 141 and 142 are not shown. In addition, differential amplifiers 171 and 172 are provided downstream of the differential units 161 and 162. The differential amplifying units 171 and 172 amplify the current generated in the differential units 161 and 162, and drive the P channel transistors P1 and P2 and the N channel transistors N1 and N2 of the output units 181 and 182, respectively. This is for outputting the same potential as the input.

  The capacitor Ca1 is provided between the gate PG1 and the output out2 of the operational amplifier circuit 122 and between the gate NG1 and the output out2 of the operational amplifier circuit 122. The capacitor Ca2 is provided between the gate PG2 and the output out1 of the operational amplifier circuit 121 and between the gate NG2 and the output out1 of the operational amplifier circuit 121. The capacitors Ca1 and Ca2 are smaller than the phase compensation capacitors C11 and C12, respectively.

  FIG. 5 shows a specific example of operation waveforms of the operational amplifier circuits 121 and 122 of the present embodiment shown in FIG.

  In the case of the dot inversion and line inversion driving operations, if the output out1 in the first line is positive, the output out2 is negative. In the next line, the output out1 is a negative electrode and the output out2 is a positive electrode. When the output changes from positive to negative, the output transitions from “HL” (from H level to L level). When the output changes from negative to positive, the output changes from “LH” (from L level to H level). To). That is, the output out1 and the output out2 always undergo reverse transitions.

  In the operational amplifier circuit 121, when the output out1 transitions to “HL”, coupling due to the phase compensation capacitor C11 occurs in the gate NG1, but the output out2 of the operational amplifier circuit 122 transitions to “LH” transition. As a result, reverse-phase coupling occurs due to the capacitance Ca1, and the amount of coupling to the gate NG1 due to the phase compensation capacitance C11 can be reduced. Similarly, the amount of coupling to the gate PG1 by the phase compensation capacitor C11 can be reduced by the reverse-phase coupling generated by the capacitor Ca1.

  On the other hand, in the operational amplifier circuit 122, the output out2 transitions to "L-H" contrary to the output out1, and the coupling due to the phase compensation capacitor C12 occurs in the gate NG2, but the output out1 is "HL". Therefore, the reverse phase coupling occurs due to the capacitance Ca2, and the amount of coupling to the gate NG2 due to the phase compensation capacitance C12 can be reduced. Similarly, the amount of coupling to the gate PG2 by the phase compensation capacitor C12 can be reduced by the reverse-phase coupling generated by the capacitor Ca2.

  Similarly, when the output out1 of the operational amplifier circuit 121 has a transition of “LH” (the output out2 has a transition of “HL”), the operational amplifier circuit 121 similarly generates the phase compensation capacitor C11. The amount of coupling to the gates PG1 and NG1 can be reduced by the reverse-phase coupling generated by the capacitor Ca1, and similarly, in the operational amplifier circuit 122, the coupling to the gates PG2 and NG2 generated by the phase compensation capacitor C12. The amount of ring can be reduced by the reverse-phase coupling generated by the capacitor Ca2.

  Thus, the amount of coupling to the gate PG1 of the P-channel transistor P1 and the gate NG1 of the N-channel transistor N1 of the output unit 181 due to the phase compensation capacitor C1 generated at the time of output transition can be reduced. The amount of coupling to the gate PG2 of the P-channel transistor P2 and the gate NG2 of the N-channel transistor N2 in the output unit 182 by the phase compensation capacitor C2 can be reduced.

  Therefore, when the outputs out1 and out2 have full amplitude, the operational amplifier circuit 121 has the same level as when a phase compensation capacitor having a capacitance of “C11-Ca1” is added, and suppresses the gate potentials of the gates PG1 and NG1. Therefore, the slew rate becomes faster. Similarly, in the operational amplifier circuit 122, the capacity becomes the same level as when the phase compensation capacity of “C12-Ca2” is added, and the suppression of the gate potentials of the gates PG2 and NG2 is reduced, so that the slew rate is increased. .

  6 shows the operation waveforms of the gates PG1 and NG1 and the output out1 of the operational amplifier circuit 121 of the present embodiment, and the operation waveforms of the gates PG1 and NG1 and the output out1 of the conventional operational amplifier circuit 50 shown in FIG. Comparison with is shown. As shown in FIG. 6, in the operational amplifier circuit 121 of this embodiment, the potentials of the gates PG1 and NG1 are larger (Y> y), the suppression of the gate potential is smaller, and the slew rate (the output is the maximum value). It can be seen that (time until) becomes high (X <x).

  In the operational amplifier circuit 121, since the phase compensation capacitor C11 and the capacitor Ca1 are connected in parallel, the phase margin is approximately the same as when the phase compensation capacitor of “C11 + Ca1”, which is a combined capacitor, is added. Since the compensation capacity increases, the phase margin increases. Similarly, in the operational amplifier circuit 122, since the phase compensation capacitor C12 and the capacitor Ca2 are connected in parallel, the phase margin is about the same as when the phase compensation capacitor of “C12 + Ca2” that is the combined capacitor is added. Thus, the phase compensation capacity is increased, and the phase margin is increased.

  As a specific example, when the capacitors C11 and C12 are 350 fF and the capacitors Ca1 and Ca2 are 87.5 fF, the conventional operational amplifier circuit 50 (see FIG. 7) has a phase margin of 11.0 deg. In the operational amplifier circuits 121 and 122 of the present embodiment, it is enlarged to 12.5 deg.

  In the present embodiment, the case where the operational amplifier circuits 121 and 122 having different output polarities are combined (connected) has been described in detail, but other odd-numbered operational amplifier circuits 121, 123,. The same applies when n-1) and even-numbered operational amplifier circuits 121, 123,..., (n-1) are combined.

  In this embodiment, an operational amplifier circuit used in a source amplifier of a source driver that performs dot inversion and line inversion driving is described. However, the present invention is not limited to this, and a plurality of operational amplifier circuits in which output transitions are reversed. In the same manner, the driving device can be applied by adding a capacitor Ca and connecting operational amplifiers having different output polarities.

  As described above, according to the operational amplifier circuit 12m (m = 1 to n) of the present embodiment, the capacitance Cam is parallel to the phase compensation capacitance C1m, and the polarity of the output of the gates PGm and NGm of the output unit 18m. Since the phase compensation capacitor C1m generated at the time of output transition, the amount of coupling to the gate PGm of the P-channel transistor Pm and the gate NGm of the N-channel transistor Nm is reduced. Since the suppression of the gate potential can be reduced, the slew rate can be increased.

  Further, since the phase compensation capacity becomes the same level as when the phase compensation capacity of “C1n + Can” which is the combined capacity is added, the phase margin can be expanded.

  Therefore, in the operational amplifier circuit 12m provided in the driving device 10 of the present embodiment, the phase margin can be increased and the slew rate can be increased.

It is a block diagram which shows an example of schematic structure of the drive device which concerns on embodiment of this invention. It is a block diagram which shows an example of schematic structure of the driver cell (output circuit) in the drive device which concerns on embodiment of this invention. It is a block diagram which shows an example of schematic structure of the driver cell (output circuit) in the drive device which concerns on embodiment of this invention. It is a block diagram which shows an example of the specific structure of the operational amplifier circuit which concerns on embodiment of this invention. It is an operation waveform diagram showing a specific example of the operation waveform of the operational amplifier circuit according to the embodiment of the present invention. It is an operation waveform diagram showing a comparison between the slew rate of the operational amplifier circuit according to the embodiment of the present invention and the slew rate of the conventional operational amplifier circuit. It is a schematic block diagram which shows an example of the circuit structure of the conventional operational amplifier circuit. It is an operation | movement waveform diagram which shows a specific example of the operation | movement waveform of the conventional operational amplifier circuit. It is explanatory drawing for demonstrating dot inversion operation | movement and line inversion operation | movement. It is a block diagram which shows an example of schematic structure of the conventional drive device. It is explanatory drawing which shows an example of the positive electrode negative electrode curve at the time of 64 gradation.

Explanation of symbols

10 Driving device 12m (m = 1 to n) Operational amplifier circuit (output circuit, driver cell)
14 m Decoder 16 m Differential unit 17 m Differential amplification unit 18 m Output unit C 1 m Phase compensation capacitance Cam capacitance Pm P channel transistor Nm N channel transistor

Claims (5)

A first output unit that outputs a first output signal having a first polarity; a first differential unit that outputs a differential signal between an input signal and the first output signal; and the first difference. A first capacitor unit including a plurality of first capacitor elements connected in parallel to the moving unit and receiving the differential signal; and a first capacitor unit connected in parallel to the first capacitor unit; A first phase compensation capacitor unit including a plurality of first phase compensation capacitor elements connected in series provided between the first output unit and the first output unit; and
A second output unit that outputs a second output signal having a phase opposite to that of the first polarity; a second differential unit that outputs a differential signal between an input signal and the second output signal; A second capacitor unit connected in parallel with a second differential unit and configured by a plurality of second capacitor elements connected in series to input the differential signal; and connected in parallel with the second capacitor unit; A second phase compensation capacitor unit including a plurality of directly connected second phase compensation capacitor elements provided between the second capacitor unit and the second output unit. When,
With
The plurality of first capacitance elements and the plurality of second phase compensation capacitance elements are connected, and between the plurality of second capacitance elements, and the plurality of first phase compensations. A drive device connected between the capacitive elements.   The first output circuit includes a first decoder that selects a gradation voltage based on a data input signal and outputs the selected gradation voltage to the first differential unit, and the second output circuit is based on the data input signal. The driving apparatus according to claim 1, further comprising a second decoder that selects a gradation voltage and outputs the selected gradation voltage to the second differential unit.   3. The drive device according to claim 1, wherein each of the first differential section and the second differential section is a differential amplifier.   The first output section includes a first P-channel transistor and a first N-channel transistor connected in series, and the gate of the first P-channel transistor is the first differential section of the first differential section. And the second output section includes a second P-channel transistor and a second N-channel transistor connected in series, and the gate of the second P-channel transistor is connected to the second P-channel transistor. The driving device according to claim 1, wherein the driving device is connected to a first output side of the differential section.   The first output circuit includes a first differential amplifier between the first differential and the first capacitor, and the second output circuit includes a second differential amplifier. 5. The driving apparatus according to claim 1, wherein the driving device is provided between the second differential unit and the second capacitor unit. 6.

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