JP2004061985A - Drive circuit for liquid crystal display - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data side driver capable of preventing oscillation of a operational amplifier without decreasing the slew rate. <P>SOLUTION: As an oscillation preventing phase compensation capacitive element of a operational amplifier 20, a phase compensation capacitive element 30 comprising an N-well capacitive element, in which the capacitive value is set for outputting of falling edge waveform and a phase compensation capacitive element 40 comprising an N well capacitive element, in which the capacitive value is set for outputting of rising edge waveform are connected, by connecting a gate side terminal of the N-well capacitive element to a well-side terminal in reverse parallel via switches 50 and 60. Here, of the two operational amplifiers 20 corresponding to (2n-1)-th data line and 2n-th data line, the operational amplifier 20 for outputting of rising edge waveform is connected to the phase compensation capacitive element 40; while the operational amplifier 20 for outputting falling edge waveform is connected to the phase compensation capacitive element 30. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a drive circuit for a liquid crystal display device, and more particularly to a drive circuit for a liquid crystal display device in which a phase compensation capacitor connected to an operational amplifier is an N-well capacitor.
[0002]
[Prior art]
As shown in FIG. 3, a liquid crystal display module of an active matrix type liquid crystal display device includes a liquid crystal panel (LCD panel) 1 and a control circuit (hereinafter, referred to as a controller) 2 composed of a semiconductor integrated circuit device (hereinafter, referred to as an IC). And a plurality of scan-side drive circuits (hereinafter, referred to as scan-side drivers) 3 and data-side drive circuits (hereinafter, referred to as data-side drivers) 4 comprising ICs. Although not shown in detail, the liquid crystal panel 1 has a semiconductor substrate on which a transparent pixel electrode and a thin film transistor (TFT) are arranged, a counter substrate on which one transparent electrode is formed on the entire surface, and these two substrates facing each other. A predetermined voltage (hereinafter, referred to as a common voltage Vcom) is supplied to the opposite substrate electrode, and a predetermined voltage is applied to each pixel electrode by controlling a TFT having a switching function. Then, an image is displayed by changing the transmittance of the liquid crystal by the potential difference between each pixel electrode and the counter substrate electrode. Here, a variable voltage (hereinafter, referred to as a gradation voltage) is applied as a predetermined voltage to each pixel electrode in order to display a halftone image (gradation display). On the semiconductor substrate, a data line for transmitting a gradation voltage to be applied to each pixel electrode and a scanning line for transmitting a switching control signal (scanning signal) for the TFT are wired.
[0003]
The controller 2 has an input side connected to a PC (personal computer) 5 and an output side connected to the scanning side driver 3 and the data side driver 4. Output sides of the scanning driver 3 and the data driver 4 are connected to scanning lines and data lines of the liquid crystal panel 1, respectively. The chip size of the scanning driver 3 and the data driver 4 is limited due to manufacturing restrictions. Therefore, the number of outputs corresponding to the scanning lines and data lines that can be output by one IC is also limited, and the size of the liquid crystal panel 1 is large. In this case, it is necessary to arrange a plurality of each on the outer periphery of the liquid crystal panel 1. For example, in the case of a liquid crystal panel of XGA (1024 × 768 pixels) color display, mounting of the drivers 3 and 4 on the module is as follows.
{Circle around (1)} The scanning driver 3 needs to drive 768 gate lines. For example, if it has a driving capability of 192 gates, it requires four, and is arranged on one side of the liquid crystal panel 1 in a cascade connection on the left outer periphery. You.
{Circle around (2)} The data side driver 4 needs three data lines for R (red), G (green), and B (blue) in order to display one pixel in color, so that 1024 × 3 = 3072 lines It is necessary to drive the data lines. For example, in the case of having a driving capability for 384 lines, eight lines are required, and one side is arranged in a cascade connection on the upper outer periphery of the liquid crystal panel 1.
Although not shown, a power supply circuit for supplying the common voltage Vcom is connected to the counter substrate electrode.
[0004]
Image data is sent from the PC 5 to the controller 2 of the liquid crystal display module, a clock signal and the like are sent from the controller 2 to the scanning driver 3 in parallel with each scanning driver 3, and a start signal STV for vertical synchronization is sent to the first stage. The data is sent to the scanning driver 3 and sequentially transferred to the scanning driver 3 in the cascade connection and subsequent stages. Further, a timing signal such as a clock signal and a data signal are sent from the controller 2 to the data side driver 4 in parallel to each data side driver 4, and a start signal STH for horizontal synchronization is sent to the first stage data side driver 4. Are sequentially transferred to the cascade-connected data driver 4 at the next and subsequent stages. Then, a pulse-like scanning signal is sent from the scanning driver 3 to each scanning line, and when the scanning signal applied to the scanning line is at a high level, all the TFTs connected to that scanning line are turned on, The gray scale voltage sent from the driver 4 to the data line is applied to the pixel electrode via the turned-on TFT. At this time, a common voltage Vcom is supplied from a power supply circuit (not shown) to the opposite substrate electrode. Then, when the scanning signal becomes low level and the TFT changes to the off state, the potential difference between the pixel electrode and the counter substrate electrode is held until the next gradation voltage is applied to the pixel electrode. Then, by sequentially transmitting a scanning signal to each scanning line, a predetermined gradation voltage is applied to all the pixel electrodes, and an image can be displayed by rewriting the gradation voltage in a frame cycle.
[0005]
When each pixel electrode is driven by the data-side driver 4, it is necessary to perform AC driving with respect to the potential of the counter substrate electrode due to the characteristics unique to the liquid crystal. As a typical AC driving method, the gray scale voltage from the data driver 4 is applied to the common voltage Vcom by a positive voltage and a negative voltage for one scan period (hereinafter, referred to as one horizontal period) for one scan line. There are a line inversion driving method for switching on a line basis and a dot inversion driving method for switching on a pixel electrode basis. The line inversion driving method is a method in which the grayscale voltage from the data side driver 4 is set to a low voltage of, for example, +5 V or less, and the polarity is inverted by changing the common voltage Vcom every one horizontal period to perform AC driving. is there. On the other hand, in the dot inversion driving method, the common voltage Vcom is fixed to a constant voltage, and a voltage having a positive polarity (hereinafter referred to as a positive gradation) is applied to the common voltage Vcom as a gradation voltage from the data driver 4. Voltage and a voltage having a negative polarity (hereinafter referred to as a negative gradation voltage) are set so as to be symmetrical, and the positive gradation voltage and the negative gradation voltage are alternately changed every one horizontal period. It is a method of supplying. For example, in the case of a 64-gradation display, Vcom <VP64 <... <VP1 as the positive gradation voltages VP1 to VP64, and Vcom>VN64> ... VN1 as the negative gradation voltages VN1 to VN64, and the positive gradation voltage VP1 to VP64 and the negative gradation voltages VN1 to VN64 are set symmetrically with respect to the common voltage Vcom. Then, one gray scale voltage VPx of the positive gray scale voltages VP1 to VP64 and one gray scale voltage VNx of the negative gray scale voltages VN1 to VN64 are alternately supplied every one horizontal period. .
[0006]
In the following, as a conventional example of the data-side driver 4, the data-side driver 100 using the dot inversion driving method is assumed to be capable of driving 384 data lines of a liquid crystal panel and capable of displaying 64 gradations. This will be described with reference to FIG. The data-side driver 100 supplies m = 6 bits of data signal DATA as image data corresponding to each of the 384 data lines, so that 2 m = 64 gray scale positive and negative gray scales Of the voltages VP1 to VP64 and VN1 to VN64, one gray scale voltage VPx, VNx corresponding to the logic of the data signal DATA is alternately changed in polarity every second horizontal period and is 2n-1 (odd number) (n = 1 to 192). ) And the 2n (even number) data lines are alternately output. The data signal DATA is serial / parallel converted to correspond to each of the 384 data lines, and is further converted to one horizontal line. A preceding stage in which the polarity is alternately changed for each period, and the 2n-1st data line and the 2nth data line perform digital / analog conversion to alternate grayscale voltages VPx and VNx and output the grayscale voltages VPx and VNx. Unit 10, 384 voltage-follower-connected operational amplifiers 20 that output the grayscale voltages VPx and VNx from the preceding-stage circuit unit 10 with increased driving capability in correspondence with 384 data lines, and oscillation of the operational amplifier 20 And a phase compensation capacitance element 30 for preventing the above.
[0007]
Next, the operation when the data driver 100 is connected to the liquid crystal panel will be described with reference to FIG. In one horizontal period, the polarity control signal POL is supplied at a “high” level to the preceding-stage circuit unit 10, and m = 6-bit data signals DATA corresponding to 384 data lines are fetched serially. In parallel with the strobe signal STB, the analog data is converted into one of the 64 grayscale voltages VP1 to VP64 corresponding to the (2n-1) th data line, and is converted into an analog signal. The grayscale voltages VN1 to VN64 of 64 grayscales are converted into one of the grayscale voltages VNx corresponding to the 2n-th data line, and the operational capability of each operational amplifier 20 increases the drive capability of each grayscale voltage VPx and VNx. The outputs S1, S2,..., S384 are supplied to the corresponding data lines of the liquid crystal panel.
[0008]
In the next one horizontal period, the polarity control signal POL is supplied at a “low” level to the preceding-stage circuit unit 10, and m = 6-bit data signals DATA corresponding to 384 data lines are serially captured and internally. Are converted in parallel, and in synchronization with the strobe signal STB, are analog-converted into one of the 64 gradation voltages VN1 to VN64 corresponding to the (2n−1) th data line, and The analog voltage is converted into one of the 64 gradation voltages VP1 to VP64 corresponding to the 2n-th data line, and the operational amplifier 20 increases the driving capability of each gradation voltage VPx, VNx. , S384 are supplied to the corresponding data lines of the liquid crystal panel.
[0009]
[Problems to be solved by the invention]
By the way, as described above, the phase compensation capacitance element 30 for preventing oscillation of the operational amplifier 20 is used. A case where an N-well capacitance element is used as the phase compensation capacitance element 30 will be described below. As shown in FIG. 6, in the N-well capacitance element, an N ⁺ diffusion layer 13 is formed in an N well layer 12 formed in a P-type semiconductor substrate 11, and a gate is provided on the N well layer 12 between the N ⁺ diffusion layers 13. A gate electrode 14 is formed via an oxide film, a gate-side terminal 15 is connected to the gate electrode 14, and a well-side terminal 16 is connected to the N ⁺ diffusion layer. This N-well capacitance element has a voltage dependency as shown in FIG. That is, when a voltage is applied to the gate-side terminal 15 and the well-side terminal 16, the capacity is maximized at a positive voltage equal to or higher than the threshold voltage with the well-side terminal 16 as a reference potential, and the capacity is reduced when the voltage is lower than the threshold voltage. The capacitance becomes minimum when the following negative voltage is reached.
[0010]
On the other hand, the operational amplifier 20 used in the data side driver 100 outputs the positive polarity gray scale voltage VPx and the negative polarity gray scale voltage VNx from each output S1, S2,. A device that can output both a rising waveform and a falling waveform at high speed is used. As an example of a specific circuit, for example, an operational amplifier 20 shown in FIG. 8 is used. The operational amplifier 20 shown in FIG. 8 is described in Japanese Patent Application Laid-Open No. 9-93055. In FIG. 8, the phase compensation capacitance element 30 is connected to the differential stage output of the operational amplifier 20, that is, between the gate of the MOS transistor M14 and the output terminal Vout, but between the gate of the MOS transistor M14 and the output terminal Vout. As shown in FIG. 9, the potential difference becomes larger on the positive side when the falling waveform is output with the output terminal Vout as the reference potential, and becomes smaller on the negative side when the rising waveform is output. Therefore, when the N-well capacitance element shown in FIG. 6 is used as the phase compensation capacitance element 30, the large positive potential difference between the gate of the MOS transistor M14 and the output terminal Vout causes the N-well capacitance element when a falling waveform is output. A positive voltage is applied between the gate side terminal 15 and the well side terminal 16 with the well side terminal 16 as a reference potential, and when a rising waveform is output, a small negative potential difference between the gate of the MOS transistor M14 and the output terminal Vout becomes In order to apply a negative voltage between the gate side terminal 15 and the well side terminal 16 of the N-well capacitive element with the well side terminal 16 as a reference potential, the gate side terminal 15 is connected to the gate of the MOS transistor M14, The side terminal 16 is connected to the output terminal Vout. In FIG. 8, the phase compensation capacitance element 30 is shown as an N-well capacitance element in which the gate side is indicated by a thick line and the well side is indicated by a thin line.
[0011]
When the N-well capacitance element is used as the phase compensation capacitance element as described above, when the capacitance value of the phase compensation capacitance element is determined in accordance with the capacitance value required at the time of output of the falling waveform, when the rising waveform is output May be smaller than the required capacitance value. In the worst case, the operational amplifier 20 oscillates. Conversely, if the capacitance value is determined according to the capacitance value required when outputting the rising waveform, the capacitance value when outputting the falling waveform may be larger than the required capacitance value. In this case, there is a disadvantage that the slew rate at the time of outputting the falling waveform of the operational amplifier 20 is reduced. In addition, it is necessary to make the capacitance value as small as possible from the viewpoint of reducing the chip area of the driver IC, and it is contrary to this that the capacitance value becomes larger than the required capacitance value.
[0012]
SUMMARY OF THE INVENTION Accordingly, the present invention has been made to solve the above-mentioned problems, and it is desirable to change the capacitance value of a phase compensation capacitance element composed of an N-well capacitance element connected to an operational amplifier when a rising waveform is output and when a falling waveform is output. It is an object of the present invention to provide a driving circuit of a liquid crystal display device which can provide a necessary and appropriate capacitance value at each time.
[0013]
[Means for Solving the Problems]
(1) A driving circuit for a liquid crystal display device according to the present invention includes a liquid crystal display device including an operational amplifier connected to a data line of a liquid crystal panel, and a phase compensation capacitive element including an N-well capacitive element connected to the operational amplifier. The driving circuit of the above has two sets of phase compensation capacitance elements having different capacitance values, and when the operational amplifier outputs a falling waveform, the phase of the two phase compensation capacitance elements having the larger capacitance value is output. When the compensating capacitive element is connected and the operational amplifier outputs a rising waveform, the phase compensating capacitive element having a small capacitance value of the pair of phase compensating capacitive elements corresponds to the phase compensating capacitive element having a large capacitive value. It is characterized in that the terminals of the N-well capacitance element are connected in the opposite direction.
(2) In the driving circuit for a liquid crystal display device according to the present invention, in the above item (1), the operational amplifier outputs a rising waveform and a falling waveform alternately.
(3) The driving circuit for a liquid crystal display device according to the above item (2), wherein the set of two operational amplifiers that alternately output a rising waveform and a falling waveform between an odd data line and an even data line are provided. A pair of phase compensation capacitive elements are connected alternately.
(4) The driving circuit for a liquid crystal display device according to the above item (2), wherein in the operational amplifier corresponding to one data line for outputting a rising waveform and a falling waveform, one pair of the two operational amplifiers is provided. The phase compensation capacitance element is connected alternately.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the data side driver 200 using the dot inversion driving method of the first embodiment based on the present invention will be described as having the ability to drive 384 data lines of a liquid crystal panel and display 64 gradations. This will be described with reference to FIG. Note that the same parts as those of the data side driver 100 shown in FIG. 4 are denoted by the same reference numerals, and redundant description is omitted.
The data-side driver 200 supplies m = 6 bits of data signal DATA as image data corresponding to each of the 384 data lines, so that 2 m = 64 gray scale positive and negative gray scales Of the voltages VP1 to VP64 and VN1 to VN64, one gray scale voltage VPx, VNx corresponding to the logic of the data signal DATA is alternately changed in polarity every second horizontal period and is 2n-1 (odd number) (n = 1 to 192). ) And the 2n (even) th data line are alternately output. The pre-stage circuit section 10, 384 voltage follower-connected operational amplifiers 20, and 192 phase amplifiers are provided. Compensating capacitance elements 30 and 40 and 192 changeover switches 50 and 60 are provided. Each of the phase compensation capacitance elements 30 and 40 is configured by an N-well capacitance element shown in FIG. The phase compensation capacitance element 30 is connected to the gate terminal 15 of the MOS transistor M14 of the operational amplifier 20 when the falling waveform is output, of the two operational amplifiers 20 corresponding to the (2n-1) th and 2nth data lines. The well side terminal 16 is connected to the output terminal Vout via the changeover switches 50 and 60, and the capacitance value is set to a level at which the operational amplifier 20 does not oscillate when the falling waveform is output. The phase compensation capacitive element 40 has the well-side terminal 16 connected to the gate of the MOS transistor M14 of the operational amplifier 20 when the rising waveform is output, of the two operational amplifiers 20 corresponding to the (2n-1) th and 2nth data lines. , And the output terminal Vout, the gate side terminal 15 is connected via the changeover switches 50 and 60, and the capacitance value is set to a level at which the operational amplifier 20 does not oscillate when the rising waveform is output. At this time, the capacitance value of the phase compensation capacitance element can be smaller when the rising waveform is output than when the falling waveform is output, so that the well side terminal 16 is connected between the gate side terminal 15 and the well side terminal 16. When the positive voltage is applied with reference to the reference potential, the phase compensation capacitance element 40 is set smaller than the phase compensation capacitance element 30. The changeover switches 50 and 60 are switched by an externally supplied polarity control signal POL.
[0015]
Next, an operation when the data side driver 200 is connected to the liquid crystal panel will be described with reference to FIG. In one horizontal period, the polarity control signal POL is supplied at a “high” level to the preceding-stage circuit unit 10, and m = 6-bit data signals DATA corresponding to 384 data lines are fetched serially. In parallel with the strobe signal STB, the analog data is converted into one of the 64 grayscale voltages VP1 to VP64 corresponding to the (2n-1) th data line, and is converted into an analog signal. The grayscale voltages VN1 to VN64 of 64 grayscales are converted into one of the grayscale voltages VNx corresponding to the 2n-th data line, and the operational capability of each operational amplifier 20 increases the drive capability of each grayscale voltage VPx and VNx. The outputs S1, S2,..., S384 are supplied to the corresponding data lines of the liquid crystal panel. At this time, the polarity control signal POL is supplied to each of the changeover switches 50 and 60 at a “high” level, the phase compensation capacitance element 40 is connected to the operational amplifier 20 corresponding to the (2n−1) -th data line, and the 2n-th data line is connected. The phase compensation capacitance element 30 is connected to the operational amplifier 20 corresponding to the data line.
[0016]
In the next one horizontal period, the polarity control signal POL is supplied at a “low” level to the preceding-stage circuit unit 10, and m = 6-bit data signals DATA corresponding to 384 data lines are serially captured and internally. Are converted in parallel, and in synchronization with the strobe signal STB, are analog-converted into one of the 64 gradation voltages VN1 to VN64 corresponding to the (2n−1) th data line, and The analog voltage is converted into one of the 64 gradation voltages VP1 to VP64 corresponding to the 2n-th data line, and the operational amplifier 20 increases the driving capability of each gradation voltage VPx, VNx. , S384 are supplied to the corresponding data lines of the liquid crystal panel. At this time, the polarity control signal POL is supplied at a “low” level to each of the changeover switches 50 and 60, the phase compensation capacitance element 30 is connected to the operational amplifier 20 corresponding to the (2n−1) -th data line, and the 2n-th The phase compensation capacitance element 40 is connected to the operational amplifier 20 corresponding to the data line.
[0017]
As described above, as described in the first embodiment, the phase compensation capacitance element 30 including the N-well capacitance element whose capacitance value is set for the output of the falling waveform and the N for which the capacitance value is set for the output of the rising waveform. The gate-side terminal and the well-side terminal of the N-well capacitance element are connected in anti-parallel to the phase compensation capacitance element 40 composed of the well capacitance element via the changeover switches 50 and 60. Of the two operational amplifiers 20 corresponding to the (2n-1) -th and 2n-th data lines, the phase compensation capacitance element 40 is connected to the operational amplifier 20 when the rising waveform is output, and when the falling waveform is output. The phase compensation capacitance element 30 is connected to the operational amplifier 20 of FIG. As a result, it is possible to set the capacitance value of the N-well capacitance element suitable at the time of output of the rising waveform and the falling waveform, and the operational amplifier oscillates because the capacitance value is too small. The inconvenience that the slew rate is reduced can be prevented, and the chip area of the data side driver can be reduced.
[0018]
Next, the data-side driver 300 using the line inversion driving method of the second embodiment, which drives 384 data lines of the liquid crystal panel and has a capability of displaying 64 gradations, will be described with reference to FIG. explain. Note that the same parts as those of the data-side driver 200 shown in FIG. 1 are denoted by the same reference numerals, and redundant description will be omitted. The data-side driver 300 is used in a common inversion driving method in which the polarity is inverted by changing the common voltage Vcom every one horizontal period and AC driving is performed, so that two types of grayscale voltages of positive polarity and negative polarity are unnecessary. , And 384 data lines, m = 6-bit data signal DATA is supplied as image data, whereby 2m = 64 gradations of gradation voltages V1 to V64 of data signal DATA One grayscale voltage Vx corresponding to logic is output to each data line for each horizontal period, and serial / parallel conversion of the data signal DATA is performed for each of the 384 data lines, and the data signal DATA is output for each horizontal period. The pre-stage circuit section 70 for digital / analog conversion into a gray scale voltage Vx and outputs the same, 384 voltage follower-connected operational amplifiers 20, and 384 phase compensation capacitors for each It includes a child 30, 40, and each 384 of the changeover switch 80, 90. Each of the phase compensation capacitance elements 30 and 40 is configured by an N-well capacitance element shown in FIG. In each phase compensation capacitance element 30, when the falling waveform of each operational amplifier 20 is output, the gate side terminal 15 is connected to the gate of the MOS transistor M14, the well side terminal 16 is connected to the output terminal Vout, and the changeover switches 80 and 90. And the capacitance value is set to a level at which each operational amplifier 20 does not oscillate when outputting a falling waveform. In each phase compensation capacitance element 40, the gate side terminal 15 is connected to the output terminal Vout and the well side terminal 16 is connected to the gate of the MOS transistor M14 via the changeover switches 80 and 90 when the rising waveform of each operational amplifier 20 is output. The capacitance value is set to a level at which each operational amplifier 20 does not oscillate when outputting a rising waveform. At this time, the capacitance value of the phase compensation capacitance element can be smaller when the rising waveform is output than when the falling waveform is output, so that the well side terminal 16 is connected between the gate side terminal 15 and the well side terminal 16. When the positive voltage is applied with reference to the reference potential, the phase compensation capacitance element 40 is set smaller than the phase compensation capacitance element 30. The changeover switches 80 and 90 are switched by an externally supplied polarity control signal POL.
[0019]
Next, the operation when the data driver 300 is connected to the liquid crystal panel will be described. In one horizontal period, the polarity control signal POL is supplied at a “high” level to the preceding-stage circuit unit 70, and m = 6-bit data signals DATA corresponding to 384 data lines are serially captured. It is converted into parallel, and in synchronization with the strobe signal STB, is analog-converted into one gradation voltage Vx among 64 gradation voltages V1 to V64 corresponding to each data line. The driving capability of the adjustment voltage Vx is increased, and is supplied to corresponding data lines of the liquid crystal panel as outputs S1, S2,..., S384. At this time, a negative voltage is supplied to the common voltage Vcom, and each operational amplifier 20 outputs a rising waveform. At this time, the polarity control signal POL is supplied at a “high” level to each of the changeover switches 80 and 90, and the phase compensation capacitance element 40 is connected to each of the operational amplifiers 20.
[0020]
In the next one horizontal period, the polarity control signal POL is supplied at the “low” level to the preceding-stage circuit unit 70, and the m = 6-bit data signal DATA corresponding to each of the 384 data lines is serially captured and internally. Are converted in parallel, and in synchronism with the strobe signal STB, are analog-converted into one of the 64 gradation voltages V1 to V64 corresponding to each data line, and are converted by the respective operational amplifiers 20. The driving capability of each gray scale voltage Vx is increased, and is supplied to each corresponding data line of the liquid crystal panel as outputs S1, S2,..., S384. At this time, a positive voltage is supplied to the common voltage Vcom, and each operational amplifier 20 outputs a falling waveform. At this time, the polarity control signal POL is supplied to each of the changeover switches 80 and 90 at a “low” level, and the operational amplifier 20 is connected to the phase compensation capacitance element 30.
[0021]
As described above, as described in the second embodiment, the phase compensation capacitance element 30 composed of the N-well capacitance element whose capacitance value is set for the output of the falling waveform, and the N equal to the capacitance value set for the output of the rising waveform. The gate-side terminal and the well-side terminal of the N-well capacitance element are connected in anti-parallel to the phase compensation capacitance element 40 composed of the well capacitance element via the changeover switches 80 and 90. Then, the phase compensation capacitance element 40 is connected to the operational amplifier 20 corresponding to each data line when outputting a rising waveform, and the phase compensation capacitance element 30 is connected when outputting a falling waveform. As a result, it is possible to set a capacitance value of the N-well suitable for each output of the rising waveform and the falling waveform. If the capacitance value is too small, the operational amplifier oscillates, or conversely, the slew rate is too large. The inconvenience of being small can be prevented.
[0022]
【The invention's effect】
According to the drive circuit of the liquid crystal display device according to the present invention, the phase compensation capacitance element composed of the N-well capacitance element connected to the operational amplifier is constituted by a pair of phase compensation capacitance elements having different capacitance values, When the operational amplifier outputs a falling waveform, a phase compensating capacitive element having a larger capacitance value is connected among the pair of phase compensating capacitive elements, and when the operational amplifier outputs a rising waveform, a pair of phase compensating capacitive elements is output. Since the phase compensation capacitance element having a small capacitance value among the phase compensation capacitance elements is connected to the phase compensation capacitance element having a large capacitance value with the terminal of the N-well capacitance element being in the opposite direction, the operational amplifier may be connected because the capacitance value is too small. Can be prevented from oscillating, and conversely, the inconvenience that the sullate is too small to be too large can be prevented. Further, a drive of a liquid crystal display device in which a pair of phase compensation capacitive elements are alternately connected to a pair of operational amplifiers that alternately output a rising waveform and a falling waveform between an odd data line and an even data line. In the circuit, the chip area can be reduced.
[Brief description of the drawings]
FIG. 1 is a main part circuit diagram of a data side driver according to a first embodiment of the present invention.
FIG. 2 is a main part circuit diagram of a data side driver according to a second embodiment of the present invention.
FIG. 3 is a schematic configuration diagram of a liquid crystal display device.
FIG. 4 is a main part circuit diagram of a conventional data side driver.
FIG. 5 is a timing chart showing a circuit operation of the data side driver of FIG. 4;
FIG. 6 is a diagram showing a schematic cross section of an N-well capacitance element.
FIG. 7 is a view showing a bias voltage dependence characteristic of the N-well capacitance element shown in FIG. 6;
FIG. 8 is a circuit diagram of an example of an operational amplifier used in the data side driver of FIGS. 1, 2 and 5;
9 is a diagram showing a change in potential at a connection point of an N-well capacitance element of the operational amplifier shown in FIG. 8;
[Explanation of symbols]
200, 300 Data side driver 10, 70 Pre-stage circuit unit 20 Operational amplifier 30, 40 Phase compensation capacitance element 50, 60, 80, 90 Changeover switch

Claims (4)

In a drive circuit of a liquid crystal display device including an operational amplifier connected to a data line of a liquid crystal panel, and a phase compensation capacitive element including an N-well capacitive element connected to the operational amplifier,
A pair of phase compensation capacitance elements having different capacitance values,
When the operational amplifier outputs a falling waveform, a phase compensating capacitive element having a large capacitance value among the pair of phase compensating capacitive elements is connected, and when the operational amplifier outputs a rising waveform, A phase compensating capacitance element having a small capacitance value among a pair of phase compensating capacitance elements is connected to the phase compensating capacitance element having a large capacitance value with the terminal of the N-well capacitance element in a reverse direction. Circuit for driving a liquid crystal display device. 2. The driving circuit according to claim 1, wherein the operational amplifier outputs a rising waveform and a falling waveform alternately. The pair of phase compensation capacitive elements are alternately connected to a pair of the operational amplifiers that alternately output the rising waveform and the falling waveform between the odd data line and the even data line. 3. The driving circuit for a liquid crystal display device according to claim 2, wherein 3. A pair of phase compensation capacitive elements are alternately connected to one operational amplifier corresponding to one data line outputting the rising waveform and the falling waveform. Drive circuit for liquid crystal display device.

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