JP2011035282A - Pattern forming method using lift-off method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a pattern forming method using a lift-off method, in which burr does not occur around edges of a conductive pattern when the pattern forming method using a lift-off method is employed. <P>SOLUTION: First, a groove 2 is formed within an area of a surface of a wafer substrate 1 where edges of a conductive pattern 6 are located. Next, a resist 3 having an opening 3a where the groove 2 is exposed is formed on the wafer substrate 1. Then, a conductive film 5 is formed on the wafer substrate 1 and the resist 3 exposed from the opening 3a. After that, the resist 3 is removed and the conductive pattern 6 is formed on the wafer substrate 1. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a pattern forming method using a lift-off method.

  2. Description of the Related Art Conventionally, in a semiconductor device manufacturing process, there is a technique for forming a wiring pattern on a semiconductor substrate using a lift-off method. A pattern forming method by a general lift method will be described as follows.

  First, a positive resist is applied to the wafer substrate. Next, the mask is aligned, exposed, and developed. Thereby, the resist of the part irradiated with light melt | dissolves. Next, in the above state, a desired metal film is formed on the entire surface of the wafer substrate by using a sputtering method or a vapor deposition method. Finally, the wafer substrate is immersed in a removing solution, or a stripping solution is applied to the surface of the wafer substrate at a high pressure to remove the unnecessary portion of the metal film together with the resist.

  For example, Patent Documents 1 and 2 exist as conventional techniques related to a pattern forming method using the lift-off method.

JP-A-5-62948 JP 2000-181077 A

  In a conventional pattern forming method using a lift-off method, a metal film on a resist to be lifted off and a metal film on a wafer substrate on which a pattern is to be formed are continuously formed. For this reason, even when the wafer substrate is immersed in the removal liquid or when the peeling liquid is applied to the surface of the wafer substrate at a high pressure, the removal liquid does not react uniformly during lift-off. Therefore, there is a problem that the metal film on the side surface of the resist is cut in the middle, and a burr-like defect occurs near the edge of the pattern.

  Accordingly, an object of the present invention is to provide a pattern forming method using the lift-off method that does not generate burrs near the edge of the conductive pattern even when the pattern forming method using the lift-off method is performed. To do.

  In order to achieve the above object, the pattern forming method using the lift-off method according to claim 1 according to the present invention includes: (A) forming a groove in the surface of the base on which the edge portion of the conductive pattern is located. (B) forming a film to be removed having an opening of a predetermined pattern exposing the groove on the base; and (C) the base exposed from the opening and the planned removal. A step of forming a conductive film on the film; and (D) a step of forming the conductive pattern on the base by removing the film to be removed after the step (C). I have.

  In the pattern forming method using the lift-off method according to the first aspect of the present invention, the groove is formed in the surface of the base on which the edge portion of the conductive pattern is located. Then, a film to be removed having an opening through which the groove is exposed is formed on the base. Then, a conductive film is formed on the base exposed from the opening and the film to be removed. Finally, the conductive pattern is formed on the base by removing the planned removal film.

  As described above, the thickness of the conductive pattern is locally reduced in the groove. Therefore, the conductive pattern can be easily formed by lift-off processing without generating burrs at the edge of the conductive pattern.

  Further, since burrs are not generated at the edge portion of the conductive pattern, the dimensional accuracy of the conductive pattern formed on the base can be improved. Furthermore, the dimensional variation of each conductive pattern can be suppressed.

  In the conductive pattern to be formed, a conductive film is also formed in the groove. Therefore, the anchor effect in the groove is exhibited. Therefore, the anchor effect can prevent the conductive pattern from being peeled off from the base, and as a result, the reliability of the finished product is improved.

It is process sectional drawing for demonstrating the pattern formation method using the lift-off method which concerns on this invention. It is process sectional drawing for demonstrating the pattern formation method using the lift-off method which concerns on this invention. It is process sectional drawing for demonstrating the pattern formation method using the lift-off method which concerns on this invention. It is process sectional drawing for demonstrating the pattern formation method using the lift-off method which concerns on this invention. It is process sectional drawing for demonstrating the pattern formation method using the lift-off method which concerns on this invention. It is process sectional drawing for demonstrating the pattern formation method using the lift-off method which concerns on this invention. It is process sectional drawing for demonstrating the pattern formation method using the conventional lift-off method. It is process sectional drawing for demonstrating the pattern formation method using the conventional lift-off method. It is process sectional drawing for demonstrating the pattern formation method using the conventional lift-off method. It is process sectional drawing for demonstrating the pattern formation method using the conventional lift-off method. It is sectional drawing which shows the form which forms a some groove | channel. It is a figure which shows an example of the planar view shape of the electroconductive pattern 6. FIG. It is a top view explaining the form which forms a some groove | channel.

  Hereinafter, the present invention will be specifically described with reference to the drawings showing embodiments thereof.

<Embodiment>
A pattern forming method using the lift-off method according to the present embodiment will be described with reference to process cross-sectional views of FIGS.

  First, a photoengraving process and an etching process are performed on the surface of a semiconductor substrate (hereinafter referred to as a wafer substrate) 1. Thereby, as shown in FIG. 1, a groove 2 having a depth a and a width b is formed in the surface of the wafer substrate 1.

  Here, the groove 2 is formed in the surface of the wafer substrate 1 where the edge portion of the conductive pattern 6 to be formed is located. Furthermore, the shape of the groove 2 in plan view is a shape along the outline of the conductive pattern 6 to be formed from now.

  In the present embodiment, a case where a wiring pattern is formed as the conductive pattern 6 will be described. In this case, the groove 2 formed in FIG. 1 is formed at a location on the substrate 1 where the edge portion of the wiring pattern to be arranged is located, and the shape of the groove 2 in plan view is It is a shape along the contour of the pattern.

  Next, as shown in FIG. 2, a positive resist (which can be grasped as a film to be removed) 3 is applied and formed on the wafer substrate 1 so as to fill the inside of the groove 2. Here, it is not necessary for the resist 3 to completely fill the inside of the groove 2. That is, the resist 3 may be formed on the side surface and the bottom surface in the groove 2 without completely closing the groove 2.

  Next, a mask 4 having an opening 4 a having a predetermined pattern shape is positioned and arranged above the wafer substrate 1. Here, the predetermined pattern shape is the same pattern shape as the conductive pattern 6 to be formed. After the mask 4 is disposed, the light L is exposed to the resist 3 through the mask 4 as shown in FIG. Thereby, the area | region of the register | resistor 3 irradiated with the light L through the opening part 4a is developed.

  That is, the resist 3 in the portion irradiated with the light L is dissolved by the exposure and development, and an opening 3a is formed in the resist 3 as shown in FIG. Moreover, the groove | channel 2 is exposed in the edge part of the said bottom face from the bottom face of the opening part 3a in planar view. In addition, the planar view shape of the bottom face part of the opening 3a is the same as the pattern shape of the conductive pattern 6 to be formed later.

  Here, when exposure and development are ideally performed, the resist 3 in the groove 2 is removed as shown in FIG. However, the resist 3 may partially remain on the bottom and side surfaces in the groove 2. This is because the partially remaining resist 3 is removed by a subsequent lift-off process.

  In the above description, the positive type is referred to as the resist 3. However, the resist 3 may naturally be a negative type. However, when a negative resist is employed, the irradiation region of the light L needs to be reversed from that in FIG. That is, when a negative resist is employed, the resist 3 in the portion irradiated with the light L is cured, and the resist 3 in the non-irradiated region of the light L is removed during development.

  Next, a sputtering method or a vapor deposition method is performed on the entire surface of the wafer substrate 1 on which the resist 3 having the opening 3a is formed. Thereby, as shown in FIG. 5, the conductive film 5 is formed on the wafer substrate 1 exposed from the opening 3a, on the side surface of the opening 3a, on the bottom surface / side surface of the groove 2, and on the resist 3. The

  Here, it is desirable that the conductive film 5 is formed with a thickness that does not completely fill the groove 2. For example, the film thickness Tm of the conductive film 5 is desirably smaller than half of the width b of the groove 2. That is, it is desirable to satisfy the relationship “b / 2 <Tm”.

  In the formation of the conductive film 5, as described above, the conductive film 5 is formed not only on the wafer substrate 1 but also in the groove 2 formed previously. However, in the groove 2, the coverage of the conductive film 5 is deteriorated. Therefore, the thickness of the conductive film 5 is locally reduced inside the groove 2.

  When the conductive pattern 6 is a wiring of a semiconductor element, the conductive film 5 is generally mainly made of copper, aluminum, aluminum oxide, etc., but other metal films are also used. I do not care.

  After the formation of the conductive film 5, the structure shown in FIG. 5 is immersed in a resist stripping solution. Alternatively, a resist stripping solution is sprayed at a high pressure on the structure shown in FIG. As a result, as shown in FIG. 6, the resist 3 is removed together with the conductive film 5 formed on the resist 3, and a conductive pattern 6 to be a wiring is formed on the wafer substrate 1. That is, the conductive pattern 6 is formed on the wafer substrate 1 by the lift-off process.

  Here, in the lift-off process, the conductive film 5 is broken and separated inside the groove 2. This is because, as described above, the thickness of the conductive film 5 is locally reduced inside the groove 2.

  Next, problems that occur in the conventional pattern formation method using the lift-off method and the effects of the pattern formation method using the lift-off method according to the present embodiment will be described.

  In the conventional method, as shown in FIG. 7, the resist 3 is formed on the wafer substrate 1 without forming the groove 2 according to the present invention in the surface of the wafer substrate 1. Then, exposure / development processing is performed on the resist 3. As a result, an opening 3a is formed in the resist 3 as shown in FIG. Next, the conductive film 5 is formed on the upper surface and side surfaces of the resist 3 and on the wafer substrate 1 exposed from the bottom surface of the opening 3a (see FIG. 9). Thereafter, the conductive film 5 formed on the resist 3 is removed together with the resist 3 by a lift-off process. Through this process, a conductive pattern 6 having a predetermined shape is formed on the wafer substrate 1 as shown in FIG.

  Here, in the conventional method, a burr 6p is generated at the end of the conductive pattern 5 as shown in FIG. 10 because the resist stripping solution does not react uniformly with the resist 3 or the like. The formation of the burr 6p causes various problems in the finished product, such as a cause of peeling of the conductive pattern 5, variation in pattern dimensions, and pattern defects.

  Therefore, in the method of the present invention, the groove 2 is formed in advance along the contour of the conductive pattern in the surface of the wafer substrate 1 where the edge portion of the conductive pattern 6 is located (FIG. 1). Thereafter, a resist 3 is formed on the wafer substrate 1, and openings 3a having a predetermined pattern in which the grooves 2 are exposed are formed in the resist 3 (FIGS. 2, 3 and 4). Further, a conductive film 5 is formed on the wafer substrate 1 including the resist 3 (FIG. 5), and then a conductive pattern 6 is formed on the wafer substrate 1 by a lift-off process (FIG. 6).

  Therefore, the thickness of the conductive pattern 6 is locally reduced in the groove 2 formed at the edge position of the conductive pattern 6. Therefore, the conductive pattern 2 is separated and peeled inside the groove 2 by the lift-off process. Therefore, the conductive pattern 6 can be easily formed by lift-off processing without generating burrs at the edge of the conductive pattern 6.

  Moreover, since burrs are not generated at the edge portion of the conductive pattern 6, the dimensional accuracy of the formed conductive pattern 6 can be improved, and the dimensional variation of each conductive pattern 6 can be suppressed.

  Further, the conductive film 5 is separated and peeled inside the groove 2. Therefore, the end portion of the conductive pattern 6 is formed in the groove 2. Therefore, the anchor effect in the groove 2 is exhibited. Therefore, the anchor effect can prevent the conductive pattern 6 from being peeled off from the wafer substrate 1, and as a result, the reliability of the finished product is improved.

  In the above, one groove 2 is formed corresponding to each edge portion of the conductive pattern 6. For example, in the configuration example of FIG. 6, a total of two right and left edge portions of the conductive pattern 6 are disclosed. In this case, one groove 2 (a total of two grooves 2 as shown in FIG. 6) is formed corresponding to each edge portion.

  However, the number of grooves 2 is not limited to one for each edge, and at least two or more may be formed corresponding to each edge portion of the conductive pattern 6 (corresponding to each edge portion, A groove group composed of a plurality of grooves 2 is formed). FIG. 11 is a modification of FIG. 1, and the shape of the conductive pattern 6 formed in plan view is the same as that described with reference to FIGS. In FIG. 11, two grooves 2 (a total of four grooves 2 as shown in FIG. 11) are formed corresponding to each edge portion of the conductive pattern 6 to be formed later.

  Here, adjacent grooves 2 constituting each groove group are formed apart by a minute distance in plan view. Furthermore, the planar view shape of each groove 2 constituting each groove group is the same as the contour shape of the corresponding edge portion.

  For example, as shown in the plan view of FIG. 12, it is assumed that the conductive pattern 6 has a linear shape. The conductive pattern 6 has two edge portions 6a and 6b, and the contours of the edge portions 6a and 6b are linear. In this case, as shown in FIG. 13 which is a plan view, a plurality of (two in FIG. 13) grooves 2a are formed corresponding to the edge portion 6a, and a plurality of (two in FIG. 13) corresponding to the edge portion 6b. Two) grooves 2b are formed.

  Here, in plan view, the grooves 2a are formed with a predetermined distance apart, and the grooves 2b are also formed with a predetermined distance apart. Further, each groove 2a formed corresponding to the edge portion 6a has the same pattern as the outline in plan view of the edge portion 6a (in the case of the configuration example of FIG. 12), and the edge portion 6b Each of the grooves 2b formed correspondingly has the same pattern as the outline in plan view of the edge portion 6b (in the case of the configuration example of FIG. 12, it is linear).

  When a plurality of grooves 2 are formed corresponding to each edge portion, all the grooves 2 are exposed from the bottom surface of the opening 3 a of the resist 3. In addition, the outermost groove | channel 2 in each edge part is exposed in the corner part of the bottom face of the said opening part 3a. As described above, since all the grooves 2 are exposed from the openings 3a of the resist 3, in the film forming process of the conductive film 5 which is a constituent material of the conductive pattern 6, the conductive film 5 is disposed inside all the grooves 2. Formed.

  As described above, by forming at least two or more grooves 2 corresponding to each edge portion of the conductive pattern 6, there are a plurality of locations where the film thickness is locally reduced for each edge. Therefore, even if the lift-off process is performed, it is possible to reliably prevent burrs of the conductive pattern 6 from occurring. Further, since the anchor effect is exhibited at a plurality of points for each edge, peeling of the conductive pattern 6 from the wafer substrate 1 can be reliably prevented.

  When the shape of the conductive pattern 6 in FIG. 6 in plan view is FIG. 12, the shape of the groove 2 formed in FIG. 1 is one groove 2a in FIG. 13, and the groove 2b in FIG. This is a configuration in which there is one.

  In the above embodiment, the case where the conductive pattern 6 such as the wiring is formed on the wafer substrate 1 using the lift-off method has been mentioned. However, the present invention can be applied to the case where the conductive pattern 6 is formed on an insulating film such as an interlayer insulating film by using the lift-off method. In this case, needless to say, the groove 2 is formed in the surface of the insulating film. It can be understood that the substrate or layer on which the conductive pattern 6 is formed is the “underlying”.

  The conductive pattern 6 is not limited to wiring, and refers to all conductive parts such as electrodes and pads.

  DESCRIPTION OF SYMBOLS 1 Wafer substrate, 2, 2a, 2b groove | channel, 3 resist, 3a (resist) opening part, 4 mask, 4a (mask) opening part, 5 conductive film, 6 conductive pattern, 6a, 6b edge part, 6p Bali, L Light.

Claims (4)

(A) forming a groove in the surface of the base on which the edge portion of the conductive pattern is located;
(B) forming a film to be removed having an opening of a predetermined pattern exposing the groove on the base;
(C) forming a conductive film on the base exposed from the opening and the film to be removed;
(D) After the step (C), the step of forming the conductive pattern on the base by removing the to-be-removed film is provided.
A pattern forming method using a lift-off method. The step (A)
Forming the groove along the contour of the conductive pattern;
The pattern forming method using the lift-off method according to claim 1. The step (C)
Forming the conductive film having a thickness that does not fill the groove;
A pattern forming method using the lift-off method according to claim 1 or 2. The groove is
At least two or more are formed corresponding to each edge portion of the conductive pattern,
The pattern formation method using the lift-off method according to any one of claims 1 to 3.

Images