JP2008047579A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reliably prevent a plating liquid from entering a part of a connection terminal for plating comprising the periphery of a substrate metal layer formed on an entire surface on a semiconductor wafer, when forming a columnar electrode by electrolytic plating. <P>SOLUTION: An annular seal ring contact 26 made of the same material as a first plating resist film 23 for forming wiring 8 is formed inside a connection terminal 7a, for plating on the upper surface of a substrate metal layer 7 formed on the entire surface of a semiconductor wafer 21. Then, when the columnar electrode 9 is formed in an opening 28a of a second plating resist film 28 by electrolytic plating, a seal ring 27 of a plating tool is brought into contact with the upper surface of the seal ring contact 26 instead of the upper surface of the periphery of the second plating resist film 28. Then, even if a dummy opening of which the outer side is open caused by step exposure is formed at the periphery of the second plating resist film 28, a plating liquid can be prevented reliably from intruding to a part of the connection terminal 7a for plating. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  In a conventional method for manufacturing a semiconductor device called a CSP (chip size package), when a columnar electrode as an external connection electrode is formed on a semiconductor wafer by electrolytic plating, for example, a base formed on the entire surface of the semiconductor wafer A plating resist film having an opening in a portion corresponding to the columnar electrode formation region is formed on the metal layer, and electrolytic plating is performed using the base metal layer as a plating current path, whereby the columnar electrode is formed in the opening of the plating resist film. (For example, refer to Patent Document 1).

JP 2004-349611 A

  In the conventional method for manufacturing a semiconductor device, when forming a plating resist film having an opening in a portion corresponding to the columnar electrode formation region, a negative unexposed plating resist film is formed on the entire surface of the base metal layer. The entire plating resist film is exposed by performing step exposure using an exposure mask for columnar electrode formation of a size corresponding to a plurality of semiconductor devices, and then developed, thereby corresponding to the columnar electrode formation region. An opening is formed in the plating resist film in the portion to be processed.

  By the way, although there is no description in the said patent document 1, in order to use the peripheral part of a base metal layer as a connection terminal part for plating, it is necessary to remove the peripheral part of a plating resist film and to expose the peripheral part of a base metal layer There is. Therefore, step exposure using a columnar electrode forming exposure mask is performed in a state where a light shielding ring is disposed on the upper surface of the peripheral portion of the negative type plating resist film, and then development is performed, thereby corresponding to the columnar electrode forming region. An opening is formed in the plating resist film in the portion, and the peripheral portion of the base metal layer is exposed by removing the peripheral portion of the plating resist film.

  However, in the method of manufacturing a semiconductor device as described above, since the plating resist film just inside the light shielding ring arranged on the upper surface of the peripheral portion of the plating resist film is also step-exposed, the plating just inside the connecting terminal portion for plating is performed. An opening is also formed in the resist film. FIG. 20A shows a plan view of an example of the peripheral portion of the semiconductor wafer in this state, and FIG. 20B shows a cross-sectional view along the line BB.

  As shown in FIGS. 20A and 20B, a base metal layer 42 is formed on the entire top surface of the semiconductor wafer 41, and a plating resist film 43 is formed on the top surface other than the peripheral portion of the base metal layer 42. A circular opening 44 is formed in the plating resist film 43. In this case, an opening 44 a having an open outer side is formed in the peripheral portion of the plating resist film 43 immediately inside the plating connection terminal portion 42 a formed from the peripheral portion of the base metal layer 42.

  On the other hand, when the semiconductor wafer 41 is attached to the plating jig and the feeding member of the plating jig is brought into contact with the plating connection terminal portion 42a, it is necessary to prevent the plating solution from entering the contact portion. Therefore, as shown in FIGS. 21A and 21B, the seal ring 45 of the plating jig is brought into contact with the upper surface of the peripheral portion of the plating resist film 43. If the opened opening 44 a is formed, the opening 44 a cannot be completely covered with the seal ring 45.

  As a result, the plating solution enters the portion of the plating connection terminal portion 42a through the opening 44a in the peripheral portion of the plating resist film 43, and the plating solution is acidic, so the plating connection terminal portion 42a is corroded. There is a problem that stable contact with the plating connection terminal portion 42a by the power supply member of the plating jig cannot be obtained, power supply becomes unstable, and this causes defective plating.

  Therefore, the present invention reliably prevents the penetration of the plating solution into the plating connection terminal portion composed of the peripheral portion of the base metal layer formed on the entire surface of the semiconductor wafer when the columnar electrode is formed by electrolytic plating. An object of the present invention is to provide a method for manufacturing a semiconductor device.

  In order to achieve the above object, the present invention provides a step of forming a base metal layer on the entire surface of a semiconductor wafer, a step of forming an unexposed first plating resist film on the base metal layer, and the first Removing the peripheral portion of the plating resist film and exposing the peripheral portion of the base metal layer to be used as a connecting terminal portion for plating; and exposing and developing the first resist layer Forming a wiring-forming opening, and forming a ring-shaped seal ring contact portion made of the first plating resist film on the inner metal layer inside the plating connection terminal portion; and the seal A seal ring of a plating jig for not plating the peripheral portion of the first plating resist film is brought into contact with the ring contact portion, and the plating jig is connected to the plating connection terminal portion. Forming a wiring on the underlying metal layer in the wiring forming opening of the first plating resist film by performing electroplating in a state where the electric member is in contact with the wiring member. Is.

  According to the present invention, the seal ring contact portion made of the first plating resist film is formed inside the connection terminal portion for plating on the base metal layer formed on the entire surface of the semiconductor wafer. When forming a columnar electrode forming opening in the plating resist film, the peripheral portion of the second plating resist film is removed to expose at least the outer peripheral side of the plating connection terminal portion and the seal ring contact portion, and the columnar shape is formed by electrolytic plating. When forming the electrode, the seal ring of the plating jig can be brought into contact with the seal ring contact portion, and a columnar electrode forming opening having an open outer side is formed in the peripheral portion of the second plating resist film. In addition, it is possible to reliably prevent the plating solution from entering the plating connection terminal portion.

  FIG. 1 shows a cross-sectional view of a semiconductor device manufactured by a manufacturing method as one embodiment of the present invention. This semiconductor device is generally called a CSP and includes a silicon substrate (semiconductor substrate) 1. An integrated circuit (not shown) is provided on the upper surface of the silicon substrate 1, and only two of them are shown in the periphery of the upper surface, but in reality, a large number of connection pads 2 made of an aluminum-based metal or the like are formed on the integrated circuit. Connected and provided.

  An insulating film 3 made of silicon oxide or the like is provided on the upper surface of the silicon substrate 1 excluding the central portion of the connection pad 2, and the central portion of the connection pad 2 is exposed through an opening 4 provided in the insulating film 3. Yes. A protective film 5 made of polyimide resin or the like is provided on the upper surface of the insulating film 3. An opening 6 is provided in the protective film 5 at a portion corresponding to the opening 4 of the insulating film 3.

  A base metal layer 7 made of copper or the like is provided on the upper surface of the protective film 5. A wiring 8 made of copper is provided on the entire upper surface of the base metal layer 7. One end of the wiring 8 including the base metal layer 7 is connected to the connection pad 2 through the openings 4 and 6 of the insulating film 3 and the protective film 5. A columnar electrode 9 made of copper is provided on the upper surface of the connection pad portion of the wiring 8. A sealing film 10 made of an epoxy resin or the like is provided on the upper surface of the protective film 5 including the wiring 8 so that the upper surface is flush with the upper surface of the columnar electrode 9. A solder ball 11 is provided on the upper surface of the columnar electrode 9.

  Next, an example of a method for manufacturing this semiconductor device will be described. First, as shown in FIG. 2, a silicon substrate in a wafer state (hereinafter referred to as a semiconductor wafer 21) is prepared. Here, in FIG. 2, a square region surrounded by vertical lines and horizontal lines is a semiconductor device formation region 22. Therefore, the vertical and horizontal lines shown in FIG. 2 are regions corresponding to dicing streets.

  Next, FIG. 3 shows a sectional view taken along line III-III in FIG. In this case, FIG. 3 is a cross-sectional view of the peripheral portion on the left side of the semiconductor wafer 21 from the left side to the right side, a cross-sectional view of one semiconductor device forming region 22 of the semiconductor wafer 21, and the right side of the semiconductor wafer 21. Sectional drawing of the part of the peripheral part of is shown.

  As shown in FIG. 3, on the semiconductor device formation region 22 of the semiconductor wafer 21, a connection pad 2 made of aluminum metal or the like, an insulating film 3 made of silicon oxide or the like, and a protective film 5 made of polyimide resin or the like are formed. The central portion of the connection pad 2 is exposed through the openings 4 and 6 formed in the insulating film 3 and the protective film 5. Only the insulating film 3 and the protective film 5 are formed on the periphery of the semiconductor wafer 21. In FIG. 2, the openings 4 and 6 of the insulating film 3 and the protective film 5 are not illustrated because they are too small.

  Next, as shown in FIG. 4, a base metal layer 7 is formed on the entire upper surface of the protective film 5 including the upper surface of the connection pad 2 exposed through the openings 4 and 6 of the insulating film 3 and the protective film 5. . In this case, the base metal layer 7 may be only a copper layer formed by electroless plating, or may be only a copper layer formed by sputtering, and a thin film such as titanium formed by sputtering. A copper layer may be formed on the layer by sputtering.

  Next, a positive liquid resist made of a novolac resin is applied to the entire upper surface of the base metal layer 7 to form an unexposed first plating resist film 23. Next, as shown in FIGS. 5 and 6, the peripheral portion of the first plating resist film 23 is removed by the edge rinse method, and the peripheral portion of the base metal layer 7 is used as the plating connection terminal portion 7a. Expose.

  Next, as shown in FIG. 7, the first light shielding ring 24 is disposed on the upper surface of the peripheral portion of the first plating resist film 23. Next, a wiring forming exposure mask 25 having a size corresponding to a plurality (for example, a total of nine in three rows and three columns) of semiconductor device formation regions 22 is prepared. In this case, the wiring forming exposure mask 25 has a portion corresponding to the wiring 8 formation region as the transmission portion 25a and the other portion as the light shielding portion 25b.

  Next, step exposure using the wiring formation exposure mask 25 is performed to expose the entire first plating resist film 23. Then, in the first plating resist film 23 in the portion corresponding to the semiconductor device formation region 22, the region corresponding to the wiring 8 formation region becomes the exposed portion, and the other region becomes the non-exposed portion. In the first plating resist film 23 in the portion corresponding to the periphery of the semiconductor device formation region 22, the region covered with the first light shielding ring 24 is a non-exposed portion, and the other region is an exposure mask 25 for wiring formation. The exposure is performed according to the exposure pattern.

  Next, as shown in FIGS. 8 and 9, when development is performed, in the semiconductor device formation region 22, an opening 23a (in FIG. 8) is formed in the first plating resist film 23 in a portion corresponding to the wiring 8 formation region. (Not shown) is formed. Around the semiconductor device formation region 22, a ring-shaped seal ring contact portion 26 made of the first plating resist film 23 is formed inside the plating connection terminal portion 7 a on the upper surface of the base metal layer 7. A dummy opening 23 b corresponding to the exposure pattern of the wiring forming exposure mask 25 is formed in the first plating resist film 23. In this case, since the seal ring contact portion 26 is formed by a portion covered with the first light shielding ring 24, an opening having an open outer side is not formed on the outer peripheral portion thereof.

  Next, as shown in FIG. 10, the seal ring 27 of the plating jig is brought into contact with the upper half of the upper surface of the seal ring contact portion 26, and the power supply member of the plating jig (on the upper surface of the connecting terminal portion 7a for plating). (Not shown) and copper electroplating is performed, wiring 8 is formed on the upper surface of base metal layer 7 in opening 23a of first plating resist film 23 in semiconductor device formation region 22. . Around the semiconductor device formation region 22, a dummy wiring 8 a is formed on the upper surface of the base metal layer 7 in the dummy opening 23 b of the first plating resist film 23 inside the seal ring contact portion 26. In this case, since the seal ring 27 of the plating jig is in contact with the upper half of the upper surface of the seal ring contact portion 26, no seal failure occurs and no plating failure due to the seal failure occurs. .

  Next, as shown in FIG. 11, the wiring 8, the dummy wiring 8a, the first plating resist film 23, and the seal ring contact portion with the first plating resist film 23 and the seal ring contact portion 26 left as they are. 26 and a negative dry film resist made of an acrylic resin are laminated on the entire upper surface of the connection terminal portion 7a for plating and an unexposed second plating resist film 28 is formed.

  Next, as shown in FIG. 12, a second light shielding ring 29 is disposed on the upper surface of the peripheral portion of the second plating resist film 28. In this case, the inner diameter of the second light shielding ring 29 is somewhat larger than the inner diameter of the seal ring contact portion 26 (that is, the inner diameter of the first light shielding ring 24 shown in FIG. 7). . Next, a columnar electrode forming exposure mask 30 having a size corresponding to a plurality of (for example, a total of nine in three rows and three columns) semiconductor device formation regions 22 is prepared. In this case, the columnar electrode forming exposure mask 30 has a portion corresponding to a connection pad portion (columnar electrode 9 formation region) of the wiring 8 as a light shielding portion 30a and the other portion as a transmission portion 30b.

  Next, step exposure using the columnar electrode forming exposure mask 30 is performed to expose the entire second plating resist film 28. Then, in the second plating resist film 28 in the portion corresponding to the semiconductor device formation region 22, the region corresponding to the connection pad portion (columnar electrode 9 formation region) of the wiring 8 is a non-exposed portion, and the other regions are It becomes an exposure part. In the second plating resist film 28 in the portion corresponding to the periphery of the semiconductor device formation region 22, the region covered by the second light shielding ring 29 is a non-exposed portion, and the other region is an exposure mask for columnar electrode formation. Exposure is performed according to 30 exposure patterns.

  Next, as shown in FIG. 13, when development is performed, in the semiconductor device formation region 22, an opening is formed in the second plating resist film 28 in a portion corresponding to the connection pad (columnar electrode 9 formation region) of the wiring 8. 28a is formed. In the periphery of the semiconductor device formation region 22, the second plating resist film 28 outside the upper half of the inner peripheral side of the upper surface of the seal ring contact portion 26 is removed, and columnar electrodes are formed on the second plating resist film 28 inside thereof. A dummy opening (not shown) corresponding to the exposure pattern of the forming exposure mask 30 is formed. In this state, the outer side of the seal ring contact portion 26 and the plated connection terminal portion 7a are exposed from the inner peripheral side half or less of the upper surface.

  Here, the first plating resist film 23 is composed of a non-exposed portion and is covered with the second plating resist film 28. However, the second plating resist film 28 is formed by the exposed portion, thereby laminating. When the exposed unexposed dry film resist is exposed, areas other than those under the second light shielding ring 29 are exposed simultaneously. Moreover, as a developer for a negative dry film resist made of an acrylic resin, an alkaline developer (Na2CO3, TMAH: tetramethylammonium hydroxide, etc.) is generally used. The positive-type first plating resist film 23 made of is not attacked by being developed.

  Next, as shown in FIG. 14, a seal ring 27 of a plating jig similar to the above is brought into contact with the outer peripheral side half of the upper surface of the seal ring contact portion 26, and the plating jig is placed on the upper surface of the plating connection terminal portion 7a. In the semiconductor device formation region 22, a columnar shape is formed on the upper surface of the connection pad portion of the wiring 9 in the opening portion 28a of the second plating resist film 28 when the copper power plating member (not shown) is contacted and copper is electroplated. Electrode 9 is formed. Although not shown, a dummy columnar electrode is formed on the upper surface of the connection pad portion of the dummy wiring in the dummy opening of the second plating resist film 28 around the semiconductor device formation region 22.

  In this case, since the seal ring 27 of the plating jig is brought into contact with the outer peripheral side half of the upper surface of the seal ring contact portion 26 instead of the upper surface of the peripheral portion of the second plating resist film 28, Even if a dummy opening having an outer opening due to step exposure is formed in the peripheral portion of the second plating resist film 28, the invasion of the plating solution into the plating connection terminal portion 7a is surely prevented. Can do.

  Next, both plating resist films 23 and 28 are peeled off simultaneously. For example, the monoethanolamine-based stripping solution can strip both of the negative second plating resist film 28 made of acrylic resin and the positive first plating resist film 23 made of novolac resin. . Therefore, both plating resist films 23 and 28 are stripped simultaneously using a monoethanolamine stripping solution.

  Next, when unnecessary portions of the base metal layer 7 are removed by etching using the wiring 8 and the dummy wiring 8a as a mask, the base metal layer 7 remains only under the wiring 8 and the dummy wiring 8a as shown in FIG. The Next, as shown in FIG. 16, a columnar electrode 9, a dummy columnar electrode (not shown, description thereof is omitted below), an upper surface of the protective film 5 including the wiring 8 and the dummy wiring 8a is made of epoxy resin or the like. The sealing film 10 to be formed is formed so that its thickness is slightly thicker than the height of the columnar electrode 9. Therefore, in this state, the upper surface of the columnar electrode 9 is covered with the sealing film 10.

  Next, by appropriately polishing the upper surface side of the sealing film 10 and the columnar electrode 9, as shown in FIG. 17, the upper surface of the columnar electrode 9 is exposed, and the exposed upper surface of the columnar electrode 9 is exposed. The upper surface of the sealing film 10 that is included is planarized. Next, as shown in FIG. 18, solder balls 11 are formed on the upper surface of the columnar electrode 9. Next, as shown in FIG. 19, a plurality of semiconductor devices shown in FIG. 1 are obtained through a dicing process.

Sectional drawing of the semiconductor device manufactured by the manufacturing method as one Embodiment of this invention. The top view of what was prepared initially in the case of manufacture of the semiconductor device shown in FIG. Sectional drawing which follows the III-III line | wire of FIG. Sectional drawing of the process following FIG. The top view of the process following FIG. Sectional drawing which follows the VI-VI line of FIG. Sectional drawing of the process following FIG. The top view of the process following FIG. Sectional drawing which follows the IX-IX line of FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. FIG. 15 is a sectional view of a step following FIG. 14. FIG. 16 is a cross-sectional view of the process following FIG. 15. FIG. 17 is a cross-sectional view of the process following FIG. 16. FIG. 18 is a cross-sectional view of the process following FIG. 17. FIG. 19 is a cross-sectional view of the process following FIG. 18. 1A and 1B are views for explaining a conventional method for manufacturing a semiconductor device, in which FIG. 1A is a plan view of an example of a peripheral portion of a semiconductor wafer, and FIG. (A) is a top view shown in order to demonstrate the process following FIG. 20, (B) is sectional drawing which follows the BB line.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Connection pad 3 Insulating film 5 Protective film 7 Base metal layer 7a Plating connection terminal part 8 Wiring 9 Columnar electrode 10 Sealing film 11 Solder ball 21 Semiconductor wafer 22 Semiconductor device formation area 23 1st plating resist film 24 First light shielding ring 25 Wiring forming exposure mask 26 Seal ring contact portion 27 Sealing ring of plating jig 28 Second plating resist film 29 Second light shielding ring 30 Columnar electrode forming exposure mask

Claims (6)

Forming a base metal layer on the entire surface of the semiconductor wafer;
Forming an unexposed first plating resist film on the base metal layer;
Removing the peripheral portion of the first plating resist film and exposing the peripheral portion of the base metal layer for use as a connection terminal portion for plating;
By performing exposure and development, an opening for forming a wiring is formed in the first plating resist film, and the first plating resist film is formed on the inner metal layer on the base metal layer from the first plating resist film. Forming a ring-shaped seal ring contact portion, and contacting the seal ring contact portion with a seal ring of a plating jig for not plating the peripheral portion of the first plating resist film; and Wiring is formed on the base metal layer in the wiring forming opening of the first plating resist film by performing electroplating in a state where the power supply member of the plating jig is in contact with the connection terminal portion for use. Process,
A method for manufacturing a semiconductor device, comprising: 2. The method according to claim 1, wherein an unexposed second plating resist film is formed on the entire surface of the wiring, the first plating resist film, the seal ring contact portion, and the plating connection terminal portion. ,
By performing exposure and development, an opening for forming a columnar electrode is formed in the second plating resist film, and a peripheral portion of the second plating resist film is removed to remove the plating connection terminal portion and the plating electrode Exposing at least the outer peripheral side of the seal ring contact portion;
A seal ring of the plating jig for not plating the peripheral portion of the second plating resist film is brought into contact with the seal ring contact portion, and a power supply member of the plating jig is connected to the plating connection terminal portion. Forming a columnar electrode on the connection pad portion of the wiring in the columnar electrode formation opening of the second plating resist film by performing electrolytic plating in a contact state;
Removing both the plating resist films using a resist remover;
Etching and removing unnecessary portions of the base metal layer using the wiring as a mask;
A method for manufacturing a semiconductor device, comprising:   In the invention according to claim 2, a step of forming a sealing film covering the periphery of the columnar electrode after removing an unnecessary portion of the base metal layer, and a step of forming a solder ball on the columnar electrode; And a step of cutting the semiconductor wafer by dicing to obtain a plurality of semiconductor devices.   In the invention according to claim 2, the exposure to the first plating resist film is performed using a wiring forming exposure mask in a state where a first light shielding ring is arranged on the upper surface of the peripheral portion of the first plating resist film. A method for manufacturing a semiconductor device, characterized in that the step exposure is performed.   The exposure of the second plating resist film according to the fourth aspect of the invention may be performed by using a columnar electrode forming exposure mask in a state where the second light shielding ring is disposed on the upper surface of the peripheral portion of the second plating resist film. A method of manufacturing a semiconductor device, wherein the step exposure is used.   6. The method of manufacturing a semiconductor device according to claim 5, wherein the inner diameter of the second light shielding ring is greater than or equal to the inner diameter of the first light shielding ring.

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