JPH0637427A - Manufacture of copper polyimide wiring board and structure thereof - Google Patents

Manufacture of copper polyimide wiring board and structure thereof

Info

Publication number
JPH0637427A
JPH0637427A JP19056992A JP19056992A JPH0637427A JP H0637427 A JPH0637427 A JP H0637427A JP 19056992 A JP19056992 A JP 19056992A JP 19056992 A JP19056992 A JP 19056992A JP H0637427 A JPH0637427 A JP H0637427A
Authority
JP
Japan
Prior art keywords
thin film
resist layer
wiring
regions
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP19056992A
Other languages
Japanese (ja)
Inventor
Yutaka Azumaguchi
裕 東口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP19056992A priority Critical patent/JPH0637427A/en
Publication of JPH0637427A publication Critical patent/JPH0637427A/en
Withdrawn legal-status Critical Current

Links

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

PURPOSE:To prevent a short-circuit between the neighboring wiring parts in a product by forming dams of polyimide resin on the surface of a substrate material in reverse phase to a wiring pattern. CONSTITUTION:Dams 3 of polyimide resin having unevenness in reverse phase to a purposed wiring pattern are formed on a substrate 1. Next, a conductive foundation thin film 4 and a resist layer 5 are by turns formed on the drams 3 for being made a wiring board material and for performing patterning to the resist layer 5 so as to perform a developing treatment. Thereby, a resist layer 5 exsisting on the second regions B excepting the first regions A corresponding to the top faces of the dams 3 is removed so as to expose a foundation thin film 4 of the second regions B while forming the wiring parts of copper on the foundation thin film in the second exposed regions by electrolytic plating. Then, the resist layer 5 of the first regions A is peeled off so as to expose the foundation thin film 4 of the first regions A wile finally performing an etching treatment for removing the foundation thin film 4 of the first regions A so as to obtain a desired wiring pattern.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、多層セラミック基板上
に薄膜技術を用いて構成される銅ポリイミド配線板の構
造に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a copper-polyimide wiring board formed by using thin film technology on a multilayer ceramic substrate.

【0002】[0002]

【従来の技術】銅ポリイミド配線板は図2に示すような
プロセスに従って構成される。先ずセラミック基板21
上にポリイミド樹脂を塗布して絶縁性を有するポリイミ
ドの層22を形成し、更にその上にクローム、銅等から
なる導電性を有する下地薄膜23を形成する(図2
a)。
2. Description of the Related Art A copper polyimide wiring board is constructed according to a process as shown in FIG. First, the ceramic substrate 21
A polyimide resin is applied to form an insulating polyimide layer 22, and a conductive underlying thin film 23 made of chrome, copper or the like is formed on the polyimide layer 22 (FIG. 2).
a).

【0003】次に下地薄膜23の上にレジスト層24を
形成し、これに写真技術を応用してパターニングを行
い、現像処理して不要な部分を除去する(図2b)。こ
れに電解メッキを施してレジスト層の除去された部分に
銅の配線部25を形成する(図2c)。次に配線部25
の間に残っているレジスト層24を剥離・除去し、露出
した下地薄膜23の部分をウェットエッチングによって
除去する(図2d)。
Next, a resist layer 24 is formed on the underlying thin film 23, a photographic technique is applied to the resist layer 24 to perform patterning, and development processing is performed to remove unnecessary portions (FIG. 2B). This is subjected to electrolytic plating to form a copper wiring portion 25 on the removed portion of the resist layer (FIG. 2c). Next, the wiring section 25
The resist layer 24 remaining between the layers is removed and removed, and the exposed portion of the underlying thin film 23 is removed by wet etching (FIG. 2d).

【0004】[0004]

【発明が解決しようとする課題】このような従来技術に
よる銅ポリイミド配線板においては、レジスト層24を
除去した後に残された配線部25の側壁がオーバーハン
グ状の傾斜をなしているので、エッチング処理において
配線板を処理液中に浸漬する際、隣合う配線部25同士
の間の溝の空気が脱出し難く、図2dに示すようにこれ
が気泡26として残る場合がある。特に、電源用の配線
として用いられる細かいメッシュ状パターンの場合には
この傾向が強い。
In such a conventional copper-polyimide wiring board, since the side wall of the wiring portion 25 left after removing the resist layer 24 has an overhang-like slope, it is etched. When the wiring board is dipped in the treatment liquid during the treatment, the air in the groove between the adjacent wiring portions 25 is difficult to escape, and this may remain as bubbles 26 as shown in FIG. 2d. This tendency is particularly strong in the case of a fine mesh pattern used as a wiring for a power supply.

【0005】このような気泡の存在は下地薄膜23への
処理液の到達を妨げ、この部分の下地薄膜がエッチング
されずに残存し、製品となった場合に隣接する配線パタ
ーン間で短絡を生じるので好ましくない。本発明は、こ
のような従来技術における問題点を解決し、エッチング
処理時に隣接する配線部間の空間に気泡が付着すること
のない銅ポリイミド配線板の製造法並びにその方法で得
られた独特の構造の配線板を提供することを目的とす
る。
The presence of such bubbles prevents the treatment liquid from reaching the underlayer thin film 23, and the underlayer thin film in this portion remains without being etched, resulting in a short circuit between adjacent wiring patterns when the product is a product. It is not preferable. The present invention solves the above problems in the prior art, a method for producing a copper polyimide wiring board in which bubbles do not adhere to the space between adjacent wiring portions during etching, and a unique method obtained by the method. An object is to provide a wiring board having a structure.

【0006】[0006]

【課題を解決するための手段】この目的は、基板上に目
的とする配線パターンに対して逆移相の凹凸を有するポ
リイミド樹脂のダムを形成し、該ダムの上に導電性の下
地薄膜とレジスト層を順次に形成して配線板素材とな
し、レジスト層に対してパターニングを行って現像処理
することによって、前記ダムの頂面に対応する第1領域
以外の第2領域に存在しているレジストを除去して当該
第2領域の下地薄膜を露出させ、露出している第2領域
の下地薄膜に電解メッキによって銅の配線部を形成し、
第1領域のレジストを剥離して第1領域の下地薄膜を露
出させ、エッチング処理を行って第1領域の下地薄膜を
除去して所望の配線パターンを得ることを特徴とする銅
ポリイミド配線板の製造方法、並びに、配線パターンと
逆位相でポリイミド樹脂のダムが表面に配列され、該ダ
ムの頂面と実質的に一致する平面上に銅の配線パターン
が配列されていることを特徴とする銅ポリイミド配線板
によって達成される。
The object of the present invention is to form a dam of polyimide resin having concavities and convexities of reverse phase shift with respect to a target wiring pattern on a substrate, and to form a conductive base thin film on the dam. A resist layer is sequentially formed to form a wiring board material, and the resist layer is patterned and developed to be present in a second region other than the first region corresponding to the top surface of the dam. The resist is removed to expose the underlying thin film in the second region, and a copper wiring portion is formed on the exposed underlying thin film in the second region by electrolytic plating.
A copper polyimide wiring board, characterized in that the resist in the first region is peeled off to expose the underlying thin film in the first region, and an etching process is performed to remove the underlying thin film in the first region to obtain a desired wiring pattern. Manufacturing method and copper characterized in that a polyimide resin dam is arranged on the surface in a phase opposite to that of the wiring pattern, and the copper wiring pattern is arranged on a plane substantially corresponding to the top surface of the dam. Achieved by a polyimide wiring board.

【0007】[0007]

【作用】配線板素材の表面には予めポリイミド樹脂のダ
ムが形成されているので、エッチング処理によって除去
されるべき下地薄膜はダムの頂面にのみ残存している。
従って、下地薄膜の表面への気泡の付着等は発生せず、
処理液は容易に下地薄膜に接触し、これを完全に除去す
る。従って、下地薄膜の残存に起因する隣接する配線部
間での短絡発生が防止される。
Since the dam of the polyimide resin is previously formed on the surface of the wiring board material, the underlying thin film to be removed by the etching process remains only on the top surface of the dam.
Therefore, adhesion of bubbles to the surface of the underlying thin film does not occur,
The treatment liquid easily contacts the underlying thin film and completely removes it. Therefore, it is possible to prevent a short circuit from occurring between the adjacent wiring portions due to the remaining base thin film.

【0008】以下、図面に示す好適実施例に基づいて、
本発明を更に詳細に説明する。
Hereinafter, based on the preferred embodiment shown in the drawings,
The present invention will be described in more detail.

【0009】[0009]

【実施例】図1は本発明の方法による銅ポリイミド配線
板の製造工程を示す。先ず通常のようにセラミック基板
1の上にポリイミド樹脂を塗布してポリイミド層2を形
成する。(図1a) 次にポリイミド樹脂の感光性を利用してメッシュ状の配
線パターンを印刷し、現像処理して配線パターンと逆位
相の位置に整然と配列された複数のポリイミド樹脂のダ
ム3を形成する。このダムが形成されている領域を第1
領域Aと称する。(図1b) メッシュのサイズが25μm 角の場合、このダムの高さ
は13μm 程度、下部の幅は25μm 程度が好ましい。
EXAMPLE FIG. 1 shows a manufacturing process of a copper polyimide wiring board by the method of the present invention. First, a polyimide resin is applied on the ceramic substrate 1 to form a polyimide layer 2 as usual. (FIG. 1a) Next, a photosensitive wiring of a polyimide resin is used to print a mesh-shaped wiring pattern, and a development process is performed to form a plurality of polyimide resin dams 3 that are regularly arranged in positions opposite to the wiring pattern. . First the area where this dam is formed
It is called area A. (FIG. 1b) When the size of the mesh is 25 μm square, the height of this dam is preferably about 13 μm, and the width of the lower part is preferably about 25 μm.

【0010】こうして形成されたポリイミド層2とダム
3の上に導電性の下地薄膜4を形成し、更にその上にレ
ジスト層5を形成する。(図1c) 次に再び配線パターンを印刷し、前記ダム3の頂部のレ
ジスト層5、即ち第1領域Aのレジスト層を感光させ、
現像して第1領域のみを残して残りの第2領域Bのレジ
スト層を除去し、第2領域の下地薄膜4を表面に露出さ
せる。(図1d) そして、電解メッキ処理を行って露出されている第2領
域Bの下地薄膜上に銅の配線部6を形成する。(図1
e) 最後に残っている第1領域Aのレジスト層2を剥離して
下地薄膜4を露出させ、この状態でエッチング処理によ
ってこの第1領域Aの下地薄膜4を除去する。(図1
f) エッチング処理の際に、第1領域Aの下地薄膜は、これ
に隣接する第2領域Bの配線部6とほぼ同じ平面上に並
んでいるので、処理液との接触が良好となり、従来技術
ではしばしば発生していた気泡の取り込み等の問題が起
こらない。従って、下地薄膜4は完全に除去され、配線
部同士の短絡による欠陥が減少する。
A conductive base thin film 4 is formed on the polyimide layer 2 and the dam 3 thus formed, and a resist layer 5 is further formed thereon. (FIG. 1c) Next, a wiring pattern is printed again, and the resist layer 5 on the top of the dam 3, that is, the resist layer in the first region A is exposed to light,
After development, only the first region is left and the remaining resist layer in the second region B is removed to expose the underlying thin film 4 in the second region on the surface. (FIG. 1d) Then, the copper wiring portion 6 is formed on the exposed underlying thin film of the second region B by electrolytic plating. (Fig. 1
e) Finally, the remaining resist layer 2 in the first area A is peeled off to expose the underlying thin film 4, and in this state, the underlying thin film 4 in the first area A is removed by etching. (Fig. 1
f) During the etching process, the underlying thin film in the first region A is lined up on substantially the same plane as the wiring portion 6 in the second region B adjacent to the first region A, so that the contact with the processing liquid becomes good, and Problems such as air bubble entrapment that often occur in technology do not occur. Therefore, the underlying thin film 4 is completely removed, and the defects due to the short circuit between the wiring portions are reduced.

【0011】このようにして得られた銅ポリイミド配線
板は、表面にポリイミド樹脂のダムが整然と点在し、こ
れらのダムの間をメッシュ状に導線パターンが配列され
ている。又、断面を見ると配線部6とポリイミド樹脂の
ダム3の頂面とがほぼ一平面上に並んだ独特の構造を形
成している。
In the copper polyimide wiring board thus obtained, dams of polyimide resin are regularly scattered on the surface, and a conductor pattern is arranged in a mesh between these dams. Further, when viewed in cross section, the wiring portion 6 and the top surface of the polyimide resin dam 3 form a unique structure in which they are arranged substantially on one plane.

【0012】[0012]

【発明の効果】本発明によれば、基板素材の表面に配線
パターンと逆位相の配置でポリイミド樹脂のダムを形成
したので、配線部が形成された後、除去すべき下地薄膜
はダムの頂面にのみ残存している。従って、下地薄膜は
エッチング処理液に容易に接触可能となり、完全に腐食
して除去され、製品における隣接する配線部間の短絡事
故が防がれる。
According to the present invention, the polyimide resin dam is formed on the surface of the substrate material in a phase opposite to that of the wiring pattern. Therefore, after the wiring portion is formed, the underlying thin film to be removed is the top of the dam. It remains only on the surface. Therefore, the underlying thin film can be easily brought into contact with the etching solution and completely corroded and removed, thereby preventing a short circuit between adjacent wiring parts in the product.

【0013】また、配線部を形成する銅がポリイミド層
に拡散浸透することを防止するために、通常、配線部の
表面にバリアメタルの皮膜が形成される。従来はオーバ
ーハング状をなす配線部の側壁領域にこのバリアメタル
皮膜を形成することが困難であったが、本発明において
は実質的に配線部の側壁が存在しないのでこうした問題
は生じない。
A barrier metal film is usually formed on the surface of the wiring portion in order to prevent copper forming the wiring portion from diffusing and penetrating into the polyimide layer. In the past, it was difficult to form this barrier metal film on the side wall region of the wiring part having an overhang shape, but since the side wall of the wiring part is substantially absent in the present invention, such a problem does not occur.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明による銅ポリイミド配線板の製造プロセ
スを示す断面図である。
FIG. 1 is a sectional view showing a manufacturing process of a copper polyimide wiring board according to the present invention.

【図2】従来の銅ポリイミド配線板の製造プロセスを示
す断面図である。
FIG. 2 is a cross-sectional view showing a manufacturing process of a conventional copper polyimide wiring board.

【符号の説明】[Explanation of symbols]

1…セラミック基板 2…ポリイミド層 3…ダム 4…下地薄膜 5…レジスト層 6…配線部 A…第1領域 B…第2領域 DESCRIPTION OF SYMBOLS 1 ... Ceramic substrate 2 ... Polyimide layer 3 ... Dam 4 ... Base thin film 5 ... Resist layer 6 ... Wiring part A ... 1st area | region B ... 2nd area | region

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 基板(1)上に目的とする配線パターン
と逆移相の凹凸を有するポリイミド樹脂のダム(3)を
形成し、該ダム(3)の上に導電性の下地薄膜(4)と
レジスト層(5)を順次に形成して配線板素材となし、
レジスト層(5)に対してパターニングを行って現像処
理することによって、前記ダム(3)の頂面に対応する
第1領域(A)以外の第2領域(B)に存在しているレ
ジスト層(5)を除去して当該第2領域(B)の下地薄
膜(4)を露出させ、露出している第2領域(B)の下
地薄膜(4)に電解メッキによって銅の配線部(6)を
形成し、第1領域(A)のレジスト層(5)を剥離して
第1領域(A)の下地薄膜(4)を露出させ、エッチン
グ処理を行って第1領域(A)の下地薄膜(4)を除去
して所望の配線パターンを得ることを特徴とする銅ポリ
イミド配線板の製造方法。
1. A dam (3) made of polyimide resin having an unevenness of a phase shift opposite to that of a target wiring pattern is formed on a substrate (1), and a conductive base thin film (4) is formed on the dam (3). ) And a resist layer (5) are sequentially formed to form a wiring board material,
By patterning and developing the resist layer (5), the resist layer existing in the second region (B) other than the first region (A) corresponding to the top surface of the dam (3). (5) is removed to expose the underlying thin film (4) in the second area (B), and the exposed underlying thin film (4) in the second area (B) is electroplated to form a copper wiring portion (6). ) Is formed, the resist layer (5) in the first region (A) is peeled off to expose the underlying thin film (4) in the first region (A), and an etching process is performed to form the underlying film in the first region (A). A method for producing a copper-polyimide wiring board, which comprises removing the thin film (4) to obtain a desired wiring pattern.
【請求項2】 配線パターン(6)と逆位相で複数のポ
リイミド樹脂のダム(3)が表面に配列され、隣接する
ダム(3)同士の間の凹部に、該ダム(3)の頂面と実
質的に一平面をなして銅の配線パターン(6)が配列さ
れていることを特徴とする銅ポリイミド配線板。
2. A plurality of dams (3) made of polyimide resin are arranged on the surface in a phase opposite to that of the wiring pattern (6), and the top surface of the dam (3) is provided in a recess between adjacent dams (3). And a copper wiring pattern (6) arranged substantially in one plane.
JP19056992A 1992-07-17 1992-07-17 Manufacture of copper polyimide wiring board and structure thereof Withdrawn JPH0637427A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19056992A JPH0637427A (en) 1992-07-17 1992-07-17 Manufacture of copper polyimide wiring board and structure thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19056992A JPH0637427A (en) 1992-07-17 1992-07-17 Manufacture of copper polyimide wiring board and structure thereof

Publications (1)

Publication Number Publication Date
JPH0637427A true JPH0637427A (en) 1994-02-10

Family

ID=16260249

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19056992A Withdrawn JPH0637427A (en) 1992-07-17 1992-07-17 Manufacture of copper polyimide wiring board and structure thereof

Country Status (1)

Country Link
JP (1) JPH0637427A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100492498B1 (en) * 2001-05-21 2005-05-30 마츠시다 덴코 가부시키가이샤 Method of manufacturing printed wiring board
US10734156B2 (en) 2014-10-09 2020-08-04 Murata Manufacturing Co., Ltd. Inductor component

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100492498B1 (en) * 2001-05-21 2005-05-30 마츠시다 덴코 가부시키가이샤 Method of manufacturing printed wiring board
US10734156B2 (en) 2014-10-09 2020-08-04 Murata Manufacturing Co., Ltd. Inductor component

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Legal Events

Date Code Title Description
A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 19991005