JP2011035143A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that satisfactorily radiates heat in rewiring formed on a semiconductor substrate and reduces thermal stress acting on a pad, and to provide a method of manufacturing the semiconductor device. <P>SOLUTION: The semiconductor device 10 includes a semiconductor substrate 12, an insulating layer for covering at least one wiring layer provided on an upper surface of the semiconductor substrate 12, the rewiring 48 composed of the pad 44 that is formed in a pad shape and allows the connection of an external terminal thereto, and wiring 19 for connecting a pad electrode 42 to the pad 44, and a stress relaxation section 11 disposed between the pad 44 and the insulating layer and made of a resin material. Then, the wiring 19 in the rewiring 48 is disposed closer to the side of the semiconductor substrate 12 than the pad 44. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a WLP (Wafer Level Package) in which wirings and electrodes are formed on a main surface of a semiconductor substrate and a manufacturing method thereof.

  2. Description of the Related Art Conventionally, a circuit device set in an electronic device is employed in a mobile phone, a portable computer, and the like, and thus, a reduction in size, thickness, and weight are required. In order to satisfy these conditions, a semiconductor device called a CSP (Chip Scale Package) having a size equivalent to a built-in semiconductor element has been developed.

  Among these CSPs, there is WLP as a particularly downsized one. A conventionally known structure of WLP is described in Patent Document 1 below. The structure of the semiconductor device 100 disclosed in this document will be described with reference to FIG. In the semiconductor device 100, a multilayer wiring layer 104 of, for example, about three layers is laminated via an insulating film on the upper surface of a semiconductor substrate 102 on which various elements are formed by a diffusion process. Further, the uppermost wiring layer is covered with an insulating film 106 made of, for example, a silicon nitride film. Further, the pad electrode 102 made of the uppermost wiring layer is exposed from the insulating film 106.

  A first resin layer 108 and a second resin layer 112 are sequentially stacked on the upper surface of the insulating film 106. The first resin layer 108 and the second resin layer 112 are made of an epoxy resin having a thickness of about 10 μm. A rewiring 110 is formed on the upper surface of the first resin layer 108, and a part of the rewiring 110 constitutes a pad 114. The pad 114 is exposed to the outside through an opening 116 provided by partially removing the second resin layer 112, and an external terminal 118 made of solder is attached to the exposed portion of the pad 114. Further, the end portion of the rewiring 110 penetrates the first resin layer 108 and is connected to the pad electrode 120.

  Moreover, the following manufacturing method is known as a manufacturing method of the conventional WLP (for example, refer patent document 2 and patent document 3). First, a first protective film made of a silicon nitride film is formed on a semiconductor wafer on which a diffusion layer or the like of a semiconductor element is formed. After the first wiring layer is formed on the first protective film or the like, a second protective film made of a polyimide film is formed on the first protective film. Then, after forming a second wiring layer on the second protective film or the like, a third protective film made of a polyimide film is formed. At this time, a peripheral pattern composed of the first wiring layer and the second wiring layer is formed around the semiconductor element formation region. Thereafter, the first to third protective films between the peripheral patterns are removed and scribe lines are formed by opening, and then the semiconductor wafer exposed from the opening region is cut with a dicing saw to obtain a chip state.

JP 2000-294607 A JP-A-8-172062 Japanese Patent Laid-Open No. 5-41449

  However, the semiconductor device having the above configuration has a problem that heat generated from the rewiring 110 when the semiconductor device 100 is operated is not easily released to the outside.

  Specifically, first, the rewiring 110 is formed on the upper surface of the first resin layer 108 formed on the semiconductor substrate 102. The reason why the rewiring 110 is formed on the upper surface of the first resin layer 108 is that the thermal stress acting on the external terminal 118 and the pad 114 is located below the pad 114 when the semiconductor device 100 is mounted. This is because the first resin layer 108 relaxes. The first resin layer 108 made of a resin is superior in flexibility as compared with other layers made of a semiconductor material or an oxide. Therefore, even if the above-described thermal stress acts on the external terminal 118 and the pad 114, the first resin layer 108 existing under the pad 114 is deformed, so that this thermal stress is reduced. As a result, the thermal stress acting on the external terminal 118 and the pad 114 is also reduced, and these are prevented from being destroyed by the thermal stress.

However, the epoxy resin that is the material of the first resin layer 108 is inferior in thermal conductivity as compared with other materials. For example, the thermal conductivity of silicon that is a material of the semiconductor substrate 102 is 168 (W · m ⁻¹ · K ⁻¹ ), whereas the thermal conductivity of the epoxy resin that is the main material of the first resin layer 108 is It is 0.21 (W · m ⁻¹ · K ⁻¹ ), which is much smaller. Therefore, even if the rewiring 100 generates heat when the semiconductor device 100 is operated, the heat transfer to the semiconductor substrate 102 side is hindered by the first resin layer 108, so that heat is not dissipated well and rewiring is not performed. The temperature of 110 will rise. As a result, the first resin layer 108 and the second resin layer 112 adjacent to the rewiring 110 may be deteriorated to cause delamination, or the characteristics of the entire semiconductor device 100 may be deteriorated.

  In order to avoid this problem, a structure in which the entire rewiring 110 is provided on the upper surface of the insulating film 106 that is a passivation film is also conceivable. However, with this structure, the stress relaxation function of the first resin layer 108 is lost, and thus the external terminals 118 and the pads 114 may be destroyed by the above-described thermal stress.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to improve the heat dissipation of the rewiring formed on the semiconductor substrate, and to reduce the thermal stress acting on the pad and the manufacturing thereof. It is to provide a method.

  The semiconductor device of the present invention includes a semiconductor substrate, an insulating layer covering at least one wiring layer provided on one main surface of the semiconductor substrate, a pad portion to which an external terminal is connected, and the wiring layer. A rewiring composed of a pad portion and a wiring portion connecting the pad portion, and a stress relieving portion made of a resin material disposed between the pad portion and the insulating layer. The wiring part is arranged closer to the semiconductor substrate side than the pad part.

  The method for manufacturing a semiconductor device of the present invention includes a semiconductor substrate, a wiring layer connected to an element formation region of the semiconductor substrate, an insulating layer covering the wiring layer, and one wiring layer exposed from the insulating layer. A step of providing a semiconductor wafer having a pad electrode made of a portion, a step of providing a stress relaxation portion mainly made of a resin on the upper surface of the insulating layer in a region where a pad portion to which an external terminal is connected is provided, A rewiring is formed that includes the pad portion disposed on the upper surface of the stress relaxation portion, and a wiring portion that connects the pad and the pad electrode, and the wiring portion is closer to the semiconductor substrate than the pad portion. And a step of arranging in a step.

  According to the present invention, the stress relaxation portion is provided between the rewiring pad portion and the semiconductor substrate, and the rewiring wiring portion is disposed closer to the semiconductor substrate side than the pad portion. Accordingly, first, since the stress relaxation layer made of a resin material is disposed below the pad portion, the thermal stress acting on the pad portion and the external terminal welded to the pad portion is relaxed. Furthermore, since the wiring portion of the rewiring is arranged on the semiconductor substrate side, even if the current passes when the semiconductor device is operated and the wiring portion generates heat, the generated heat passes through the insulating layer and the semiconductor substrate. And is released well to the outside. This prevents overheating of the wiring part.

1A and 1B are diagrams illustrating a configuration of a semiconductor device according to the present invention, in which FIG. 1A is a cross-sectional view, and FIG. 1B and FIG. (A) is sectional drawing which shows the specific structure of the wiring layer with which the semiconductor device of this invention is equipped, (B) is sectional drawing which shows the state with which the semiconductor device of this invention was mounted in the mounting board | substrate. It is a figure which shows the manufacturing method of the semiconductor device of this invention, (A) is a top view, (B) is the enlarged top view. It is a figure which shows the manufacturing method of the semiconductor device of this invention, and (A)-(C) is sectional drawing. It is a figure which shows the manufacturing method of the semiconductor device of this invention, and (A)-(D) is sectional drawing. It is a figure which shows the manufacturing method of the semiconductor device of this invention, and (A)-(D) is sectional drawing. It is sectional drawing which shows the semiconductor of background art.

  With reference to FIG. 1, the structure of the semiconductor device 10 of this embodiment is demonstrated. 1A is a cross-sectional view illustrating the entire semiconductor device 10, FIG. 1B is a cross-sectional view illustrating a part of the semiconductor device 10 in an enlarged manner, and FIG. 1C illustrates another embodiment. It is sectional drawing which shows this structure.

  Referring to FIG. 1A, a semiconductor device 10 is a WLP in which a wiring and an external terminal 46 are arranged on the upper surface side of a semiconductor substrate 12, and a schematic configuration is as follows. First, an element is formed near the upper surface of the semiconductor substrate 12 made of a semiconductor material such as silicon by a diffusion process. An insulating layer (not shown) covering the upper surface of the semiconductor substrate 12 is covered with the first resin layer 30, and a rewiring 48 connected to the pad electrode 42 is formed on the upper surface of the first resin layer 30. ing. The upper surfaces of the rewiring 48 and the first resin layer 30 are covered with the second resin layer 32. Further, the pad portion 44 made of a part of the rewiring 48 is exposed from the second resin layer 32, and an external terminal 46 made of a conductive adhesive such as solder is welded to the upper surface of the pad portion 44.

  With reference to FIG. 1B, the structure of the semiconductor device 10 will be described in detail. Transistors, resistors, and the like are formed in the semiconductor substrate 12 by diffusion regions, and have a rectangular shape in plan view. As the structure of the semiconductor substrate 12, a structure composed of a single crystal substrate or a structure in which an epitaxial layer is formed on the single crystal substrate can be considered. The material of the semiconductor substrate 12 may be silicon or a compound semiconductor substrate.

  One or more wiring layers 15 are provided on the upper surface of the semiconductor substrate 12. The wiring layer 15 is formed by laminating a wiring layer mainly composed of aluminum or aluminum alloy via an insulating layer made of silicon oxide. A specific configuration of the wiring layer 15 will be described later with reference to FIG.

  The upper surface of the wiring layer 15 is covered with an insulating film 17 made of, for example, a silicon nitride film. Further, the pad electrode 42 in which the uppermost wiring layer is formed in a pad shape is exposed from an opening provided by partially removing the insulating film 17.

  The first resin layer 30 is formed so as to cover the insulating film 17. The first resin layer 30 is formed mainly of a resin material such as a polybenzoxazole (PBO) film or a polyimide resin film. Here, the material of the first resin layer 30 may be a thermosetting resin or a thermoplastic resin. Furthermore, the 1st resin layer 30 may be comprised from the resin material with which the filler which consists of granular alumina etc. was filled. By doing so, the thermal conductivity of the first resin layer 30 is improved, and the heat generated from the rewiring 48 is favorably conducted to the semiconductor substrate 12 via the first resin layer 30 and released to the outside. Can be made.

  The stress relaxation portion 11 is configured by projecting a part of the first resin layer 30 upward. The stress relieving portion 11 is a portion where the pad portion 44 formed of a part of the rewiring 48 is disposed, and has a trapezoidal cross-sectional shape as illustrated. The height at which the stress relaxation portion 11 protrudes from the first resin layer 30 in the other region is, for example, 2 μm or more (1 μm or more and 3 μm or less). Furthermore, the upper surface of the first resin layer 30 in a region other than the stress relaxation portion 11 is a flat surface, and the thickness of the first resin layer 30 in this region is thinner than that in the background art. As an example, the thickness of the first resin layer 30 in a region formed flat is about 5 μm or less (3 μm or more and 8 μm or less). Moreover, the upper surface of the pad electrode 42 is exposed from the first resin layer 30 by partially removing and opening the first resin layer 30.

  The rewiring 48 is formed on the upper surface of the first resin layer 30. The rewiring 48 is configured by laminating a plating metal layer and a plating layer. Here, the metal layer for plating is formed by laminating a Cu layer or a nickel (Ni) layer on a refractory metal film composed of a chromium (Cr) layer, a Ti layer or a TiW layer, and forms a plating layer. Used as a seed. As the plating layer, a Cu plating layer formed by electrolytic plating is employed.

  Further, the rewiring 48 includes a pad portion 44 to which the external terminal 46 is attached, and a wiring portion 19 extending integrally so as to connect the pad electrode 42 and the pad portion 44 on the semiconductor substrate 12 side. Composed. The pad portion 44 is formed in a circular or quadrangular shape in plan view, and the width of the wiring portion 19 is formed to be narrower than the pad portion 44 (for example, half or less).

  The pad 44 has an upper surface exposed from the opening 13 provided in the second resin layer 32, and an external terminal 46 made of solder is welded thereto. Further, the pad portion 44 is disposed on the flat upper surface of the stress relaxation portion 11 as described above. Therefore, below the pad portion 44 (between the pad portion 44 and the semiconductor substrate 12), the thick first resin layer 30 including the stress relieving portion 11 as a protruding portion exists. For example, the thickness of the first resin layer 30 existing below the pad portion 44 is about 10 μm. As described above, by providing the stress relaxation portion 11 below the pad portion 44 and locally increasing the thickness of the first resin layer 30, the first resin layer 30 is easily deformed, and the effect of relaxing the thermal stress is obtained. growing. This effect will be described later with reference to FIG.

  The wiring part 19 is formed on the flat upper surface of the first resin layer 30 in a region other than the stress relaxation part 11. In other words, the wiring portion 19 is formed on the upper surface of the first resin layer 30 formed to have a thickness of, for example, 5 μm or less. Therefore, even if the wiring portion 19 generates heat by supplying current under the usage conditions of the semiconductor device 10, the generated heat is good to the outside via the thin first resin layer 30 and the semiconductor substrate 12. To be released. Specifically, most of the heat generated from the wiring part 19 is released to the outside through the first resin layer 30, the insulating film 17, the wiring layer 15, and the semiconductor substrate 12. In addition, since the wiring layer 15 and the insulating film 17 laminated on the upper surface of the semiconductor substrate 12 are made of silicon oxide or metal (inorganic material) that has better heat dissipation than the resin material, heat conduction is relatively good. is there. In this embodiment, the semiconductor substrate 12 having a thermal conductivity superior to that of the first resin layer 30 is used as a heat sink to suppress overheating of the wiring portion 19.

  That is, in this embodiment, the first resin layer 30 is thickened below the pad portion 44 to reduce the thermal stress acting on the pad portion 44, and further, the first resin layer 30 on which the wiring portion 19 is disposed is formed on the first resin layer 30. Thinning ensures heat dissipation.

  With reference to FIG. 1C, a structure of another mode of a semiconductor device will be described. In the semiconductor device shown in this figure, the stress relaxation portion 11 made of the first resin layer 30 is provided only below the pad portion 44, and the first resin layer 30 is not provided in other regions. That is, the lower surface of the pad portion 44 of the rewiring 48 is in contact with the stress relaxation portion 11, and the lower surface of the wiring portion 19 of the rewiring 48 is in contact with the upper surface of the insulating film 17. Other structures are similar to those shown in FIG.

  By disposing the lower surface of the wiring part 19 in contact with the upper surface of the insulating film 17, the heat generated from the wiring part 19 can be released to the outside more efficiently. Specifically, most of the heat generated from the wiring part 19 is released to the outside through the insulating film 17, the wiring layer 15 and the semiconductor substrate 12. Comparing the structure shown in FIG. 1B, since the first resin layer 30 having a large thermal resistance is not included in the heat dissipation path, the structure shown in FIG. 1C is excellent in heat dissipation. .

  Furthermore, since the resistance of the wiring portion 19 formed to be narrower than half the width of the pad portion 44 is increased, it becomes a condition that heat is easily generated when current flows. Even under such a condition, in the present embodiment, the wiring portion 19 is disposed close to the semiconductor substrate 12 side as described above, so that the wiring portion 19 can be radiated well through the semiconductor substrate 12. Suppresses overheating.

  Next, a specific configuration of the wiring layer 15 formed on the upper surface of the semiconductor substrate 12 will be described with reference to FIG. Here, three wiring layers are laminated through an insulating layer. Specifically, the oxide film 16, the first wiring layer 18, the first insulating layer 20, the second wiring layer 22, the second insulating layer 24, the third wiring layer 26, and the like are formed on the upper surface of the semiconductor substrate 12 from the lower layer. A third insulating layer 28 is laminated.

The oxide film 16 is formed on the semiconductor substrate 12 by, for example, a thermal oxidation method or a CVD (Chemical Vapor Deposition) method. Then, a contact hole is formed in the oxide film 16 by photolithography, for example, by dry etching using a CHF ₃ or CF ₄ gas. Tungsten (W) is buried in this contact hole by the CVD method.

  A first wiring layer 18 connected to the diffusion region via the contact hole is formed on the upper surface of the oxide film 16. For example, the first wiring layer 18 is formed by laminating a barrier metal film, a metal film, and an antireflection film in this order. Here, the barrier metal film is made of a refractory metal such as titanium (Ti) or titanium nitride (TiN). The metal film is an aluminum film selected from an aluminum (Al) film, an aluminum-silicon (Al-Si) film, an aluminum-silicon-copper (Al-Si-Cu) film, an aluminum-copper (Al-Cu) film, or the like. It consists of an alloy film mainly composed of (Al). The antireflection film is made of a refractory metal such as TiN or titanium tungsten (TiW).

  The first insulating layer 20 is formed so as to cover the oxide film 16 and the first wiring layer 18 described above. The first insulating layer 20 includes a TEOS (Tetra-Ethyl-Orso-Silicate) film, an SOG (Spin On Glass) film, and a TEOS film that are sequentially stacked. In this way, by forming the first insulating layer 20 with a plurality of layers of films, the flatness of the upper surface of the first insulating layer 20 is improved. In addition, a contact hole for connecting the first wiring layer 18 and the second wiring layer 22 is formed by partially penetrating a desired portion of the first insulating layer 20.

  A second wiring layer 22 is formed on the upper surface of the first insulating layer 20. Similar to the first wiring layer 18, the second wiring layer 22 is formed of a laminate of a barrier metal film, a metal film, and an antireflection film. The second wiring layer 22 penetrates the first insulating layer 20 at a predetermined location and is electrically connected to the lower first wiring layer 18.

  The second insulating layer 24 is formed so that the upper surfaces of the second wiring layer 22 and the first insulating layer 20 are covered. The configuration of the second insulating layer 24 may be the same as that of the first insulating layer 20 described above. For example, the second insulating layer 24 is formed by stacking a TEOS film, an SOG film, and a TEOS film in this order.

  A third wiring layer 26 is formed on the upper surface of the second insulating layer 24. The third wiring layer 26 is a laminate of a barrier metal film, a metal film, and an antireflection film, like the first wiring layer 18 described above. A pad electrode 42 shown in FIG. 1A is formed from a part of the third wiring layer 26. Further, the second wiring layer 22 and the third wiring layer 26 are electrically connected through the second insulating layer 24 at a predetermined location.

  A third insulating layer 28 is formed so as to cover the second insulating layer 24 and the third wiring layer 26. The third insulating layer 28 includes a TEOS film that covers the second insulating layer 24 and the third wiring layer 26 and a silicon nitride (SiN) film that covers the upper surface of the TEOS film. The SiN film is excellent in moisture resistance, prevents moisture from entering the lower interlayer insulating layer, and prevents corrosion of the wiring layer. Then, a jacket coat film is formed by the TEOS film and the SiN film.

  Further, the upper surface of the third wiring layer 26 to be the pad electrode 42 is exposed from the opening 54 provided by partially removing the third insulating layer 28 and is connected to the rewiring 48.

  Here, when the first resin layer 30 is disposed only below the pad portion as shown in FIG. 1C, the rewiring 48 is formed directly on the upper surface of the third insulating layer 28.

  With reference to FIG. 2 (B), the matter by which the thermal stress is relieved by the stress relieving part 11 will be described. As shown in this figure, the semiconductor device 10 is flip-chip mounted on a mounting substrate 36 to constitute, for example, a semiconductor module. Further, an underfill made of a resin material such as an epoxy resin may be filled between the semiconductor device 10 and the mounting substrate 36.

  The mounting substrate 36 is a substrate mainly made of a resin material such as glass epoxy resin, a metal substrate, or the like. Conductive paths 38 formed by patterning a copper foil into a predetermined shape are formed on the upper surface of the mounting substrate 36. Then, after placing the semiconductor device 10 on the mounting substrate 36 so that the external terminal 46 contacts the upper surface of the conductive path 38, the external terminal 46 made of solder is once melted and cured, whereby the semiconductor device 10 is Implemented face down.

When the semiconductor device 10 that is WLP is mounted face down on the mounting substrate 36 in this way, thermal stress is generated with a change in temperature under use conditions. Specifically, the linear expansion coefficient of the semiconductor substrate 12 (silicon) which is the main material of the semiconductor device 10 is 3.0 × 10 ⁻⁶ / K, and the linear expansion coefficient of the resin constituting the mounting substrate 36 is, for example, 30. × 10 ⁻⁶ / K. Accordingly, since the linear expansion coefficients are greatly different from each other, the expansion amounts of the two are greatly different according to the temperature change. Specifically, as the temperature rises, the amount of expansion of the semiconductor device 10 is slight, whereas the mounting substrate 36 expands relatively large. In such a case, a large thermal stress acts on the external terminal 46 and the pad portion 44 that connect the two, and there is a risk of peeling of these parts or occurrence of cracks in the external terminal 46.

  In this embodiment, the above-described thermal stress is reduced by providing the stress relaxation portion 11 in the semiconductor device 10. Specifically, when a thermal stress is applied to the external terminal 46 and the pad portion 44 as the temperature rises, the stress relaxation portion 11 made of a resin material disposed immediately above the pad portion 44 is laterally moved on the paper surface. Deform in the direction. In this way, the stress relaxing portion 11 made of resin is deformed, so that the stress acting on the external terminal 46 and the pad portion 44 is reduced, and the peeling and cracking of both are suppressed.

  With reference to FIG. 3 to FIG. 6, a method for manufacturing the above-described semiconductor device will be described.

  Referring to FIG. 3, first, a semiconductor wafer 50 provided with a number of element formation regions is prepared through a pre-process. 3A is a plan view generally showing the semiconductor wafer 50, and FIG. 3B is an enlarged plan view showing the element forming region 14. As shown in FIG.

  With reference to FIG. 3A, a plurality of element formation regions 14 are arranged in a matrix on a semiconductor wafer 50. Each element formation region 14 is surrounded by a scribe line 52 defined in a lattice shape on the semiconductor wafer 50.

  Referring to FIG. 3B, a scribe region 34 that is a margin region for scribing is provided between each element formation region 14 arranged in a matrix. In this figure, the scribe area 34 is indicated by dot hatching.

  A scribe line 52 indicated by an alternate long and short dash line indicates a scribe center serving as a reference when the semiconductor wafer 50 is divided, and a region surrounded by the scribe line 52 is one semiconductor device. The enclosed region includes an element formation region 14 formed in a rectangular shape near the center and a scribe region 34 surrounding the element formation region 14.

  Next, a process of providing each wiring layer and insulating layer on the upper surface of the semiconductor substrate 12 will be described with reference to each cross-sectional view of FIG.

  Referring to FIG. 4A, a semiconductor substrate 12 which is a semiconductor wafer is prepared, and an oxide film 16 is formed on the semiconductor substrate 12. The oxide film 16 is formed by, for example, a thermal oxide film method, and is formed by heating to 700 to 1200 (° C.) in an oxidizing atmosphere. As the oxide film 16, for example, a silicon oxide film formed by a CVD method may be deposited on a silicon oxide film formed by a thermal oxide film method. Further, the semiconductor substrate 12 may be a single crystal substrate or an epitaxial layer formed on the single crystal substrate. As a material of the semiconductor substrate 12, silicon or a compound semiconductor is employed. A semiconductor element is formed near the upper surface of the semiconductor substrate 12 by a diffusion region.

Next, a contact hole is formed in the oxide film 16 by photolithography using, for example, dry etching using a CHF ₃ or CF ₄ gas. Then, this contact hole is buried with W.

  Next, a first wiring layer 18 is formed on the upper surface of the oxide film 16. Specifically, first, a refractory metal such as Ti or TiN is deposited as a barrier metal film on the upper surface of the oxide film 16 by sputtering. Further, an Al alloy film selected from an Al film, an Al—Si film, an Al—Si—Cu film, an Al—Cu film, or the like as a metal film is deposited on the upper surface of the barrier metal film by sputtering. Further, a high melting point metal such as TiN or TiW is deposited on the upper surface of the metal film as a reflection preventing film by sputtering. Thereafter, the barrier metal film, the metal film, and the antireflection film are selectively removed by using a photolithography technique and an etching technique, and the first wiring layer 18 is formed.

  Next, the first insulating layer 20 is formed on the oxide film 16 including the first wiring layer 18. The first insulating layer 20 is formed by stacking a TEOS film, an SOG film, and a TEOS film in this order. Here, the TEOS film is formed, for example, in a state heated to about 400 (° C.) by a CVD method. The SOG film is applied on the lower TEOS film by a spin coating method, dried at 150 to 200 (° C.), and baked at 400 (° C.).

Next, a contact hole (not shown) is formed in the first insulating layer 20 by dry etching using, for example, CHF ₃ or CF ₄ gas, using a photolithography technique. This contact hole is used to electrically connect the first wiring layer 18 and the second wiring layer 22 to be formed.

  Referring to FIG. 4B, next, a second wiring layer 22 is formed on the upper surface of the first insulating layer 20. The formation method of the second wiring layer 22 is the same as that of the first wiring layer 18 described above. That is, the second wiring layer 22 is formed by stacking and etching a barrier metal film, a metal film, and an antireflection film by a sputtering method. At this time, the second wiring layer 22 is also formed in the contact hole provided by partially removing the first insulating layer 20.

  Next, the second insulating layer 24 is formed so as to cover the upper surface of the first insulating layer 20 and the second wiring layer 22. The formation method of the second insulating layer 24 is the same as that of the first insulating layer 20 described above. That is, the second insulating layer 24 is formed by laminating the TEOS film, the SOG film, and the TEOS film in this order on the upper surface of the first insulating layer 20. Further, as in the case of the first insulating layer 20, a contact hole (not shown) penetrating the second insulating layer 24 is formed.

  Next, referring to FIG. 4C, a third wiring layer 26 is formed on the upper surface of the second insulating layer 24. The formation method of the third wiring layer 26 is the same as that of the first wiring layer 18 and the second wiring layer 22 described above. That is, the third wiring layer 26 is formed by sequentially stacking and etching a barrier metal film, a metal film, and an antireflection film on the upper surface of the second insulating layer 24 by sputtering. The pad electrode 42 is formed by making a part of the third wiring layer 26 into a pad shape.

  Next, the third insulating layer 28 is formed so as to cover the upper surface of the second insulating layer 24 and the third wiring layer 26. The third insulating layer 28 formed as the uppermost layer is called a jacket coat film or a passivation film. The third insulating layer 28 is formed by forming a TEOS film on the upper surface of the second insulating layer 24 and then covering the upper surface of the TEOS film with a SiN film. Here, the TEOS film is formed in a state heated to about 400 (° C.) by a CVD method. The SiN film is formed in a state heated to about 400 (° C.) by a plasma CVD method.

Further, the third insulating layer 28 is partially removed to provide an opening 54, and the upper surface of the pad electrode 42 formed of a part of the third wiring layer 26 is exposed from the opening 54. The partial removal of the third insulating layer 28 is performed by dry etching using a CHF ₃ or CF ₄ gas.

  Next, a process of forming the rewiring 48 will be described with reference to FIGS. In this step, the first resin layer 30 is entirely formed on the insulating layer to form the semiconductor device shown in FIG. 1B, and the first resin layer is formed only below the portion to be a pad. There is a second method of forming the semiconductor device shown in FIG. The first method will be described with reference to FIG. 5, and the second method will be described with reference to FIG.

  A first method for forming the rewiring 48 having the configuration shown in FIG. 1B will be described with reference to each drawing of FIG.

  Referring to FIG. 5A, a first resin layer 30 is formed on the upper surface of insulating film 17 formed on semiconductor substrate 12. Here, the insulating film 17 shown in this figure corresponds to the third insulating layer 28 shown in FIG. As the first resin layer 30, both a thermoplastic resin and a thermosetting resin can be employed. Specifically, a PBO film or a polyimide resin film formed by a spin coating method is used. Furthermore, the first resin layer 30 may be one in which these resin materials are filled with a filler such as granular alumina. Here, the thickness of the formed first resin layer 30 is, for example, about 10 μm.

  Referring to FIG. 5B, next, by performing selective etching, the stress relaxation portion 11 in which the first resin layer 30 is locally projected is formed. Specifically, when the resin constituting the first resin layer 30 is a photosensitive resin, after irradiating the stress relaxation portion 11 with light, the region first resin layer 30 other than the stress relaxation portion 11 is exposed from the upper surface. Dissolve in alkaline solution and remove. Here, the removal in this step is partial in the thickness direction, and is performed to such an extent that the first resin layer 30 in the region other than the stress relaxation portion 11 remains thin. For example, the removal in this step is performed so that the upper end of the stress relaxation portion 11 protrudes from the upper surface of the first resin layer 30 in another region by about 2 μm (1 μm or more and 3 μm or less). The thickness of the first resin layer 30 in a region other than the stress relaxation portion 11 is reduced to, for example, about 8 μm (7 μm or more and 9 μm or less), and the upper surface of this region is a flat surface.

  Further, the first resin layer 30 may be selectively removed using an etching mask. In this case, after the upper surface of the first resin layer 30 corresponding to the stress relaxation portion 11 is covered with an etching mask, etching is performed using an etchant such as an alkaline solution. As a result, the first resin layer 30 is selectively removed from the upper surface, and a structure in which the stress relaxation portion 11 protrudes locally is obtained. Further, by removing the first resin layer 30 by isotropically proceeding etching, the side surface of the stress relaxation portion 11 becomes a certain inclined surface spreading downward. In other words, the stress relaxation part 11 has a trapezoidal shape in which the cross section of the stress relaxation part 11 spreads. This has an advantage that a rewiring made of metal can be easily formed on the side surface of the stress relaxation portion 11 in a later process.

  Further, separately from the above processing, the upper surface of the pad electrode 42 is exposed from the opening of the first resin layer 30 by removing the portion of the first resin layer 30 covering the pad electrode 42.

  Furthermore, in the above process, the stress relaxation portion 11 that protrudes is formed by etching back the first resin layer 30 from the upper surface. However, the stress relaxation portion 11 can be provided by other methods. For example, after the flat first resin layer 30 having a desired thickness is formed, the stress relaxation portion 11 made of a separate resin may be formed on the upper surface of the first resin layer 30 by a technique such as potting.

  Next, referring to FIG. 5C, the rewiring 48 is formed on the upper surface of the first resin layer 30. As described above, the rewiring 48 includes the pad portion 44 formed on the upper surface of the stress relaxation portion 11 and the elongate wiring portion 19 that continues the pad portion 44 and the pad electrode 42 on the semiconductor substrate 12 side. The A part of the wiring part 19 is also formed on the opening provided by removing the first resin layer 30 and the upper surface of the pad electrode 42 exposed from the opening.

  A specific method for manufacturing the rewiring 48 is formed by forming a plating metal layer on the upper surface of the first resin layer 30 and then forming a Cu plating layer on the plating metal layer. Here, the plating metal layer is formed by laminating a Cu layer or a nickel (Ni) layer on a refractory metal film composed of a chromium (Cr) layer, a Ti layer, or a TiW layer. These metal layers for plating are formed by sputtering. The Cu plating layer is made of copper formed on the surface of the plating metal layer by electrolytic plating.

  Here, the rewiring 48 is formed on the flat upper surface of the first resin layer 30, the upper surface and the side surface of the stress relaxation portion 11. As described above, since the side surface of the stress relaxation portion 11 is an inclined surface that extends downward, it is easy to form a metal film at this location by sputtering.

  Next, referring to FIG. 5D, the upper surface of the first resin layer 30 and the rewiring 48 are covered with the second resin layer 32. The material of the second resin layer 32 may be the same as that of the first resin layer 30 described above, and a PBO film or a polyimide resin film formed by spin coating is used. Then, by partially removing the second resin layer 32 using a photolithography technique, the opening 13 from which the upper surface of the pad portion 44 is exposed is formed.

  Here, the width of the lower end of the opening portion 13 is set to be shorter than the width of the pad portion 44. As a result, only the flat portion of the pad portion 44 is exposed to the opening 13, and the step around the pad portion 44 is not exposed from the opening 13. As a result, the external terminal to be formed and the pad portion 44 are in good contact.

  Furthermore, the side surface of the opening 13 is an inclined surface that spreads outward (upward). As a result, the occurrence of constriction in the external terminal disposed in the opening 13 is suppressed, and the occurrence of cracks in the external terminal during stress action is prevented.

  A second method for forming the rewiring having the configuration shown in FIG. 1C will be described with reference to each drawing of FIG. This second method is the same as the first method except for the method of forming the stress relaxation portion 11. Therefore, it demonstrates centering on the formation method of the stress relaxation part 11 which is a difference, and the overlapping description is omitted.

  With reference to FIG. 6A, first, the upper surface of the insulating film 17 is covered with the first resin layer 30. In the above description, the thickness of the first resin layer 30 is about 10 μm, but it may be about the same as the stress relaxation portion to be formed in this step (2 μm (1 μm or more and 3 μm or less)).

  Referring to FIG. 6B, next, the stress relieving portion 11 is formed by removing the first resin layer 30 leaving only the portion where the pad portion is formed. The partial removal of the first resin layer 30 may be the same as in the first method. By this step, the insulating film 17 is exposed in a region other than the stress relaxation portion 11. Here, as a method of forming the stress relaxation portion 11, the stress relaxation portion 11 is not formed from the first resin layer 30 covering the entire surface of the insulating film 17, but a resin material having a shape shown in FIG. May be formed only on the upper surface of the insulating film 17.

  Next, referring to FIG. 6C, a rewiring 48 including a pad portion 44 and a wiring portion 19 is formed. The pad portion 44 is formed on the flat upper surface of the stress relaxation portion 11, and the wiring portion 19 is formed directly on the upper surface of the insulating film 17.

  Next, referring to FIG. 6D, the upper surfaces of the rewiring 48 and the insulating film 17 are covered with the second resin layer 32. Furthermore, the upper surface of the pad portion 44 is exposed from the opening portion 13 by removing the second resin layer 32 where the pad portion 44 is disposed and providing the opening portion 13.

  After the above process is completed, referring to FIG. 6D, a solder cream that is a mixture of powdered solder and flux is applied to the pad 44 exposed from the opening 13, and then the solder cream is applied. The external terminals are formed by melting.

  Finally, the semiconductor wafer 50 shown in FIG. 3A is cut into small pieces to obtain a WLP semiconductor device. Specifically, the semiconductor substrate 12 and each layer stacked on the upper surface thereof are cut along the scribe line 52 using a dicing saw that rotates at high speed.

  Through the above process, the semiconductor device 10 having the structure shown in FIG. 1 is manufactured.

DESCRIPTION OF SYMBOLS 10 Semiconductor device 11 Stress relaxation part 12 Semiconductor substrate 13 Opening part 14 Element formation area 15 Wiring layer 16 Oxide film 17 Insulating film 18 1st wiring layer 19 Wiring part 20 1st insulating layer 22 2nd wiring layer 24 2nd insulating layer 26 Third wiring layer 28 Third insulating layer 30 First resin layer 32 Second resin layer 34 Scribe area 36 Mounting substrate 38 Conductive path 42 Pad electrode 44 Pad portion 46 External terminal 48 Rewiring 50 Semiconductor wafer 52 Scribe line 54 Opening

Claims (9)

A semiconductor substrate;
An insulating layer covering at least one wiring layer provided on one main surface of the semiconductor substrate;
Rewiring composed of a pad portion to which an external terminal is connected, a pad electrode composed of the wiring layer, and a wiring portion that connects the pad portion;
A stress relieving portion made of a resin material disposed between the pad portion and the insulating layer,
The semiconductor device according to claim 1, wherein the wiring portion of the rewiring is disposed closer to the semiconductor substrate side than the pad portion. The rewiring is formed on an upper surface of a resin layer covering the insulating layer,
The stress relaxation portion is a portion where the resin layer is projected in a region where the pad portion is disposed, and the wiring portion of the rewiring is formed thinner than a portion where the stress relaxation portion is provided. The semiconductor device according to claim 1, wherein the semiconductor device is disposed on an upper surface of the resin layer.   3. The semiconductor device according to claim 2, wherein the stress relaxation portion is made of a resin mixed with a filler.   The semiconductor device according to claim 3, wherein the stress relaxation portion has a thickness of 2 μm or more.   The semiconductor device according to claim 1, wherein the wiring portion of the wiring layer is in direct contact with the upper surface of the insulating layer covering the semiconductor substrate. A semiconductor wafer having a semiconductor substrate, a wiring layer connected to an element formation region of the semiconductor substrate, an insulating layer covering the wiring layer, and a pad electrode formed of a part of the wiring layer exposed from the insulating layer A process of preparing
A step of providing a stress relaxation portion mainly made of a resin on the upper surface of the insulating layer in a region where a pad portion to which an external terminal is connected is provided;
A rewiring is formed that includes the pad portion disposed on the upper surface of the stress relaxation portion, and a wiring portion that connects the pad and the pad electrode, and the wiring portion is closer to the semiconductor substrate than the pad portion. A process of arranging in
A method for manufacturing a semiconductor device, comprising: In the step of providing the stress relieving portion, the insulating layer is covered with a resin layer in which the stress relieving portion is configured by a locally protruding portion,
7. The semiconductor device according to claim 6, wherein in the step of forming the rewiring, the wiring portion of the rewiring is disposed on an upper surface of the resin layer in a thin portion where the stress relaxation portion is not provided. Manufacturing method.   8. The method of manufacturing a semiconductor device according to claim 7, wherein a side surface of the stress relaxation portion is an inclined surface that spreads toward the semiconductor substrate side. In the step of providing the stress relaxation part, the stress relaxation part made of a resin layer is formed only in a region where the pad part is disposed,
The method for manufacturing a semiconductor device according to claim 6, wherein in the step of forming the rewiring, the wiring portion of the rewiring is formed directly on an upper surface of the insulating layer.

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