JP2011019113A - Solid-state imaging element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state imaging element without generating a lateral smear characteristic when imaging a high-luminance object, in a solid-state imaging element equipped with a buffer amplifier at the output of a column amplifier.SOLUTION: In this solid-state imaging element 101 including: pixels arranged in a two-dimensional shape, and each having a photoelectric conversion part for converting light to an electric signal; a plurality of vertical signal lines VLINE each used for receiving electric signals read from the pixels arranged in a column direction; column amplifiers CAMP each having a first constant current source for amplifying the electric signals read to the vertical signal line; buffer amplifiers BF arranged in series to the column amplifiers and each having a second constant current source; and horizontal output circuits for horizontally outputting electric signals output by the buffer amplifiers, a first grounding line 105 for grounding the first constant current sources of the column amplifiers and a second grounding line 107 for grounding the second constant current sources of the buffer amplifiers are arranged, and the first grounding line and the second grounding line are arranged independently of each other and grounded at both mutual ends.

Description

  The present invention relates to a solid-state image sensor for capturing a subject image.

  In recent years, electronic cameras using a CCD type or CMOS type solid-state imaging device have been widely used. For example, a CMOS-type solid-state imaging device is converted into an electrical signal corresponding to the amount of incident light by a photoelectric conversion unit of pixels arranged in a two-dimensional matrix and is read out to a vertical signal line arranged in each column by column. After amplification by the amplifier, a signal read in units of rows is output to the outside of the solid-state imaging device in a column order by a horizontal output circuit.

  On the other hand, if the gain of the column amplifier is increased for higher sensitivity, the amount of negative feedback is reduced and the bandwidth is narrowed, so the time until the output of the column amplifier stabilizes increases and the readout time increases significantly. There is a problem. Therefore, in order to solve this problem, a method of providing a buffer amplifier at the output of the column amplifier is considered (for example, see Patent Document 1).

JP 2008-034974 A

  However, when the buffer amplifier is provided at the output of the column amplifier, the readout time is improved, but there is a problem that the lateral smear characteristic when the high-luminance subject is in the shooting screen is greatly deteriorated.

  An object of the present invention is to provide a solid-state imaging device capable of obtaining a high-quality image without lateral smear when imaging a high-luminance subject in a solid-state imaging device provided with a buffer amplifier at the output of a column amplifier. .

  The inventor has analyzed the above problems and found the cause. That is, the above problem is caused by the Id / Vds characteristics of the drain current (Id) and the drain-source voltage (Vds) of the MOS transistor, and the Vds of the MOS transistor of the common current source of the buffer amplifier is the level of the output signal of the column amplifier. Therefore, the Id corresponding to the output signal of the high-luminance pixel increases relative to the Id of the low-luminance pixel, and this Id difference appears as the level difference of the ground line in the row direction. It was.

  A solid-state imaging device according to the present invention is arranged in a two-dimensional form, has a pixel having a photoelectric conversion unit that converts light into an electrical signal, and is connected to the pixel arranged in the column direction in the column direction, and read from the pixel. A plurality of vertical signal lines that receive electrical signals to be transmitted; a column amplifier that includes a first constant current source that amplifies the electrical signals read to the vertical signal lines; In a solid-state imaging device having a buffer amplifier having a constant current source and a horizontal output circuit for outputting an electric signal output from the buffer amplifier in the horizontal direction, the first constant current of the column amplifier is arranged in the row direction. A first ground line for grounding the source, and a second ground line arranged in the row direction and grounding the second constant current source of the buffer amplifier, and the first ground line and the second ground line are provided. Ground wire is independent Disposed Te, and said first ground line and the second ground line, characterized in that it is grounded at both ends of each other.

  In addition, the solid-state imaging device according to the present invention is two-dimensionally arranged and includes a pixel having a photoelectric conversion unit that converts light into an electric signal, the pixel arranged in a column direction, and the pixel connected in the column direction. A plurality of vertical signal lines for receiving an electrical signal read from the column amplifier, a column amplifier having a first constant current source for amplifying the electrical signal read to the vertical signal line, and the column amplifier. In a solid-state imaging device having a buffer amplifier having a second constant current source and a horizontal output circuit for outputting an electric signal output from the buffer amplifier in a horizontal direction, the second constant current source of the buffer amplifier has a cascode configuration It is characterized by that.

  In the present invention, even when there is a high-luminance subject in the photographed image, fluctuations in the ground potential that cause lateral smear can be reduced, so that a high-quality image without lateral smear can be obtained.

1 is a block diagram of a solid-state image sensor 101 according to a first embodiment. It is a circuit diagram of pixel P (m, n). It is a timing chart. It is explanatory drawing which shows the grounding part of column amplifier CAMP (n) and buffer BF (n). It is explanatory drawing which shows the voltage distribution of the row direction when not isolate | separating the ground GND of buffer BF (y). It is explanatory drawing which shows the voltage distribution of the row direction when isolate | separating the ground GND of buffer BF (y). It is a block diagram of the solid-state image sensor 101b which concerns on 2nd Embodiment. FIG. 3 is an equivalent circuit diagram of a column amplifier CAMP (n) and a buffer BF ′ (n). It is explanatory drawing for demonstrating the effect of the cascode connection of a common current source.

Hereinafter, embodiments of the solid-state imaging device according to the present invention will be described in detail with reference to the drawings.
(First embodiment)
FIG. 1 is a block diagram showing a solid-state imaging device 101 according to the first embodiment. The solid-state imaging device 101 includes M × N pixels P (x, y), a vertical signal line VLINE (y), a constant current source PW (y), a column amplifier CAMP (y), and a vertical scanning circuit 102. And a horizontal output circuit 103 and a buffer BF (y). Here, x represents a row number with a natural number of 1 to M, and y represents a column number with a natural number of 1 to N. The M × N pixels P (x, y) constitute the imaging unit of the solid-state imaging device 101 and are arranged in a matrix of M rows and N columns. Hereinafter, except for the case where a specific circuit is described as an example, the same circuit is represented as (x), (y) and (x, y).

  A signal read from each pixel P (x, y) is read to the vertical signal line VLINE (y) corresponding to each column. Further, a constant current source PW (y) constituting a source follower circuit is arranged for each column on the vertical signal line VLINE (y) of each column. The ground of each pixel P (x, y) is connected to the pixel ground line PGND (y) arranged in the column direction for each column. Further, the pixel ground line PGND (y) is connected at each column position a (y) of the first ground line 105 having a length corresponding to at least the length of the row arranged in the row direction.

  A reference voltage VREF is applied by a reference voltage line 106 to a positive input terminal of a column amplifier CAMP (y) that amplifies a signal read from each pixel P (x, y). Further, the buffer BF (y) is grounded at each column position b (y) of the second ground line 107 having a length corresponding to at least the length of the row arranged in the row direction. The first ground line 105 and the second ground line 107 are connected to the external ground GND at both end positions of the row (in the case of FIG. 1, the leftmost connection point G1 and the rightmost connection point G2).

  Here, the solid-state imaging device 101 according to the present embodiment has a circuit configuration in which the buffer BF (y) is disposed in the subsequent stage of the column amplifier CAMP (y). The reason why the buffer BF (y) is arranged at the subsequent stage of the column amplifier CAMP (y) is as follows. When the gain of the column amplifier CAMP (y) is set high (for example, 10 times or more) in order to increase the sensitivity of the solid-state imaging device 101, the negative feedback amount is reduced and the bandwidth of the amplifier is reduced. When the value is large, it takes time until the output is settled, resulting in a problem that the readout time is greatly increased. For example, in the n-th column of FIG. 1, when there is no buffer BF (n) and the gain of the column amplifier CAMP (n) is increased, a capacitor Cd or a capacitor having a relatively large capacity for driving the horizontal output circuit 103 is used. Since Cs becomes a load capacity, the above-mentioned problem becomes remarkable. In order to solve this problem, a technique is known in which a buffer BF (y) is arranged after the column amplifier CAMP (y) of each column.

  However, when the buffer BF (y) is provided after the column amplifier CAMP (y), the above problem can be solved and the readout time can be shortened, but the lateral smear characteristic at the time of photographing a high-luminance subject is greatly deteriorated. Newly occurs. Incidentally, when the buffer BF (y) is provided, the reason why the lateral smear characteristic at the time of photographing a high brightness subject is greatly deteriorated is as follows. In the prior art, since the ground GND of the buffer BF (y), the column amplifier CAMP (y), and the pixel ground line PGND (y) are connected to the same ground line arranged in the row direction, the buffer BF When the ground potential of (y) greatly fluctuated, the ground potential of the column amplifier CAMP (y) and the pixel ground line PGND (y) also fluctuated, and as a result, a lateral smear appeared in the captured image. The ground potential variation mechanism will be described in detail later.

  The solid-state imaging device 101 according to the present embodiment includes a ground line that connects the ground GND of the buffer BF (y) and a ground line that connects the ground GND of the column amplifier CAMP (y) and the pixel ground line PGND (y). By dividing, even in a circuit configuration in which the buffer BF (y) is arranged at the subsequent stage of the column amplifier CAMP (y), the circuit configuration can prevent the occurrence of lateral smear.

  Next, the circuit of each part of the solid-state image sensor 101 shown in FIG. 1 will be described in detail. The vertical scanning circuit 102 outputs a timing signal for reading the signal of the pixel P (x, y) to the vertical signal line VLINE (y) arranged for each column in a row unit. For example, in the m-th row, the timing signal φSEL (m), the timing signal φRES (m), and the timing signal φTX () are applied to all the N columns of pixels from the pixel P (m, 1) to the pixel P (m, N). m).

  Here, the configuration of the pixel P (x, y) will be described with reference to FIG. FIG. 2 shows a circuit diagram of the pixel P (m, n) in the m-th row and the n-th column. The M × N pixels P (x, y) have the same circuit configuration. In FIG. 2, a pixel P (m, n) includes a photodiode PD, a transfer transistor Tr1, an amplification transistor Tr2, a selection transistor Tr3, and a reset transistor Tr4. Note that VDD indicates a power source, GND indicates ground, and FD indicates a floating diffusion portion (floating diffusion region). The timing signal φSEL (m), the timing signal φRES (m), the timing signal φTX (m), and the vertical signal line VLINE (n) are the same as those in FIG. The ground GND of the pixel P (m, n) is connected to the pixel ground line PGND (n), and the pixel ground line PGND (n) is connected to the first ground line 105 at each column position a (n).

  In FIG. 2, light incident on the photodiode PD is photoelectrically converted and accumulated as electric charges. The charge accumulated in the photodiode PD is transferred to the FD section when the timing signal φTX (m) is input to the gate of the transfer transistor Tr1, and is amplified by the amplification transistor Tr2. The signal amplified by the amplification transistor Tr2 is read out to the vertical signal line VLINE (n) when the timing signal φSEL (m) is input to the gate of the selection transistor Tr3. When the timing signal φRES (m) is input to the gate of the reset transistor Tr4, the FD section is reset to the reset voltage (VDD−Vt−ΔVt). Here, Vt is a threshold voltage, and ΔVt is a fluctuation due to the back gate effect. The operation of each timing signal will be described in detail later.

  In this manner, the signal of the pixel P (x, y) is read out to the corresponding vertical signal line VLINE (y) and then input to the column amplifier CAMP (y) arranged for each column. The

  Here, a signal read to the vertical signal line VLINE (n) in FIG. 2 will be described. The signal read out to the vertical signal line VLINE (n) is an image signal including optical information of a captured image from each pixel P (m, n) or a dark signal including a noise component before image signal accumulation. Subject light incident on the photodiode PD is photoelectrically converted into electric charge by the photodiode PD. The charge is transferred to the FD portion by the transfer transistor Tr1, and a potential corresponding to the charge is applied to the gate electrode of the amplification transistor Tr2. The image signal is a signal read to the vertical signal line VLINE (n) through the selection transistor Tr3 at this time. On the other hand, the dark signal is a signal obtained by reading the potential of the FD portion to the vertical signal line VLINE (n) through the amplification transistor Tr2 and the selection transistor Tr3 when the charge held in the FD portion is reset by the reset transistor Tr4. It is. Here, the potential of the FD portion is a value with respect to the ground GND of the pixel connected to the pixel ground line PGND (n).

  In this way, an image signal or a dark signal is read from the pixel P (m, n) to the vertical signal line VLINE (n) and input to the column amplifier CAMP (n). Although the pixel P (m, n) has been described here, the same applies to the other pixels P (x, y).

  Next, the column amplifier CAMP (n) in the nth column will be described. The other column amplifiers CAMP (1) to CAMP (N) operate in the same manner as the column amplifier CAMP (n) in the nth column.

  The column amplifier CAMP (n) in FIG. 1 is an inverting amplifier having an amplification factor that includes a capacitor Cf and a capacitor Cin and is determined by a ratio of capacitance values of these capacitors. The source and drain of the amplifier reset transistor Tr5 are connected to both ends of the capacitor Cf of the feedback circuit of the column amplifier CAMP (n). When the timing signal φCARST is applied to the gate of the transistor Tr5, the charge accumulated in the capacitor Cf is discharged and reset. Note that the solid-state imaging device 101 accumulates the dark signal read from the pixel after reset in the capacitor Cin, and then reads the image signal. Thereby, the column amplifier CAMP (n) subtracts the dark signal from the image signal when reading, and removes the variation between the pixels.

  The output side of the column amplifier CAMP (n) is connected to the drains of the image signal storage transistor Tr6 and the dark signal storage transistor Tr7. After the column amplifier CAMP (n) is reset, when the timing signal φTD is input to the gate of the dark signal storage transistor Tr7, the dark signal storage transistor Tr7 is turned on and the capacitor Cd is connected to the column amplifier CAMP (n). It is charged until the output voltage is reached. After the image signal is read from the pixel, when the timing signal φTS is input to the gate of the image signal storage transistor Tr6, the image signal storage transistor Tr6 is turned on, and the capacitor Cs is connected to the column amplifier CAMP (n). It is charged until the output voltage is reached. The voltage of the capacitor Cs is input to the horizontal output circuit 103 as an image signal, and the voltage of the capacitor Cd is input as a dark signal (offset signal of the column amplifier CAMP).

  The horizontal output circuit 103 receives the image signal accumulated in the capacitor Cs for each column and the dark signal accumulated in the capacitor Cd, and outputs them to the outside in the column order in units of rows. At this time, in order to reduce the variation between the columns of the column amplifier CAMP (y), the image signal stored in the capacitor Cs by the output differential amplifier (not shown) of the horizontal output circuit 103 is stored in the capacitor Cd. The dark signal is subtracted, and a signal from which the inter-column variation of the column amplifier CAMP (y) is removed is output to the outside of the solid-state imaging device 101. The process of subtracting the dark signal from the image signal may be performed in the solid-state image sensor 101. The image signal and the dark signal are separately output from the solid-state image sensor 101, and the dark signal is externally generated from the image signal. You may make it subtract.

  Here, a series of operations from reading out the dark signal and the image signal from each pixel P (x, y) until each signal is held in the capacitor Cd and the capacitor Cs in each column will be described with reference to the timing chart of FIG. I will explain.

  FIG. 3 shows the timing when signals are read from the m-th row and the (m + 1) -th row. In FIG. 3, during a period T <b> 1, signals for one row read from N pixels P (m−1, y) in the (m−1) th row are read from the horizontal output circuit 103 in the column order, and It shows the period of output to the outside.

  The next period T2 is a period from when the dark signal and the image signal for one row are read from each pixel P (m, y) in the m-th row until each signal is held in the capacitor Cd and the capacitor Cs in each column. Is shown. At the start of the period T2, first, the timing signal φSEL (m) is turned on in the period T5, and at the same time, the timing signal φRES (m) is turned off in the period T5. Since the timing signal φSEL (m) is on, the timing signal φTX (m) is off, and the timing signal φRES (m) is off, as described with reference to FIG. Data is read out to the vertical signal line VLINE (y) via Tr2 and the selection transistor Tr3.

  Next, since the timing signal φTD (m) is turned on in the period T6, the dark signal read out to the vertical signal line VLINE (y) during the period T6 passes through the column amplifier CAMP (y) and the transistor Tr7. Until the timing signal φTD (m) is turned off.

  Next, after the timing signal φTD (m) is turned off, the timing signal φTX (m) is turned on in the period T7. In the period T7, the electric charge accumulated in the photodiode PD that enters the subject light is transferred to the FD portion via the transfer transistor Tr1. A potential corresponding to the charge transferred to the FD unit is applied to the gate of the amplification transistor Tr2, and an image signal is output from the amplification transistor Tr2 and read out to the vertical signal line VLINE (y) via the selection transistor Tr3.

  Next, since the timing signal φTS is turned on in the period T8, the image signal read to the vertical signal line VLINE (y) is turned off until the timing signal φTS is turned off via the column amplifier CAMP (y) and the transistor Tr6. Accumulated in the capacitor Cs of each column.

  When the dark signal and the image signal are respectively stored in the capacitor Cd and the capacitor Cs in each column, reading of the dark signal and the image signal for one row from each pixel P (m, y) in the m-th row is completed. The timing signal φSEL (m) is turned off and the timing signal φRES (m) is turned on.

  In the next period T3, the horizontal output circuit 103 reads the dark signals and image signals for the N columns of the m-th row stored in the capacitors Cd and Cs of each column in order of the columns, and Output to the outside.

  In the next period T4, the timing signals φSEL (m + 1), φRES (m + 1), φTX in the (m + 1) th row are the same as the timing signals φSEL (m), φRES (m), φTX (m) in the period T2. By (m + 1), the dark signal and the image signal are read from each pixel P (m + 1, y) in the (m + 1) th row and stored in the capacitor Cd and the capacitor Cs in each column, respectively. The dark signal and the image signal for the N columns of the (m + 1) th row respectively stored in the capacitor Cd and the capacitor Cs of each column are read in the column order by the horizontal output circuit 103 and output to the outside of the solid-state imaging device 101. Is done.

  Next, the characteristic part of the solid-state imaging device 101 according to the present embodiment will be described in detail. The solid-state imaging device 101 according to the present embodiment includes a second ground line 105 connected to the ground GND of the buffer BF (y) arranged at the subsequent stage of the column amplifier CAMP (y), and the column amplifier CAMP (n). That is, the ground GND and the first ground line 105 to which the pixel ground line PGND (n) is connected are independently wired separately.

  Here, in order to make the features of the present embodiment easy to understand, a detailed description will be given with reference to FIG. 4 in which circuit portions of the n-th column amplifier CAMP (n) and the buffer BF (n) are extracted. 1 denote the same components as those in FIG. 4, the second ground line 107 to which the ground GND of the buffer BF (n) is connected, and the first ground line to which the ground GND of the column amplifier CAMP (n) and the pixel ground line PGND (n) are connected. 105 are arranged in parallel in the row direction of the solid-state imaging device 101 as independent ground wires of different systems except that they are connected to each other at the positions of the connection points G1 and G2 at both ends of the row.

  As shown in FIG. 4, the second ground line 107 that connects the ground GND of the buffer BF (n), and the first ground that connects the ground GND of the column amplifier CAMP (n) and the pixel ground line PGND (n). Even if the ground potential of the buffer BF (n) fluctuates in the circuit configuration in which the buffer BF (n) is arranged at the subsequent stage of the column amplifier CAMP (n) by separating the ground line 105 from the column line CAMP (n). Variations in the ground potential of the amplifier CAMP (n) and the pixel ground line PGND (n) can be suppressed. As a result, occurrence of lateral smear can be prevented even when a high-luminance subject is in the shooting screen.

  Here, the potential variation of the ground line when the ground GND of the buffer BF (n) and the ground GND of the column amplifier CAMP (n) and the pixel ground line PGND (n) are connected to a common ground line is shown in FIG. Will be described. In FIG. 5, the same reference numerals as those in FIGS. 1 and 4 denote the same components. In FIG. 5, three current sources of a constant current source PW (y), a column amplifier CAMP (y), and a buffer BF (y) are connected to each column of the common ground line 201 at a connection point p (y). Yes. The ground point p (y) is also a connection point of the pixel ground line PGND (y) in each column. Further, in FIG. 5, it is depicted as being connected to one point of the ground point p (y), but in an actual circuit pattern, the constant current source PW (y), the column amplifier CAMP (y), and the buffer BF (y ) Are not necessarily the same on the ground line 201, and include cases where they are connected to positions close to each other. However, in FIG. It is drawn.

  In FIG. 5, a current I1 (y) is a load current of a constant current source PW (y), a current I2 (y) is a load current of a common current source of a column amplifier CAMP (y), and a current I3 (y) is a buffer BF ( The load current of the common current source of y) is shown respectively. Here, particularly in the case of a solid-state imaging device having a large number of pixels, the ground line 201 includes thousands of constant current sources PW (y), a column amplifier CAMP (y), and a buffer BF (y). The common ground line 201 is connected at p (y). In view of the mask pattern configuration, the ground line 201 is grounded to the external GND at the left and right ends (left and right ends of the chip).

  However, in a relatively large solid-state imaging device, the total length of the ground line 201 is on the order of several tens of millimeters, so that an operating current is supplied to the ground line 201 from several thousands of circuits arranged in parallel on the line. Flows in. As a result, the potential difference caused by this current and the distributed resistance r is integrated between the columns, so that the potential of the ground line 201 near the center of the row increases and decreases toward the external GND at both ends of the row. The potential changes depending on the position of each column 201. Further, since the pixel ground line PGND (y) of each column is wired in the vertical direction with the ground line 201 as a base point, the ground potential of each pixel P (x, y) is similarly distributed in the horizontal direction. A graph (a) in FIG. 5 is a diagram showing a state of potential change in the row direction of the ground line 201 when it is assumed that the ground line 201 is a wiring path distributed by the resistance r between the columns. It is drawn corresponding to the position of the drawn ground line 201 in the row direction. Therefore, the horizontal axis indicates the position in the row direction of the ground line 201 corresponding to the above figure, and the vertical axis indicates the potential with respect to the external GND.

  In the graph (a) in FIG. 5, as described above, both ends of the row of the ground line 201 are grounded to the external GND, so the potential is 0 (external ground potential). The potential of the ground line 201 becomes higher toward the center of the line. Ideally, as in the characteristic 303, the potential must be constant regardless of the ground point p (y) of each column, but the FD portion of each pixel P (x, y) is based on VDD. Reset and dark signals and image signals are generated based on the reset potential, so even if there is a difference in ground potential between pixels, if there is no temporal change and it is constant, it will be canceled at the time of readout, so signal output Will not be affected.

  However, when a high-luminance subject such as illumination is included in the effective pixel area arranged in a two-dimensional matrix, the current flowing from the common current source of the buffer BF (y) to the ground point p (y) of the ground line 201 is also present. The potential of the corresponding row of the ground line 201 distributed greatly due to the inter-column resistance r increases as a whole. Even if the current change of the common current source of each buffer BF (y) in each column is as small as several μA, if the size of the high-brightness object is several hundred to several thousand columns, A small current fluctuation may be several mA to several tens of mA. Therefore, when a row including such a high brightness subject is selected, the ground line 201 when a signal is read from each pixel P (x, y) with respect to the potential of the ground line 201 at the time of resetting. Changes in the order of several tens to several hundreds μV. Then, a slight difference in level occurs between the ground line potential when reading a dark signal of a row with a high-luminance subject and the ground line potential of a row without an adjacent high-luminance subject, and this level difference is caused by the grounding of the FD of the pixel. Because of the potential difference, a slight level difference also occurs in the dark signal output voltage. As a result, white smear occurs on both sides of the high brightness subject portion of the photographed image. In an actual image, in an image where the illumination is extremely bright like a night street lamp and the background is extremely dark, a lateral smear that can be perceived even with a slight level difference appears. The reason why the current of the common current source of the buffer BF (y) largely fluctuates will be described in detail with reference to an equivalent circuit diagram of the second embodiment.

  Due to the above phenomenon, for example, in the graph (a), the potential change of the dark signal ground line 201 in the row where there is no high-luminance subject is characteristic 302, and the potential change of the dark signal ground line 201 in the row where there is a high-luminance subject is characteristic. If 301, the potential of the characteristic 301 is higher than the potential of the characteristic 302, and a slight potential difference actually occurs. Since this potential difference is transmitted to the amplification transistor Tr2 as a difference in ground potential of the FD portion of each pixel P (x, y), a slight difference occurs in the output of the dark signal, and the high luminance of the image finally output A horizontal smear will appear on the line where the part is located. Conventionally, measures have been taken to increase the GND wiring width so as to make the impedance of the ground line as low as possible. However, there is a design limit such as an increase in the chip area in the thickness, and the residual resistance component is reduced. Therefore, the essential problem was not solved.

  As shown in FIG. 1, the solid-state imaging device 101 according to the present embodiment includes the second ground line 107 to which the ground GND of the buffer BF (y) is connected, the ground GND of the column amplifier CAMP (y), and the pixel. The first ground line 105 to which the ground line PGND (y) is connected is arranged in parallel as a separate line of ground wiring except for the connection points G1 and G2 at both ends of the row. Accordingly, as shown in FIG. 6, the second ground line 107 to which the ground GND of the buffer BF (y) is connected, the ground GND of the column amplifier CAMP (y), and the pixel ground line PGND (y) are separately provided. Thus, the influence of the fluctuation of the load current of the common current source of the buffer BF (y) on the ground GND of the column amplifier CAMP (y) and the pixel ground line PGND (y) is eliminated.

  As described above, the solid-state imaging device 101 according to the present embodiment can eliminate the influence of the fluctuation of the ground potential of the buffer BF (y) that causes the lateral smear even when the captured image includes a high-luminance subject. A high-quality image with no image can be obtained.

(Second Embodiment)
Next, the solid-state imaging device 101b according to the second embodiment will be described. The solid-state imaging device 101b according to the present embodiment is different from the solid-state imaging device 101 according to the first embodiment in that there is no second ground line 107, the ground GND of the column amplifier CAMP (y) and the pixel ground line PGND ( y) and the ground GND of the buffer BF ′ (y) are all connected to the first ground line 105, and the circuit configuration of the buffer BF ′ (y) is different. In FIG. 7, the same reference numerals as those of the solid-state imaging device 101 in FIG. The configuration and operation timing of each pixel of the solid-state imaging device 101b are exactly the same as the pixel configuration and operation timing described with reference to FIGS.

  In the solid-state imaging device 101 b according to the present embodiment, the ground GND of the column amplifier CAMP (y), the pixel ground line PGND (y), and the ground GND of the buffer BF ′ (y) are all connected to the first ground line 105. Therefore, the ground line 201 in FIG. 5 described in the first embodiment corresponds to the first ground line 105. However, in the present embodiment, the problem of lateral smear can be avoided by devising the circuit configuration of the buffer BF ′ (y).

  Next, the circuit configuration of the buffer BF ′ (y), which is a feature of this embodiment, will be described. FIG. 8 is a diagram showing an equivalent circuit example of the column amplifier CAMP (n) and the buffer BF ′ (n) in the nth row. In FIG. 8, a column amplifier CAMP (n) is a circuit of a double cascode differential amplifier. A low-voltage current mirror circuit on the load side includes a cascode pair of a transistor Tr21 and a transistor Tr22 and a cascode pair of a transistor Tr25 and a transistor Tr26. Composed. Similarly, the cascode pair of the transistor Tr23 and the transistor Tr24 and the cascode pair of the transistor Tr27 and the transistor Tr28 constitute a low-voltage current mirror circuit on the differential input side. The sources of the transistors Tr24 and Tr28 on the differential input side are connected to the ground GND via a transistor Tr29 which is a current source. Further, the bias BIAS1 is applied to the gates of the transistors Tr22 and Tr26, the bias BIAS2 is applied to the gates of the transistors Tr23 and Tr27, and the bias BIAS3 is applied to the gate of the transistor Tr29. Since a constant current flows through the transistor Tr29 constituting the common current source of the double cascode differential amplifier type column amplifier CAMP (n), the negative input (VLINE (n)) of the column amplifier CAMP (n) And the positive voltage (VREF) is output to the buffer BF ′ (n).

  On the other hand, in FIG. 8, the buffer BF ′ (n) is a circuit of a single differential amplifier, but is characterized by a circuit configuration of a common current source, and a common current source normally composed of one transistor Tr35 is designated as a transistor Tr35. And a cascode circuit of the transistor Tr36. The buffer BF ′ (n) includes a pair of a transistor Tr31 and a transistor Tr33, and a pair of a transistor Tr32 and a transistor Tr34. The sources of the transistors Tr32 and Tr34 on the differential input side are connected to the ground GND via the transistors Tr36 and Tr35 which are common current sources. A bias BIAS4 is applied to the gate of the transistor Tr36, and a bias BIAS5 is applied to the gate of the transistor Tr35.

  Here, since the transistors Tr35 and Tr36 constituting the common current source of the buffer BF ′ (n) have a cascode configuration, the output impedance at the point B1 can be increased, and even when the drain voltage of the transistor Tr35 increases. The increase in the current of the common current source can be suppressed to such an extent that the influence of the fluctuation of the potential of the ground line 105 can be ignored. This principle is shown in FIG. FIG. 9 is a diagram showing an equivalent circuit of the common current source of the buffer BF ′ (n). The equivalent circuit of the conventional common current source which is not cascoded is one transistor Tr35 as shown in FIG. 9A. The output impedance at point B1 in FIG. 9A corresponds to the output impedance r01 between the source and drain of the transistor Tr35.

  In FIG. 8, when the buffer BF ′ (n) is composed of only one transistor Tr35 as shown in FIG. 9A, the output of the column amplifier CAMP (n) becomes excessive when there is a high brightness subject, Following the output level of the column amplifier CAMP (n), the potential at the point B of the common current source of the buffer BF ′ (n) also changes greatly. In general, the saturation characteristic of a MOS transistor exhibits a resistance curve characteristic of several tens of kΩ to several hundreds of kΩ due to the channel length modulation effect, and therefore the value of the drain current Id of the common current source of the buffer BF ′ (n) corresponding to the high luminance pixel. Increases relatively with respect to the drain current Id of the low luminance pixel.

  In contrast, the common current source of the buffer BF ′ (n) of the solid-state imaging device 101b according to the present embodiment has a circuit configuration in which the transistors Tr35 and Tr36 are cascoded as shown in FIG. 9B. Therefore, the output impedance of the point B1 is r02 · gm2 · r01, which is significantly higher than the output impedance of the point B1 when the transistor Tr35 is constituted by one. As a result, the change in the drain current Id can be suppressed low.

  Here, the drain-source voltage characteristic (Vds characteristic) of the transistor Tr35 of the common current source will be described with reference to FIG. In FIG. 9C, the horizontal axis represents the voltage Vds between the drain (D) and the source (S), and the vertical axis represents the drain current Id. Ideally, the drain current Id should be constant even when the drain-source voltage Vds increases. However, since the output impedance of the common current source constituted by the transistor Tr35 is not infinite, the drain-source As the inter-voltage Vds increases, the drain current Id also increases. For this reason, when there is a high-luminance subject, for example, the potential at the point B1 of the buffer BF ′ (n) in FIG. 8 greatly fluctuates, so that the drain current Id increases when the common current source is composed only of the transistor Tr35. Will do. On the other hand, the buffer BF ′ (n) of the solid-state imaging device 101b according to the present embodiment is configured by the cascode connection of the transistor Tr35 and the transistor Tr36 as shown in FIG. As described above, when the output impedance of the common current source is as high as r02 · gm2 · r01, and there is a high-luminance object, an increase in the drain current Id can be suppressed even if the drain-source voltage Vds increases.

  As described above, in the solid-state imaging device 101b according to this embodiment, the common current source of the buffer BF ′ (y) has a cascode configuration, and the drain-source voltage (Vds) increases by increasing the output impedance of the common current source. The increase in the drain current (Id) of the common current source due to can be suppressed to a negligible level, and a high-quality image free from lateral smear can be obtained even when there is a high-luminance subject in the captured image. Further, in the present embodiment, it is not necessary to separate the ground line as in the first embodiment, so that the degree of freedom in pattern design is increased, the chip size is reduced, and the cost can be reduced.

  In each of the above-described embodiments, in the first embodiment, when there is a high-luminance subject in the captured image, as a solving means that reduces the influence of the ground potential fluctuation of the buffer BF (y) that causes lateral smear, The solid-state imaging device 101 in which the ground line of the buffer BF (y) is separated will be described. In the second embodiment, as a solution for suppressing the fluctuation of the ground potential of the buffer BF ′ (y) that causes the same lateral smear. The solid-state imaging device 101b in which the common current source of the buffer BF ′ (y) is a cascode circuit has been described. However, a circuit configuration in which the first embodiment and the second embodiment are used together may be employed. That is, the buffer BF (y) of the circuit of the solid-state imaging device 101 in FIG. 1 may be a cascode circuit as in the case of the buffer BF ′ (y) in FIG.

  As described above, the solid-state image pickup device according to the present invention has been described by way of example in each embodiment, but can be implemented in various other forms without departing from the spirit or main features thereof. Therefore, the above-described embodiment is merely an example in all respects and should not be interpreted in a limited manner. The present invention is defined by the claims, and the present invention is not limited to the text of the specification. Further, all modifications and changes belonging to the equivalent scope of the claims are within the scope of the present invention.

DESCRIPTION OF SYMBOLS 101,101b ... Solid-state image sensor 102 ... Vertical scanning circuit 103 ... Horizontal output circuit 105 ... First ground line 106 ... VREF line 107 ... Second ground line 201 ... Ground lines P (1, 1) to P (M, N)... Pixels VLINE (1) to VLINE (N)... Vertical signal lines CAMP (1) to CAMP (N). (1) to BF (N), BF ′ (1) to BF ′ (N)... Buffer PW (1) to PW (N)... Constant current source PGND (1) to PGND (N).・ Pixel GND

Claims (2)

A pixel having a two-dimensionally arranged photoelectric conversion unit that converts light into an electrical signal;
A plurality of vertical signal lines connected in the column direction with the pixels arranged in the column direction and receiving electrical signals read from the pixels;
A column amplifier having a first constant current source for amplifying the electric signal read to the vertical signal line;
A buffer amplifier disposed in series with the column amplifier and having a second constant current source;
In a solid-state imaging device having a horizontal output circuit for horizontally outputting an electrical signal output by the buffer amplifier,
A first ground line arranged in a row direction and grounding a first constant current source of the column amplifier;
A second ground line arranged in the row direction and grounding the second constant current source of the buffer amplifier;
The first ground line and the second ground line are disposed independently, and the first ground line and the second ground line are grounded at both ends. Image sensor. A pixel having a two-dimensionally arranged photoelectric conversion unit that converts light into an electrical signal;
A plurality of vertical signal lines connected in the column direction with the pixels arranged in the column direction and receiving electrical signals read from the pixels;
A column amplifier having a first constant current source for amplifying the electric signal read to the vertical signal line;
A buffer amplifier disposed in series with the column amplifier and having a second constant current source;
In a solid-state imaging device having a horizontal output circuit for horizontally outputting an electrical signal output by the buffer amplifier,
A solid-state imaging device, wherein the second constant current source of the buffer amplifier has a cascode configuration.

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