JP2006311335A - Imaging apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an imaging apparatus provided with an output amplifying part capable of adjusting an output DC level without using a reference voltage. <P>SOLUTION: A capacitive element C1 connects a signal output line 6 to the gate of a transistor Tr1. The transistor Tr1 inputs the voltage signal of each unit cell of an imaging part 1 to the gate via the capacitive element C1 and outputs an amplification signal from its source. A transistor Tr2 with a bias voltage Vbias applied to its gate operates as a load. A transistor Tr3 inputs a signal outputted from the source of the transistor Tr1 to its gate and outputs an inversely amplified signal VOUT from its drain. A transistor Tr4 operates as a depression type load. A transistor Tr5 connects the gate of the transistor Tr1 and the source of the transistor Tr4 by the drain and the source, respectively and performs a switching operation in response to a reset signal RESET applied to the gate. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an imaging device in which a plurality of unit cells that receive light and perform photoelectric conversion are arranged on a semiconductor substrate.

  As is well known, imaging devices using imaging devices such as home video cameras, digital still cameras, and mobile phone cameras are rapidly spreading. Particularly in recent years, there has been an increasing market demand for higher pixel and higher performance imaging devices.

  As an image pickup apparatus used for these image pickup devices, there is an amplification type image sensor provided with an amplification element for each unit cell. This amplification type image sensor has excellent features such as low power consumption and low noise. In addition, this amplification type image sensor generally includes a separate amplification circuit in addition to each unit cell in order to further reduce noise.

  Patent Document 1 discloses an amplifier circuit used in an amplification MOS (Metal Oxide Semiconductor) image sensor. With this amplifier circuit, it is possible to reduce fixed pattern noise and the influence of external noise.

FIG. 1 is a schematic diagram showing a configuration of a general imaging apparatus common to the present invention and the related art. FIG. 6 is a diagram illustrating a circuit configuration example of the output amplifying unit 70 in FIG.
In the amplification type MOS image sensor, an amplification circuit using a capacitive feedback operational amplifier shown in FIG. By amplifying the signal output from the unit cell by the output amplifier 70, the influence of external noise can be reduced.

However, the output amplifying unit 70 needs to adjust the output DC level in order to adjust the current for reducing power consumption and optimize the linearity of the output signal with respect to the optical signal. In the amplifier circuit using the capacitive feedback operational amplifier shown in FIG. 6, the adjustment of the output DC level is realized by changing the reference voltage VREF.
Patent Document 1 also describes an output amplifying unit that does not use an operational amplifier, but the output amplifying unit that does not use an operational amplifier also adjusts the output DC level using the reference voltage VREF.
Japanese Patent Laid-Open No. 2004-312700

  However, when the output amplifying unit 70 using the reference voltage VREF described above is used for an amplification type image sensor, there is a problem that fluctuation of the reference voltage VREF becomes a noise source. That is, as shown in FIG. 7, the fluctuation amount of the reference voltage VREF is multiplied by a gain (amplification gain) by the output amplification unit 70 and appears as a noise component at the output terminal. For this reason, the noise component becomes an offset of the output signal VOUT, which causes a problem that the image quality deteriorates.

  Therefore, an object of the present invention is to provide an image pickup apparatus including an output amplifying unit capable of adjusting an output DC level without using a reference voltage.

The present invention is directed to an imaging apparatus including a unit cell that generates a voltage corresponding to an incident light amount. In order to achieve the above object, the imaging apparatus of the present invention includes an imaging unit, a load unit, a row selection / column selection unit, a signal processing unit, and an output amplification unit.
The imaging unit has a plurality of unit cells arranged in a matrix. The load unit applies a load to the unit cells of the imaging unit in units of columns in order to read the voltage generated in the unit cells. The row selection / column selection unit selects a desired unit cell. The signal processing unit outputs the voltage of each unit cell selected and read in units of rows by the load unit and the row selection / column selection unit to the horizontal signal line. The output amplification unit amplifies the voltage of each unit cell output from the signal processing unit to the horizontal signal line.

The output amplification unit includes a capacitive element, a source follower circuit, an inverting amplification circuit, and a switching element.
The capacitive element is connected to the horizontal signal line. The source follower circuit includes a first nMOS transistor for amplification that inputs the voltage of each unit cell output to the horizontal signal line through the capacitive element to the gate, a bias voltage is applied to the gate, and the drain is the first And a second nMOS transistor for load operation connected to the source of one nMOS transistor. The inverting amplifier circuit has a third source nMOS transistor for amplification that inputs the output from the source follower circuit to the gate, and a depletion type second transistor for load operation in which the source is connected to the drain of the third nMOS transistor. 4 nMOS transistors. The switching element is inserted between the output terminal of the inverting amplifier circuit and the input terminal of the source follower circuit, and applies an initial voltage to the input / output of the output amplifier by a predetermined switch operation.

  Preferably, the output amplifying unit may be provided with a second source follower circuit in the previous stage of the capacitive element. The second source follower circuit has a fifth nMOS transistor for amplification that inputs the voltage of each unit cell output to the horizontal signal line to the gate, a bias voltage is applied to the gate, and the drain is the fifth And a sixth nMOS transistor for load operation connected to the source of the nMOS transistor.

  According to the above invention, the potential at the input end and the potential at the output end can be reset to the reference potential using the potential resetting transistor. Further, the output DC level can be adjusted without using the reference voltage by changing the transistor size, threshold voltage, and bias voltage of each transistor constituting the output amplifier. As a result, it is possible to suppress noise caused by the reference voltage without reducing the gain of the output amplifier, and a good image can be obtained. In addition, by inserting a source follower circuit in front of the capacitive element to lower the output impedance, the circuit can be driven at high speed even if the capacity of the capacitive element is increased in order to prevent gain reduction caused by the capacitive element and the subsequent transistor. Is possible.

Hereinafter, an imaging apparatus of the present invention will be described with reference to the drawings.
FIG. 1 is a schematic diagram showing the configuration of the imaging apparatus of the present invention. In FIG. 1, the imaging apparatus of the present invention includes an imaging unit 1, a load unit 2, a row selection unit 3, a column selection unit 4, a signal processing unit 5, and an output amplification unit 7. The signal processing unit 5 and the output amplification unit 7 are connected by a signal output line 6.

The imaging unit 1 is an imaging region in which pixels that are unit cells are two-dimensionally arranged. In FIG. 1, nine pixels arranged in a 3 × 3 two-dimensional shape are illustrated, but the number of pixels of the imaging unit 1 actually used in the imaging device is approximately several hundred thousand to several millions. is there. The load unit 2 applies a load to the pixels of the imaging unit 1 in units of columns in order to read the signal (output voltage) of the imaging unit 1. The load unit 2 has a configuration in which one identical circuit is connected for each vertical column. The row selection unit 3 controls reset (initialization), reading (reading), and row selection in units of rows for the pixels of the imaging unit 1 using a predetermined control line. The column selection unit 4 controls column selection in units of columns for the pixels of the imaging unit 1 using a predetermined control line. The signal processing unit 5 processes the pixel signals in units of columns output from the imaging unit 1 and sequentially outputs them to the signal output line 6. The signal processing unit 5 has a configuration in which one identical circuit is connected for each vertical column. The output amplifier 7 amplifies and outputs each pixel signal transmitted from the signal output line 6.
The imaging apparatus according to the present invention is characterized by the circuit configuration of the output amplifying unit 7. Hereinafter, the output amplifying unit 7 having characteristics will be specifically described.

(First embodiment)
FIG. 2 is a diagram showing a circuit configuration of the output amplifying unit 7 according to the first embodiment of the present invention. In FIG. 2, the output amplifying unit 7 according to the first embodiment includes a capacitive element C1, a source follower circuit 9, an inverting amplifier circuit 8, and a fifth transistor Tr5 for potential reset. The source follower circuit 9 includes a first transistor Tr1 for amplification and a second transistor Tr2 for load operation. The inverting amplifier circuit 8 includes a third transistor Tr3 for amplification and a fourth transistor Tr4 for load operation. Typically, the first to fourth transistors Tr1 to Tr4 are nMOS transistors, and the fifth transistor Tr5 is a MOS transistor.

  The capacitive element C1 connects the signal output line 6 and the input end of the source follower circuit 9, that is, the gate of the first transistor Tr1. The first transistor Tr1 has a drain connected to the power supply VDD, inputs a voltage signal of each unit cell of the imaging unit 1 to the gate via the capacitive element C1, and outputs an amplified signal from the source. The second transistor Tr2 has a drain connected to the source of the first transistor Tr1 and a source connected to the GND, and operates as a load when a bias voltage Vbias is applied to the gate.

  The third transistor Tr3 has a source connected to GND, a signal output from the source of the first transistor Tr1 is input to the gate, and an inverted and amplified signal VOUT is output from the drain. The fourth transistor Tr4 has a drain and a gate connected to the power supply VDD, and a source connected to the drain of the third transistor Tr3, and operates as a depletion type load. The fifth transistor Tr5 connects the input terminal of the source follower circuit 9 and the output terminal of the inverting amplifier circuit 8, that is, the source of the fourth transistor Tr4, with a drain and a source, respectively. Then, the fifth transistor Tr5 performs a switching operation in accordance with the reset signal RESET applied to the gate, and matches the potentials of the input terminal of the source follower circuit 9 and the output terminal of the inverting amplifier circuit 8.

  FIG. 3 is a diagram illustrating a timing example of signals processed by the output amplifying unit 7 according to the first embodiment. In FIG. 3, a period T <b> 1 is a reset period (field-through period) in which a high signal is supplied to the reset signal RESET, and is a period in which a reference potential is applied to the output amplifier 7. The period T2 is a signal readout period in which a Low signal is supplied to the reset signal RESET, and is a period in which the output amplifier 7 amplifies and outputs a signal appearing on the signal output line 6.

  In the period T1, the fifth transistor Tr5 is turned on, and the inverting amplifier circuit 8 becomes an equivalent circuit shown in FIG. Therefore, the DC level of the output signal VOUT in this ON state, that is, the reference potential is determined by the ratio of the resistor R1 and the resistor R2. The resistor R1 is determined by the size (width W × length L) of the fourth transistor Tr4 and the threshold value, and the resistor R2 is determined by the size (width W × length L) of the third transistor Tr3, the threshold value, and the gate voltage. Determined by The gate voltage can be adjusted by the input / output potential difference of the source follower circuit 9. Note that the input / output potential difference is a difference between the gate potential and the source potential of the first transistor Tr1.

  In the period T2, the fifth transistor Tr5 is turned off. In the OFF state, a signal V1 obtained by multiplying the signal V0 transmitted to the signal output line 6 by an amplifier gain (voltage gain) is output as the output signal VOUT. In order to reliably detect the change amount of the signal V0 for each column sequentially selected by the column selection unit 4 and transmitted to the signal output line 6, the reset of the signal output line 6 and the output amplifier circuit 7 It is necessary to synchronize with the reset.

  As described above, according to the output amplifying unit of the first embodiment of the present invention, the potential at the input end and the potential at the output end can be reset to the reference potential by using the potential reset transistor. Further, the output DC level can be adjusted without using the reference voltage by changing the transistor size, threshold voltage, and bias voltage of each transistor constituting the output amplifier. As a result, it is possible to suppress noise caused by the reference voltage without reducing the gain of the output amplifier, and a good image can be obtained.

(Second Embodiment)
FIG. 5 is a diagram showing a circuit configuration of the output amplifying unit 7 according to the second embodiment of the present invention. In FIG. 5, the output amplifying unit 7 according to the second embodiment includes a capacitive element C1, a first source follower circuit 9, an inverting amplifier 8, a fifth transistor Tr5 for potential reset, 2 source follower circuits 10. The first source follower circuit 9 includes a first transistor Tr1 for amplification and a second transistor Tr2 for load operation. The second source follower circuit 10 includes a sixth transistor Tr6 for amplification and a seventh transistor Tr7 for load operation. The inverting amplifier circuit 8 includes a third transistor Tr3 for amplification and a fourth transistor Tr4 for load operation. Typically, the first to fourth and sixth to seventh transistors Tr1 to Tr4 and Tr6 to Tr7 are nMOS transistors, and the fifth transistor Tr5 is a MOS transistor.

  As shown in FIG. 5, the circuit configuration of the output amplifying unit 7 according to the second embodiment is the second stage before the capacitive element C1 with respect to the circuit configuration of the output amplifying unit 7 according to the first embodiment. The source follower circuit 10 is further added.

  The sixth transistor Tr6 has a drain connected to the power supply VDD, inputs a voltage signal of each unit cell of the imaging unit 1 that transmits the signal output line 6 to the gate, and outputs an amplified signal from the source. The seventh transistor Tr7 operates as a load when the drain is connected to the source of the sixth transistor Tr6 and the source is connected to GND, and the bias voltage Vbias is applied to the gate. A signal output from the source of the sixth transistor Tr6 is input to the gate of the first transistor Tr1 through the capacitive element C1.

  As described above, according to the output amplifying unit according to the second embodiment of the present invention, by inserting the source follower circuit in the previous stage of the capacitive element, in addition to the above-described effect of reducing noise, It is possible to suppress the gain reduction that occurs in the signal processing unit.

  The image pickup apparatus of the present invention can be used for image pickup devices such as home video cameras, digital still cameras, and mobile phone cameras that require high image quality, and is particularly good at suppressing noise caused by the reference voltage. It is suitable when you want to get a clear image.

Schematic showing the configuration of a general imaging device common to the present invention and the prior art The figure which shows the circuit structure of the output amplification part 7 which concerns on the 1st Embodiment of this invention. The figure which shows the example of a timing of the signal processed in the output amplification part 7 which concerns on 1st Embodiment The figure which shows the circuit structure of the output amplification part 7 which concerns on the 2nd Embodiment of this invention. The figure which shows the equivalent circuit of the inverting type amplifier circuit 8 in a reset period The figure which shows the circuit structure of the conventional output amplification part 70. The figure explaining the subject in the conventional output amplification part 70

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Image pick-up part 2 Load part 3 Row selection part 4 Column selection part 5 Signal processing part 6 Signal output line 7, 70 Output amplification part 8 Inversion amplification circuit 9, 10 Source follower circuit 19 Operational amplifier C1, C21, C23 Capacitance element R1, R2 Resistors Tr1-Tr7, Tr22 Transistors

Claims (2)

An imaging apparatus including a unit cell that generates a voltage according to the amount of incident light,
An imaging unit in which a plurality of the unit cells are arranged in a matrix;
In order to read the voltage generated in the unit cell, a load unit that applies a load to the unit cell of the imaging unit in a column unit,
A row selection / column selection unit for selecting a desired unit cell;
A signal processing unit that outputs the voltage of each unit cell selected and read in units of rows by the load unit and the row selection / column selection unit to a signal output line;
An output amplifying unit for amplifying the voltage of each unit cell output from the signal processing unit to the signal output line;
The output amplifier is
A capacitive element connected to the signal output line;
A first nMOS transistor for amplification that inputs the voltage of each unit cell output to the signal output line via the capacitive element to the gate, a bias voltage is applied to the gate, and the drain is the first nMOS A source follower circuit comprising: a second nMOS transistor for load operation connected to the source of the transistor;
A third source nMOS transistor for amplification that inputs the output from the source follower circuit to the gate, a fourth nMOS transistor for depletion operation for load operation, the source of which is connected to the drain of the third nMOS transistor; And an inverting amplifier circuit, and inserted between the output terminal of the inverting amplifier circuit and the input terminal of the source follower circuit, and applies an initial voltage to the input / output of the output amplifier unit by a predetermined switch operation. An imaging device comprising a switching element. A fifth nMOS transistor for amplification that inputs the voltage of each unit cell output to the horizontal signal line to the gate, a bias voltage is applied to the gate, and a drain is the fifth nMOS in the stage preceding the capacitive element The imaging apparatus according to claim 1, further comprising a second source follower circuit including a sixth nMOS transistor for load operation connected to a source of the transistor.

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