JP4957925B2 - Amplification type solid-state imaging device - Google Patents

Description

  The present invention relates to an amplification type solid-state imaging device having a memory in a pixel.

In general, an amplification type solid-state imaging device has a pixel unit having an amplification function and a scanning circuit arranged around the pixel unit, and reads out pixel data from the pixel unit by the scanning circuit. is doing.
As an example of such an amplification-type solid-state imaging device, an APS (Active Pixel) configured by a CMOS (Complementary Metal Oxide Semiconductor), which is advantageous for integrating a pixel portion with a peripheral driving circuit and a signal processing circuit. Sensor) type image sensors are known. Among such APS type image sensors, a 4-transistor type capable of obtaining high image quality is becoming mainstream in recent years.

FIG. 16 is a circuit diagram showing an example of a conventional four-transistor pixel configuration in which four NMOS transistors are provided in the pixel 100.
In FIG. 16, the light receiving element PD is normally formed of a buried photodiode, and signal charges are transferred from the light receiving element PD to the connection portion FD by the transfer transistor TX. The connection unit FD is reset to the power supply voltage Vdd that is the drain voltage of the reset transistor RT by the reset transistor RT before the signal charge is transferred from the light receiving element PD. Next, the transfer transistor TX is turned on, and the signal charge from the light receiving element PD is transferred to the connection portion FD. The voltage of the connection portion FD after the reset and the signal charge transfer is amplified by the amplification transistor SF and read out to the read signal line Vsig through the selection transistor SL. A constant current load transistor CL is connected to one end of the read signal line Vsig, and an output voltage Vo is obtained from the drain of the constant current load transistor CL.

FIG. 17 is a diagram illustrating a configuration example of a two-dimensional image sensor constituting an amplification type solid-state imaging device including a pixel array 200 in which the pixels 100 of FIG. 16 are arranged in a matrix.
In FIG. 17, reference numeral 11 denotes a power supply line for applying a power supply voltage Vdd to each drain of the reset transistor RT and the amplification transistor SF. The power supply line 11 is directly connected to the power supply line 13 of the entire amplification type solid-state imaging device. Yes. The drive line 16 is a transfer transistor drive line, a reset transistor drive line, and a select transistor drive line.
In each pixel row, a specific row is selected by the row decoder circuit 14, and a drive signal is given to the drive line 16 through the row drive circuit 15. A signal from the read signal line Vsig is input to the column signal processing circuit 17, and analog or analog and digital signal processing is performed by the column signal processing circuit 17. Thereafter, the column decoder circuit 18 reads out the signal for each column to the horizontal signal line 19 and finally outputs it to the outside of the amplification type solid-state imaging device.

  In the configuration shown in FIG. 17, each pixel is sequentially read out row by row, and the pixel 100 outputs the signal accumulated in the light receiving element PD until the readout is performed. In order to capture a moving subject, the image is distorted in accordance with the movement. In order to solve such a problem, there has been a collective exposure technique in which a pixel is provided with a memory, all the pixels are read out simultaneously and written into the memory, and then the information in the memory is sequentially read out. However, in this case, there is a problem that noise increases between the time when the signal from the light receiving element is written to the memory and the time when the signal is read, and the S / N ratio is lowered. For this reason, there is a technique for amplifying the signal of the light receiving element and then writing it into the memory, and FIG. 18 is a circuit diagram showing an example of this (see, for example, Patent Document 1).

A pixel 110 illustrated in FIG. 18 has a configuration in which a first amplification transistor SF1, a constant current load VB, a current control switch SW, a write switch Wr, and a memory Cm are added to the pixel 100 illustrated in FIG. In FIG. 18, the second amplification transistor SF2 corresponds to the amplification transistor SF of FIG. 16, and the current control switch SW may be provided on the power supply side.
For example, the pixel 110 is used to form the two-dimensional image sensor shown in FIG. 17, and all the pixels are first operated to write the signal from the light receiving element PD into the memory Cm. That is, after the current control switch SW is turned on, the write switch Wr is turned on, and the signal from the light receiving element PD amplified by the first amplification transistor SF1 is written in the memory Cm.

  Thereafter, the write switch Wr is turned off, and then the current control switch SW is turned off to complete the batch write operation. The read operation is sequentially performed for each row. That is, the operation of reading the signal held in the memory Cm to the read signal line Vsig through the second amplification transistor SF2 and the selection transistor SL is sequentially performed for each row. A constant current load transistor CL is connected to one end of the read signal line Vsig, and the output voltage Vo is sequentially obtained for each row.

JP 2005-65074 A

However, the configuration shown in FIG. 18 has the following problems (a) to (d).
(A) Since the first amplification transistor SF1 is simultaneously turned on in all the pixels, an excessive current flows in the entire two-dimensional image sensor element. For example, if 1 μA per pixel is 1 million pixels, the entire device is 1 A.
(B) When the gate voltage of the constant current load VB is set near the threshold value Vth in order to suppress the current per pixel, the current value greatly varies from pixel to pixel due to variations in the threshold value Vth.
(C) Two transistors, the constant current load VB and the current control switch SW, and a control signal line to each of the transistors are required in one pixel, and the pixel layout becomes complicated.

前記（１）式では、ｋはボルツマン定数、Ｔは絶対温度、ｇｍ１及びｇｍ２は第１の増幅トランジスタＳＦ１及び定電流負荷ＶＢの相互コンダクタンスをそれぞれ示している。画素領域内では、面積の制約から相互コンダクタンスｇ_ｍ１及びｇ_ｍ２は同程度の値になるため、ノイズ電力は１トランジスタの場合と比較して２倍程度になる。 (D) Noise generated in the source follower circuit constituted by the first amplification transistor SF1 and the constant current load VB is expressed by the following equation (1).

In the equation (1), k is a Boltzmann constant, T is an absolute temperature, and gm1 and gm2 are transconductances of the first amplification transistor SF1 and the constant current load VB, respectively. In the pixel region, the mutual conductances g _m1 and g _m2 have _{substantially} the same value due to area restrictions, so that the noise power is about twice that in the case of one transistor.

  As a technique for stably reducing the current per pixel, a circuit as shown in FIG. 19 can be considered. That is, in FIG. 19, even when the high resistance RL is inserted on the source side of the constant current load VB and the gate voltage is made a subthreshold region having a threshold voltage Vth or less due to the back gate effect of the MOS transistor, the current is greatly suppressed. The source voltage can be kept stable. However, for example, in order to reduce the current of the entire element to 100 mA or less in 1 million pixels, it is necessary to set the source voltage of the constant current load VB to 1 V and RL = 10 MΩ. It was difficult to form in a pixel.

Further, when a normal source follower output as shown in FIGS. 18 and 19 is written into a memory having a capacitance value Cm, kTC noise as shown in the following equation (2) is generated in terms of noise power. The kTC noise is added to the source follower noise, leading to an increase in noise.

  The present invention has been made to solve such a problem. With a simple circuit configuration, the current at the time of writing to the memory can be suppressed, and stable operation and high performance can be obtained. An object is to obtain an amplification type solid-state imaging device.

An amplification type solid-state imaging device according to the present invention includes a pixel array in which a plurality of unit pixels each having a memory are arranged in a matrix, and a control circuit unit that performs operation control on each pixel constituting the pixel array. In the amplification type solid-state imaging device,
Each pixel is
A photoelectric conversion unit that generates and outputs a signal corresponding to the received light; and
A first amplification transistor composed of a MOS transistor for inputting a signal output from the photoelectric conversion unit to a gate and amplifying and outputting the signal input to the gate;
A first capacitor forming the memory for storing a signal output from the first amplification transistor;
A first write switch unit that performs output control to the first capacitor to control writing to the first capacitor with respect to a signal output from the first amplification transistor;
A second amplifying transistor comprising a MOS transistor for inputting a signal written in the first capacitor to a gate and amplifying and outputting the signal input to the gate;
An initialization transistor for initializing a signal written in the first capacitor to a predetermined first voltage;
Each with
The first amplifying transistor has only the first capacitor as a load, and the first write switch unit has a predetermined period after the initialization with respect to the first capacitor is performed by the initialization transistor. The signal output from the first amplifying transistor is output to the first capacitor and written to the first capacitor.

  Specifically, the first write switch unit is output from the first amplification transistor during a period in which the first amplification transistor shifts from the saturation region operation to the subthreshold region operation and becomes a metastable state. A signal is output to the first capacitor to perform writing to the first capacitor.

  In addition, the control circuit unit operates each of the pixels constituting the pixel array at the same time to perform a writing operation on the first capacitor in each of the pixels, and then performs a predetermined method on the pixels. Reading from the first capacitor of each pixel was sequentially performed.

  In this case, in each pixel in the pixel array, the first amplification transistor is connected to a power supply line in a column unit, and the power supply line is connected to a predetermined power supply voltage through a resistor for each column unit. I made it.

  In each pixel in the pixel array, the first amplification transistor is connected to a power supply line in units of columns, the power supply lines in all columns are connected to each other, and the connection portion is connected to a power supply voltage via a resistor. You may make it connect.

  Further, when the control circuit section sequentially reads out the row from the pixel array, the second amplification transistor is inactivated with respect to the initialization transistor in each pixel of the non-selected row. The first voltage is initialized.

Further, each pixel is
One or more second capacitors forming the memory for storing a signal output from the first amplification transistor;
One or more second write switch units for performing output control to the corresponding second capacitor and controlling writing to the second capacitor with respect to the signal output from the first amplification transistor When,
A first read switch unit for controlling output to the gate of the second amplification transistor with respect to a signal written to the first capacitor;
One or more second read switch units for controlling output to the gate of the second amplification transistor with respect to a signal written in the corresponding second capacitor;
With
The first amplification transistor uses only the first or second capacitor as a load, and the initialization transistor initializes a signal written in the second capacitor to the predetermined first voltage, and The second write switch unit outputs a signal output from the first amplification transistor to the second capacitor for a predetermined period after the initialization of the second capacitor is performed by the initialization transistor. Then, writing to the second capacitor may be performed.

  In this case, the second write switch unit outputs the signal output from the first amplification transistor during a period when the first amplification transistor shifts from the saturation region operation to the subthreshold region operation and becomes a metastable state. An output is made to the second capacitor and writing to the second capacitor is performed.

  Each of the pixels includes a reset transistor that resets a gate of the first amplification transistor to a predetermined second voltage, and each of the first and second write switch units includes the first and second write switches. For each capacitor, the output signal from the first amplification transistor when the gate is reset is written into one capacitor, and the output signal from the photoelectric conversion unit is input to the gate. The output signal from one amplification transistor is written to the other capacitor.

  Each of the pixels may include a control switch unit that outputs a predetermined voltage to the output terminal of the first amplification transistor during the reset operation.

  Specifically, the first amplification transistor is an enhancement type MOS transistor.

  The second amplification transistor may be a depletion type MOS transistor.

  The first capacitor may include a MOS capacitor at least in part.

  In this case, the MOS type capacitor is a depletion type MOS type capacitor.

  According to the amplification type solid-state imaging device of the present invention, since there is no constant current load in the pixel, the current at the time of writing can be suppressed. In order to perform a write operation to the first capacitor serving as a load of the first amplification transistor, first, the first capacitor is initialized to a predetermined voltage, for example, a low voltage such as a ground voltage, and then A stable operation can be performed by performing the write operation by the charging current to the first capacitor and controlling the write time by the first write switch section.

  Further, the first write switch unit is configured to output a signal output from the first amplification transistor during a period in which the first amplification transistor is in a metastable state from the saturation region operation to the subthreshold region operation. Is output to the first capacitor to perform writing to the first capacitor. For this reason, the write operation is completed when the first amplification transistor shifts to the subthreshold region and the time change of the voltage in the first capacitor becomes extremely small. It can be carried out.

  The unit pixel includes one or more sets of the second capacitor and the second write switch unit, and the first and second capacitors correspond to the first and second capacitors. For example, a gate is provided for each of the first and second capacitors so as to include each readout switch section, and further, in the unit pixel, a reset transistor that resets a gate of the first amplification transistor. The output signal from the first amplification transistor when the signal is reset is written to one capacitor, and the output from the first amplification transistor when the output signal from the photoelectric conversion unit is input to the gate The signal was written to the other capacitor. Accordingly, since a plurality of information can be stored per pixel, for example, the reset level of the gate in the first amplification transistor and the signal level from the photoelectric conversion unit can be independently held. . Therefore, if these are read out separately to the signal line by the second amplification transistor, the correlated double sampling (CDS) method can be applied by taking the voltage difference between the two levels in the subsequent circuit. The fixed pattern noise caused by the variation of the threshold value Vth in each of the first and second amplification transistors and the reset noise to the gate of the first amplification transistor can be suppressed, and a low noise image signal can be suppressed. Can be obtained.

  In addition, after the pixels constituting the pixel array are simultaneously operated to perform the writing operation to the first capacitor in the pixels, the first of each pixel is performed by a predetermined method. For example, the first amplifying transistor is connected to the power supply line in column units, and the power supply line is connected to the power supply voltage through the resistors for each column unit. In addition, it is possible to perform an operation of simultaneously writing all the pixels to the respective capacitors at the same time and an operation of sequentially reading from the respective capacitors. For example, if resistors are connected in series to the power supply lines of each column, the peak value of the transient current that charges the capacitor can be suppressed even when information of all the pixels is written in a lump.

  Further, the gate voltage of the second amplifying transistor is controlled by the initialization transistor so that the second amplifying transistor in the non-selected row becomes inactive when signals are read out from the pixel array in row order. As a result, there is no need to provide a selection transistor between the second amplification transistor and the signal line, the number of components in the pixel can be reduced, and performance improvement such as an increase in the area of the light receiving portion. Can be achieved.

  Further, by using an enhancement type for the first amplifying transistor, or by making the drain voltage of the reset transistor smaller than the power supply voltage, the output level of the first amplifying transistor becomes higher than the power supply voltage. The response time until the first amplifying transistor shifts from the saturation region operation to the subthreshold region operation can be shortened, and the response speed of the entire write operation can be increased.

  Further, by using a depletion type for the second amplification transistor, even if the first amplification transistor is made to be an enhancement type and the input voltage of the second amplification transistor is reduced, the second amplification transistor A sufficient operating margin can be secured.

  In addition, since the MOS capacitor is included in at least a part of the first capacitor, it is easy to secure a sufficient memory capacity value within a limited pixel area, and the capacitor is made a depletion type. As a result, the operating voltage range in which the capacitance value can be secured can be expanded to the low voltage side.

It is the figure which showed the pixel structural example of the amplification type solid-state imaging device in the 1st Embodiment of this invention. It is the figure which showed the structural example of the two-dimensional image sensor containing the pixel array 20 which has arrange | positioned the pixel 10 of FIG. 1 in the matrix form. It is the figure which showed the other structural example of the two-dimensional image sensor containing the pixel array 20 which has arrange | positioned the pixel 10 of FIG. 1 in the matrix form. It is the figure which showed a part of circuit structure which extracted the pixel arrangement | sequence for 1 row in the amplification type solid-state imaging device shown in FIGS. FIG. 5 is a diagram illustrating an operation example of the circuit configuration of FIG. 4 with potential. FIG. 5 is a diagram showing an operation example of the circuit configuration of FIG. 4 by potential change and current change. FIG. 5 is a diagram showing an operation example of the circuit configuration of FIG. 4 by circuit simulation. FIG. 2 is a diagram illustrating an example of an operation range in the pixel configuration of FIG. 1. It is the figure which showed the other pixel structural example of the amplification type solid-state imaging device in the 1st Embodiment of this invention. It is the figure which showed the amplification type solid-state imaging device of the 2nd Embodiment of this invention by the pixel structural example. 11 is a timing chart illustrating an operation example of the pixel 50 illustrated in FIG. 10. It is the figure which showed the example of another pixel structure of the amplification type solid-state imaging device of the 2nd Embodiment of this invention. 13 is a timing chart illustrating an operation example in the pixel 50 of FIG. 12. It is the figure which showed the pixel structural example of the amplification type solid-state imaging device in the 3rd Embodiment of this invention. 15 is a timing chart illustrating an operation example of the pixel 60 illustrated in FIG. 14. It is the figure which showed the pixel structural example of the conventional amplification type solid-state imaging device. It is the figure which showed the structural example of the two-dimensional image sensor containing the pixel array which has arrange | positioned the pixel 100 of FIG. 16 in the matrix form. It is the figure which showed the other pixel structural example of the conventional amplification type solid-state imaging device. It is the figure which showed the other pixel structural example of the conventional amplification type solid-state imaging device.

Next, the present invention will be described in detail based on the embodiments shown in the drawings.
First embodiment.
FIG. 1 is a diagram illustrating an example of a pixel configuration of an amplification type solid-state imaging device according to the first embodiment of the present invention.
In FIG. 1, a pixel 10 includes a light receiving element PD constituted by an embedded photodiode, a transfer transistor TX, a reset transistor RT, a first amplification transistor SF1, a selection transistor SL, a second amplification transistor SF2, a write switch Wr, a capacitor. And an initialization transistor IT that initializes a terminal voltage of the memory Cm. The transfer transistor TX, the reset transistor RT, the first amplification transistor SF1, the selection transistor SL, the second amplification transistor SF2, the write switch Wr, and the initialization transistor IT are each composed of an NMOS transistor. The light receiving element PD serves as a photoelectric conversion unit, the write switch Wr serves as a first write switch unit, and the memory Cm serves as a first capacitor.

  The anode of the light receiving element PD is connected to the ground voltage, and the transfer transistor TX is connected between the cathode of the light receiving element PD and the gate of the first amplification transistor SF1. When the connection portion between the transfer transistor TX and the gate of the first amplification transistor SF1 is FD, the reset transistor RT is connected between the power supply voltage Vdd and the connection portion FD. The drain of the first amplification transistor SF1 is connected to the power supply voltage Vdd via the resistor R, the source of the first amplification transistor SF1 is connected to one end of the memory Cm via the write switch Wr, and the other end of the memory Cm. Is connected to ground voltage.

  A connection portion between the write switch Wr and the memory Cm is connected to a gate of the second amplification transistor SF2, and an initialization transistor IT is connected between the connection portion and a predetermined voltage V1. The drain of the second amplification transistor SF2 is connected to the power supply voltage Vdd, and the selection transistor SL is connected between the source of the second amplification transistor SF2 and the read signal line Vsig. A constant current load transistor CL is connected between one end of the read signal line Vsig and the ground voltage, and an output voltage Vo is output from a connection portion between the constant current load transistor CL and the read signal line Vsig.

  Thus, the power supply of the first amplification transistor SF1 is separated from the power supplies of the second amplification transistor SF1 and the reset transistor, and the drain of the first amplification transistor SF1 is connected to the power supply line 12 in units of columns. The power supply line 12 is connected via a resistor R to a power supply voltage Vdd that forms the power supply of the entire amplification type solid-state imaging device. The initialization transistor IT resets the initial value of the terminal voltage of the memory Cm to a low voltage, for example, a predetermined voltage V1, which is a ground voltage, before the write operation, and turns on the write switch Wr at the start of the write operation. When the charging current flows, the source follower operation can be performed without the constant current load of the first amplification transistor SF1.

FIG. 2 is a diagram illustrating a configuration example of a two-dimensional image sensor constituting an amplification type solid-state imaging device including a pixel array 20 in which the pixels 10 of FIG. 1 are arranged in a matrix.
In FIG. 2, a power supply line 11 is a power supply line for applying a power supply voltage Vdd to each drain of the reset transistor RT and the second amplification transistor SF2, and the power supply line 11 is a power supply line for the entire amplification type solid-state imaging device. 13 is directly connected. Each power line 12 is connected to the power line 13 via a resistor Rcol, and is connected to the drain of each first amplification transistor SF1. The drive line 16 shows a drive line for the transfer transistor TX, a drive line for the reset transistor RT, a drive line for the write switch Wr, a drive line for the initialization transistor IT, and a drive line for the selection transistor SL. The drive lines are respectively connected to the gates of the corresponding transistors.

In each pixel row, a specific row is selected by the row decoder circuit 14, and a drive signal is given to the drive line 16 through the row drive circuit 15. A signal from the read signal line Vsig is input to the column signal processing circuit 17, and analog or analog and digital signal processing is performed by the column signal processing circuit 17. Thereafter, the column decoder circuit 18 reads out the signal for each column to the horizontal signal line 19 and finally outputs it to the outside of the amplification type solid-state imaging device. The row decoder 14, the row drive circuit 15, the column signal processing circuit 17, and the column decoder circuit 18 constitute a control circuit unit, and a control signal input to the row decoder 14 and a circuit that generates the control signal are omitted. Yes.
The power source of the first amplifying transistor SF1 is separated from the power source of the reset transistor RT and the second amplifying transistor SF2, and is connected to the power source line 13 of the entire amplifying solid-state imaging device through a resistor Rcol in units of columns. The resistor Rcol corresponds to the resistor R in FIG. Note that the resistors may be connected in common to all columns, not in units of columns, and then connected to the power supply voltage Vdd of the entire amplification type solid-state imaging device via the resistor Rfrm. In this case, FIG. Is as shown in FIG.

  In such a configuration, writing to the memory Cm is performed simultaneously for all the pixels at once. First, the signal charge is transferred from the light receiving element PD to the connection portion FD by the transfer transistor TX. The connection unit FD is reset to the power supply voltage Vdd that is the drain voltage of the reset transistor RT by the reset transistor RT before the signal charge is transferred from the light receiving element PD. Next, the transfer transistor TX is turned on, and the signal charge from the light receiving element PD is transferred to the connection portion FD. The voltage of the connection portion FD after the reset and after the signal charge transfer is amplified by the first amplification transistor SF1. When the signal from the light receiving element PD is written to the memory Cm, the write switch Wr is turned on, and the signal from the light receiving element PD amplified by the first amplification transistor SF1 is written to the memory Cm. Thereafter, the write switch Wr is turned off to complete the write operation.

  The read operation is sequentially performed for each row. That is, the operation of reading the signal held in the memory Cm to the read signal line Vsig through the second amplification transistor SF2 and the selection transistor SL is sequentially performed for each row. A constant current load transistor CL is connected to one end of the read signal line Vsig, and an output voltage Vo is sequentially obtained for each row from the drain of the constant current load transistor CL.

FIG. 4 is a diagram showing a part of a circuit configuration in which a pixel array for one column in the amplification type solid-state imaging device shown in FIGS. 1 to 3 is extracted.
As shown in FIG. 4, a power supply line 12 is connected to a power supply voltage Vdd of the entire amplification type solid-state imaging device via a resistor R, and a first amplification transistor is provided for each pixel between the power supply line 12 and the ground voltage. SF1 and memory Cm are connected in series.
Here, the channel potential of the first amplification transistor SF1 in each pixel is represented by Φj, and in order to explain the operation of FIG. 4, an example of the relationship of the potential of the first amplification transistor SF1 in one pixel is shown in FIG. Show.

In FIG. 5, in the first amplifying transistor SF1, the channel potential of the gate is Φj, the drain voltage is the power supply voltage Vdd, and the source has an initial value when the time t = 0 is reset by the initialization transistor IT. The ground voltage is GND. At t> 0, first, the gate of the first amplifying transistor SF1 is in the mode 1 in which the operation is in the saturation region, and the source voltage Vs, j rises rapidly from the initial ground voltage GND to Φj. When the source voltage Vs, j exceeds Φj, the gate of the first amplifying transistor SF1 is in mode 2 which is a subthreshold region operation, and becomes a logarithmic change with time due to the heat release phenomenon, which is very slow. Voltage changes. In the saturation region operation of the mode 1, the current output from the first amplification transistor SF1 becomes the charging current of the memory Cm, and the charging current is determined by the resistance value Ra and the load capacitance value Ca in the target current path. Decay exponentially with a determined time constant τ _CR = Ca × Ra. The voltage change of the source voltage Vs, j in such a mode 1 is shown in the following formula (3). The charging current peaks at the starting point and its value becomes Vdd / Ra.

なお、ｑは電子電荷を、ｉｏはモード２の開始点における前記充電電流をそれぞれ示している。 In the circuit of FIG. 4, Ra = Rcol, Ca = n × Cm when the resistor R is provided for each column, and Ra = Rfrm, when the resistor R is at one place in the entire amplifying solid-state imaging device. Ca = n × m × Cm. Note that n represents the number of pixels connected to the signal line 12, and m represents the number of columns. The voltage change of the source voltage Vs, j of the first amplification transistor SF1 in mode 2 is expressed by a logarithmic change as shown in the following equation (4).

Here, q represents an electronic charge, and io represents the charging current at the start point of mode 2.

These relationships are schematically shown in FIG.
Before the time to, the mode becomes the mode 1 and becomes an exponential function response determined by the RC time constant, and after the time to becomes the mode 2 and the logarithmic function response determined by the heat release. At time to, the source voltage Vs, j of the first amplifying transistor SF1 substantially matches the channel potential Φj. For these reasons, if sampling is performed at a time ts when a sufficient time has passed since the transition to the mode 2, the output level of the memory Cm can be read almost stably. The peak value of the current flowing through the memory Cm can be suppressed by appropriately selecting the resistance value of the resistor R.

Here, the difference between the cases of FIG. 2 and FIG. 3 will be described.
In order to make the time constant τ _CR = Ca × Ra in the entire amplification type solid-state imaging device the same, the relationship of Rcol = m × Rfrm is established, and the resistance Rcol has a larger resistance value than the resistance Rfrm. As shown in FIG. 6, when the source voltage Vs, j of the first amplifying transistor SF1 exceeds Φj in each pixel, the current i1W from the first amplifying transistor SF1 rapidly decreases (that is, the first amplifying transistor SF1). The resistance value of the transistor SF1 becomes very large), and this state is called a semi-off state. Since a large number of pixels are connected to each column, the change point of the source voltage Vs, j, that is, the voltage when the source voltage Vs, j of the first amplification transistor SF1 exceeds the channel potential when viewed in column units. Becomes a different value depending on the value of the channel potential. If the majority of the columns are in the semi-off state and only a small number of columns are in the on state, the resistance value of the first amplification transistor SF1 remains small only in the small number of columns, and the signal line 12 is The memory is directly connected to the memory Cm having the capacity of the small number of columns.

  In the case shown in FIG. 3, the resistance value of the resistor Rfrm connected in series is small, and a large current flows through the small number of columns as described above. On the other hand, in the case shown in FIG. 2, since a resistor Rcol having a relatively large resistance value is connected to the power source for each column, a large current flows through the small number of columns as described above. It can be avoided. However, in most pixels connected to a specific column, the first amplification transistor SF1 is turned on, and in most pixels connected to other columns, the first amplification transistor SF1 is in a semi-off state. This is extremely rare in a general image sensor composed of a large number of pixels. Therefore, even if the configuration shown in FIG. 3 is simplified, there is usually no problem.

FIG. 7 shows an example of a result calculated using the equations (3) and (4). FIG. 7 shows an example in which the number of pixels is 1280 × 1024 = 1.3 million, the power supply voltage is 3.3 V, the capacity of the memory Cm is 40 fF, and the resistance is Rcol = 40 kΩ for each column. The result in the range of 1-2V is shown.
As is apparent from FIG. 7, when the sampling time is set to 5 μs or more, the capacitance voltage Vs, j (t), which is a substantially stable voltage of the memory Cm, can be obtained. In addition, the peak current of the entire amplification type solid-state imaging device at this time is 105 mA, which is a sufficiently small value compared to a value of 1280 mA when the pixel has a constant current load of, for example, 1 μA as in the past. .

  A further advantage of the present invention is that it is advantageous for reducing noise. The noise generated on the source follower load side, which is unavoidable in the conventional pixel configuration, as shown in the equation (1), is essentially avoided in the present invention. Furthermore, the present invention has the following noise reduction factors. Normally, when a signal is written to the memory Cm in the pixel, noise as expressed by the equation (2) is generated, which is called kTC noise and cannot be avoided.

However, in the present invention, as shown in FIG. 5, in the final stage of writing, the mode 2 is the subthreshold region operation. In this case, the noise is known to be expressed by the following equation (5). ing. This is called a soft reset mode, and the noise power is ½ of normal operation.

  In FIG. 1, the maximum value of the output level in the first amplification transistor SF1 desirably has a margin with respect to the power supply voltage Vdd, as indicated by V (UL) in FIG. Here, the value of V (UL) depends on the threshold value of the first amplification transistor SF1 and the voltage of the connection portion FD, and the voltage of the connection portion FD depends on the drain voltage Vrd of the reset transistor RT. As illustrated in FIG. 1, when Vrd = Vdd, it is easy to secure the margin by making the threshold value of the first amplification transistor SF1 an enhancement type. Alternatively, although not shown, when Vrd <Vdd, it is easy to ensure the margin even if the threshold value of the first amplification transistor SF1 is a depletion type. In this way, the period of mode 1 in FIG. 6 can be shortened, and the response of the entire write operation can be accelerated.

  In FIG. 1, when the output level of the first amplifying transistor SF1, and hence the maximum value of the input level of the second amplifying transistor SF2, is lowered below the power supply voltage Vdd by the above-described method, the second amplifying transistor SF2 If is an enhancement type, as shown in FIG. 8, the operating region with good linearity is lowered. The input shown in FIG. 8 indicates the gate voltage, and the output shown in FIG. 8 indicates the source voltage. FIG. 8A shows an example of the relationship between the input and output voltages of the first and second amplification transistors SF1 and SF2 when the first and second amplification transistors SF1 and SF2 are both of the enhancement type. Yes.

  The output voltage, that is, the source voltage is SF1o with respect to the input voltage, that is, the gate voltage of the first amplifying transistor SF1 indicated by SF1i, and this voltage is the gate voltage of the second amplifying transistor SF2. become. As is clear from FIG. 8A, the vicinity of the lower limit of the operation region of the second amplification transistor SF2 is a region deviating from linearity. On the other hand, as shown in FIG. 8B, even if the input voltage SF2i of the second amplifying transistor SF2 is reduced by making the second amplifying transistor SF2 a depletion type, the second amplifying transistor A sufficient operating margin of SF2 can be secured.

  Further, in FIG. 1, by making at least a part of the memory Cm a MOS type capacitor, it is possible to increase the capacity density (capacity per unit area), and the capacity of the memory Cm sufficient within a limited pixel area. It becomes easy to secure the value. Further, if the MOS type capacitor is made a depletion type, the operating voltage range in which the capacity value of the memory Cm can be secured can be expanded to the lower side, and as described above, the output voltage of the first amplification transistor SF1. Even if SF1o decreases, it is possible to easily secure a certain capacity value of the memory Cm.

  In FIG. 1, the transfer transistor TX may be omitted to form a three-transistor pixel. In such a case, FIG. 1 becomes as shown in FIG. Even in the case of FIG. 9, the writing to the memory Cm and the reading from the memory Cm are the same as in the case of FIG.

Second embodiment.
FIG. 10 is a diagram illustrating an example of a pixel configuration of an amplification type solid-state imaging device according to the second embodiment of the present invention. In FIG. 10, the same or similar elements as those in FIG. 1 are denoted by the same reference numerals, and the description thereof will be omitted here, and only the differences from FIG. 1 will be described.
The difference between FIG. 10 and FIG. 1 is that the number of memories in the pixel is two, Cm1 and Cm2, and two write switches Wr1 and Wr2 and two read switches Rd1 and Rd2 are provided accordingly. Therefore, the pixel 10 in FIG.

  In FIG. 10, a pixel 50 includes a light receiving element PD, a transfer transistor TX, a reset transistor RT, a first amplification transistor SF1, a selection transistor SL, a second amplification transistor SF2, and first and second write switches Wr1 and Wr2. The first and second read switches Rd1, Rd2, the first and second memories Cm1, Cm2 and the initialization transistors IT for initializing the first and second memories Cm1, Cm2 are provided. Each of the first and second write switches Wr1 and Wr2 and each of the first and second read switches Rd1 and Rd2 includes NMOS transistors. Note that the memory Cm1 has a first capacity, the memory Cm2 has a second capacity, the first write switch Wr1 has a first write switch section, and the second write switch Wr2 has a second write switch section. The first read switch Rd1 forms a first read switch unit, and the second read switch Rd2 forms a second read switch unit.

  When the connection portion between the gate of the second amplification transistor SF2 and the initialization transistor IT is FD2, the first write transistor Wr1 and the first read transistor are connected between the source of the first amplification transistor SF1 and the connection portion FD2. A series circuit of the transistor Rd1 and a series circuit of the second write transistor Wr2 and the second read transistor Rd2 are connected in parallel. The first memory Cm1 is connected between the connection between the first write transistor Wr1 and the first read transistor Rd1 and the ground voltage, and the connection between the second write transistor Wr2 and the second read transistor Rd2. And the ground voltage are connected to the second memory Cm2.

10 is a diagram illustrating a configuration example of a two-dimensional image sensor including a pixel array in which the pixels 50 in FIG. 10 are arranged in a matrix, except that the reference numeral of the pixels 10 in FIGS. 2 and 3 is changed to 50. Omitted. Each of the first and second write switches Wr1 and Wr2 and the first and second read switches Rd1 and Rd2 receives a control signal from the row drive circuit 15 through the signal line 16, respectively.
In such a configuration, FIG. 11 is a timing chart showing an operation example of the pixel 50 shown in FIG. 10, and the operation of the pixel 50 in FIG. 10 will be described with reference to FIG.

The write operation is simultaneous for all rows. In FIG. 11, first, the reset transistor RT is turned on / off in the period t1 to reset the voltage of the connection portion FD, and then in the period t2, the first write switch Wr1 is turned on, and the connection portion FD at this time The voltage is written to the first memory Cm1 as the reset level FR by the write operation of the present invention described with reference to FIGS.
Next, in period t3, the transfer transistor TX is turned on to transfer the signal charge to the connection part FD, and in period t4, the second write switch Wr2 is turned on to change the voltage of the connection part FD changed by the signal charge. The signal level FS is written into the second memory Cm2 by the same write operation as in the case of t2. Finally, in the period t5, the reset transistor RT is turned on / off again to discharge the signal charge of the connection portion FD and reset the connection portion FD. In this manner, the reset level FR and the signal level FS can be independently written in a batch for each pixel in the two memories Cm1 and Cm2.

Reading of signals written in the memories Cm1 and Cm2 is sequentially performed in units of rows. For example, an arbitrary i-th row is as follows. In the reference numerals, (i) indicates the i-th row and (i + 1) indicates the (i + 1) -th row.
First, in the period t6, the initialization transistor IT (i) is turned on / off, and the voltage of the connection FD2 (i) that becomes the gate voltage of the second amplification transistor SF2 (i) that forms the second-stage source follower. Is initialized to a low voltage V1 such as a ground voltage.
Next, in a period t7, after the selection transistor SL (i) between the second amplification transistor SF2 (i) and the read signal line Vsig is turned on, the read switch Rd1 (i) is turned on, and the first The reset level FR held in the memory Cm1 (i) is read out.

Next, in a period t8, the initialization transistor IT (i) is turned on / off again to erase the signal read out earlier and reset the voltage of the connection portion FD2.
In a period t9, the second read switch Rd2 (i) is turned on to read the signal level FS held in the second memory Cm2 (i).
In the period t10, the selection transistor SL (i) is turned off, the initialization transistor IT (i) is turned on, and each of the first and second read switches Rd1 (i) and Rd2 (i) is turned on. The first and second memories Cm1 and Cm2 are simultaneously reset to the low voltage V1 to prepare for a write operation in the next frame.

  In this way, with respect to the two signals FR and FS read out, a reset that occurs in the connection unit FD is performed by performing a correlated double sampling (CDS) operation that takes a difference between the two in a subsequent processing circuit (not shown). Not only can noise be removed, but the threshold value varies between pixels in each of the first amplification transistor SF1 forming the first-stage source follower and the second amplification transistor SF2 forming the second-stage source follower. It is possible to remove the fixed pattern noise generated for each pixel.

In FIG. 10, the selection transistor SL may be omitted. In such a case, FIG. 10 becomes as shown in FIG. 12 is the same as the configuration example of the two-dimensional image sensor including the pixel array in which the pixels 50 in FIG. 12 are arranged in a matrix except that the reference numeral of the pixel 10 in FIGS. 2 and 3 is changed to 50. I will omit it.
In such a configuration, FIG. 13 is a timing chart showing an operation example of the pixel 50 in FIG. 12, and the operation of the pixel 50 in FIG. 12 will be described with reference to FIG.

In FIG. 13, the write operation is the same as in FIG. Also in FIG. 13, reading of signals written in the memories Cm1 and Cm2 is sequentially performed in units of rows. For example, an arbitrary i-th row is as follows. Also in the code | symbol of FIG. 13, (i) shows that it is the thing of the i-th line, (i + 1) has shown that it is the thing of the (i + 1) -th line.
In FIG. 12, the initialization transistor IT is normally turned on (on except during the read operation). Therefore, in the read operation, all the initialization transistors IT are turned on in the non-selected rows, and in these pixels, the connection portion FD2 is fixed to the low voltage V1 such as the ground voltage. For this reason, the second amplifying transistor SF2 constituting the source follower is turned off.

  In the read row i, the initialization transistor IT (i) is turned off only in the periods t7 and t9, and the connection portion FD2 (i) is in a floating state. In the period t7, the first read transistor Rd1 (i) is turned on during this period, the reset level FR is read from the first memory Cm1 (i) to the connection portion FD2 (i), and the connection portion FD2 (i) The voltage becomes a large voltage corresponding to this. Therefore, the second amplification transistor SF2 (i) is turned on only in such row i, and the reset level FR of row i is selectively read out.

  Similarly, in the period t9, the second read switch Rd2 (i) is turned on during this period, the signal level FS is read from the second memory Cm2 (i) to the connection unit FD2 (i), and the connection unit FD2 ( The voltage i) becomes a large voltage corresponding thereto, and the signal level FS of this row i is selectively read out. Since the operation range is FR ≧ FS, if FS> V1, reading can be performed without being affected by the non-selected rows. Further, the CDS operation for taking the difference between the reset level FR and the signal level FS in the subsequent processing circuit (not shown) is the same as in the case of FIGS.

Third embodiment.
In the case of the pixel configuration shown in the second embodiment, when the reset transistor RT is turned on in the period t1 to reset the connection portion FD, the output side Va of the first amplifying transistor SF1 is in a floating state, and the voltage Therefore, the indefinite voltage information is stored in the capacitor Ca between the connecting portion FD and the output side Va. This is because when the reset transistor RT is turned off and the connecting portion FD is in a floating state, the voltage of the connecting portion FD is influenced by the indefinite voltage information through the capacitor Ca, and an error occurs. A configuration in which such an error is eliminated is referred to as a third embodiment of the present invention.

FIG. 14 is a diagram illustrating an example of a pixel configuration of an amplification type solid-state imaging device according to the third embodiment of the present invention. In FIG. 14, the same or similar parts as those in FIG. 10 are denoted by the same reference numerals, and description thereof is omitted here, and only differences from FIG. 10 are described.
14 differs from FIG. 10 in that a control switch Wr3, which is an NMOS transistor, is connected in parallel to the first amplification transistor SF1, and accordingly, the pixel 50 in FIG. The control switch Wr3 forms a control switch unit.
In FIG. 14, when the control switch Wr3 is on, it is desirable that the control switch Wr3 be a depletion type MOS transistor so that the voltage on the output side Va of the first amplification transistor SF1 becomes the power supply voltage Vdd. Alternatively, although not shown, the drain side of the control switch Wr3 may be a predetermined DC voltage different from the power supply voltage Vdd.

In FIG. 14, a pixel 60 includes a light receiving element PD, a transfer transistor TX, a reset transistor RT, a first amplification transistor SF1, a selection transistor SL, a second amplification transistor SF2, and first and second write switches Wr1 and Wr2. , First and second read switches Rd1, Rd2, control switch Wr3, first and second memories Cm1, Cm2, and initialization transistors for initializing the first and second memories Cm1, Cm2 It has IT.
14 is a diagram showing a configuration example of a two-dimensional image sensor including a pixel array in which the pixels 60 in FIG. Omitted. In the control switch Wr3, a control signal from the row driving circuit 15 is input to the gate through the signal line 16.

In such a configuration, FIG. 15 is a timing chart showing an operation example of the pixel 60 shown in FIG. 14, and the operation of the pixel 60 in FIG. 14 will be described with reference to FIG.
In FIG. 15, first, in the period ta within the first reset period t1, the reset transistor RT and the control switch Wr3 are simultaneously turned on to reset the connection portion FD and set the voltage on the output side Va to the power supply voltage Vdd. The determined voltage information is written in the capacitor Ca. Thereafter, in the period t2 to t5, the operation shown in FIG. 11 is performed without causing an error. Such an operation is performed collectively for all the pixels, and the subsequent readout operation is exactly the same as in FIG.

  In each of the first to third embodiments, the case where each MOS transistor in the pixel is an NMOS type has been described as an example. However, this is an example, and the present invention is not limited to this. The case of the PMOS type can be similarly applied by reversing the polarity of the voltage and current. Further, the case where the signal charge of the light receiving element PD is an electron has been described as an example. However, even in the case of a hole, the present invention can be similarly applied because the polarity change due to signal accumulation is reversed.

10, 50, 60 pixels PD light receiving element TX transfer transistor RT reset transistor SF1 first amplification transistor SF2 second amplification transistor Wr write switch SL selection transistor IT initialization transistor Cm memory Wr1 first write switch Wr2 second write Switch Wr3 Control switch Rd1 First read switch Rd2 Second read switch Cm1 First memory Cm2 Second memory R, Rcol, Rfrm Resistance CL Constant current load transistors 11, 12, 13 Power supply line 14 rows Decoder circuit 15 rows Drive circuit 16 Drive line 17 Column signal processing circuit 18 Column decoder circuit 19 Horizontal signal line 20 Pixel array

Claims (12)

In an amplification type solid-state imaging device including a pixel array in which a plurality of unit pixels each having a memory are arranged in a matrix, and a control circuit unit that performs operation control on each pixel constituting the pixel array,
Each pixel is
A photoelectric conversion unit that generates and outputs a signal corresponding to the received light; and
A first amplification transistor composed of a MOS transistor for inputting a signal output from the photoelectric conversion unit to a gate and amplifying and outputting the signal input to the gate;
A first capacitor forming the memory for storing a signal output from the first amplification transistor;
A first write switch unit that performs output control to the first capacitor to control writing to the first capacitor with respect to a signal output from the first amplification transistor;
A second amplifying transistor comprising a MOS transistor for inputting a signal written in the first capacitor to a gate and amplifying and outputting the signal input to the gate;
An initialization transistor for initializing a signal written in the first capacitor to a predetermined first voltage;
Each with
The first amplifying transistor uses only the first capacitor as a load, and the first write switch unit performs the initialization after the initialization of the first capacitor is performed by the initialization transistor. During the period in which the amplifying transistor shifts from the saturation region operation to the subthreshold region operation and becomes a metastable state, the signal output from the first amplifying transistor is output to the first capacitor to the first capacitor. An amplifying solid-state imaging device, wherein   The control circuit unit operates each of the pixels constituting the pixel array at the same time to perform a write operation on the first capacitor in each of the pixels, and then performs each of the pixels by a predetermined method. 2. The amplification type solid-state imaging device according to claim 1, wherein reading from the first capacitor is sequentially performed.   Each pixel in the pixel array is characterized in that the first amplification transistor is connected to a power supply line in a column unit, and the power supply line is connected to a predetermined power supply voltage through a resistor for each column unit. The amplification type solid-state imaging device according to claim 2. In each pixel in the pixel array, the first amplifying transistor is connected to a power supply line in units of columns, and the power supply lines in all columns are connected to each other through a connection portion. The amplification type solid-state imaging device according to claim 2, wherein the amplification type solid-state imaging device is connected to a power supply voltage.   When the control circuit section sequentially reads out each row from the pixel array, the second amplification transistor becomes inactive with respect to the initialization transistor in each pixel of the non-selected row. The amplification type solid-state imaging device according to claim 1, wherein the amplification type solid-state imaging device is initialized to one voltage. Each pixel is
One or more second capacitors forming the memory for storing a signal output from the first amplification transistor;
One or more second write switch units for performing output control to the corresponding second capacitor and controlling writing to the second capacitor with respect to the signal output from the first amplification transistor When,
A first read switch unit for controlling output to the gate of the second amplification transistor with respect to a signal written to the first capacitor;
One or more second read switch units for controlling output to the gate of the second amplification transistor with respect to a signal written in the corresponding second capacitor;
With
The first amplification transistor uses only the first or second capacitor as a load, and the initialization transistor initializes a signal written in the second capacitor to the predetermined first voltage, and In the second write switch unit, after the initialization of the second capacitor is performed by the initialization transistor, the first amplification transistor shifts from a saturation region operation to a subthreshold region operation to be in a metastable state. The signal output from the first amplifying transistor is output to the second capacitor during a period, and writing to the second capacitor is performed. Amplifying solid-state imaging device described in 1.   Each of the pixels includes a reset transistor that resets the gate of the first amplification transistor to a predetermined second voltage, and each of the first and second write switch units includes the first and second capacitors. On the other hand, the output signal from the first amplification transistor when the gate is reset is written to one capacitor, and the output signal from the photoelectric conversion unit is input to the gate. 7. The amplification type solid-state imaging device according to claim 6, wherein an output signal from the amplification transistor is written to the other capacitor. The amplification type solid-state imaging device according to claim 7 , wherein each of the pixels includes a control switch unit that outputs a predetermined voltage to an output terminal of the first amplification transistor when the gate is reset. .   The amplification type solid-state imaging device according to claim 1, wherein the first amplification transistor is an enhancement type MOS transistor.   The amplification type solid-state imaging device according to claim 9, wherein the second amplification transistor is a depletion type MOS transistor.   The amplification type solid-state imaging device according to claim 1, wherein the first capacitor includes a MOS capacitor at least in part.   12. The amplification type solid-state imaging device according to claim 11, wherein the MOS type capacitor is a depletion type MOS type capacitor.

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