JP2008060269A - Photoelectric conversion apparatus, and imaging apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a photoelectric conversion apparatus which can obtain a high quality image while suppressing generation of a false signal. <P>SOLUTION: The photoelectric conversion apparatus comprises a pixel array region 100, a constant current source region 200 having a plurality of constant current sources arranged to be connected to a plurality of column signal lines respectively, and a differential circuit region 300. The photoelectric conversion apparatus further comprises a first ground pattern 201 for the constant current source region 200, and a second ground pattern 301 for the differential circuit region 300. Inside of a region CA including the constant current source region 200 and the differential circuit region 300, the first ground pattern 201 and the second ground pattern 301 are separated from each other. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a photoelectric conversion device and an imaging device.

FIG. 2 is a diagram illustrating an example of a photoelectric conversion device (solid-state imaging device). The photoelectric conversion device 30 illustrated in FIG. 2 includes a pixel array region 100, a constant current source region 200, a column amplifier region 300, a storage capacitor region 400, and an output amplifier region 450. The pixel array region 100 is a region including a pixel array in which a plurality of pixel portions 6 are arranged in a matrix in the XY direction and a signal is output through a plurality of column signal lines PV. Each pixel unit 6 can be configured to include, for example, a photodiode 1, a charge transfer transistor 2, a reset transistor 3, an amplification transistor 4, and a selection transistor 5. The constant current source region 200 is a region in which a plurality of constant current sources 7 respectively connected to a plurality of column signal lines PV are arranged in the X direction. The column amplifier region 300 is a region where a plurality of column amplifier units 11 are arranged in the X direction. Each column amplifier unit 11 may be configured to include, for example, a differential amplifier 8, a clamp capacitor 9, a feedback capacitor 10, and a clamp control switch CS. Each column amplifier unit 11 can be a difference circuit (clamp CDS circuit) that outputs a signal corresponding to the difference between the optical signal level and the reset level. The storage capacitor region 400 is a region in which a plurality of storage capacitor units 18 are arranged in the X direction. Each holding capacitor unit 18 includes a reset level writing transistor 12, an optical signal level writing transistor 13, a reset level holding capacitor 14, an optical signal level holding capacitor 15, a reset level transfer transistor 16, and an optical signal level transfer transistor 17. Can be configured. The output amplifier area 450 includes the output amplifier 19.
JP 2003-51989 JP 2005-223559 A

  Consider a case where light is incident on a part of the pixel array region 100 in the photoelectric conversion device illustrated in FIG. For example, it is assumed that light is incident only on the central portion of the pixel array region 100 and no light is incident on the peripheral portion of the pixel array region 100. At this time, in the case of an ideal photoelectric conversion device, since a large amount of optical signal charge is generated in the central portion of the pixel array region 100, the optical signal level is high and the optical signal level holding capacitor 15 is high. A potential is written. On the other hand, since no optical signal charge is generated in the peripheral portion of the pixel array region 100, the optical signal level is the same as the reset level, and the optical signal level holding capacitor 15 is written with the same potential as the reset level holding capacitor 14. It is. As a result, as illustrated in FIG. 11, a white image can be output from the center of the screen, and a black image can be output from the photoelectric conversion device at the periphery of the screen.

  However, the actual image does not have to be illustrated in FIG. 11, and as illustrated in FIGS. 12 and 13, the light intensity on the pixel array region is generated by generating a false signal at the signal level at the periphery of the screen. The distribution (optical image) and the image output from the photoelectric conversion device are different.

  The present invention has been made with the above problem recognition as an opportunity, and an object thereof is to provide a photoelectric conversion apparatus that can obtain, for example, a high-quality image in which generation of false signals is suppressed.

  The photoelectric conversion device of the present invention includes a pixel array in which a plurality of pixel units are arranged and outputs a signal through a plurality of column signal lines, a plurality of constant current sources respectively connected to the plurality of column signal lines, and the plurality of the plurality of column signal lines. A plurality of differential circuits that are respectively connected to the column signal lines and output a signal corresponding to the difference between the optical signal level and the reset level; and a first region for the first region in which the plurality of constant current sources are arranged. A second ground pattern for a second region in which the plurality of differential circuits are arranged, and at least a part of the first ground pattern is disposed in the first region; At least a portion of the first ground is disposed in the second region, and the first ground is disposed at least between the first region and the second region inside the region including the first region and the second region. Characterized in that said the turn second ground pattern are separated from each other.

  According to the present invention, for example, it is possible to obtain a high-quality image in which generation of false signals is suppressed.

  Hereinafter, a photoelectric conversion device (solid-state imaging device) according to a preferred embodiment of the present invention will be described with reference to the accompanying drawings.

  A photoelectric conversion device (solid-state imaging device) 30 according to a preferred embodiment of the present invention has a circuit configuration as illustrated in FIG. The circuit configuration is as already described. Hereinafter, the operation of the photoelectric conversion device 30 will be described with reference to FIG.

  The photodiode (photoelectric conversion unit) 1 receives light and generates electric charges. The reset transistor 3 resets the potential of the floating diffusion portion (floating diffusion) FD to a predetermined potential. The charge transfer transistor 2 transfers charges generated in the photodiode 1 to the floating diffusion portion FD in accordance with a transfer pulse provided to the gate when reading an optical signal. The potential of the floating diffusion FD is determined by the amount of charge transferred to it. The amplification transistor 4 constitutes a source follower circuit together with the constant current source 7, and amplifies a signal corresponding to the potential of the floating diffusion portion FD when the selection transistor 5 controlled by the row selection signal is activated. Output to the signal line PV.

  Here, reading of the signal from the pixel unit 6 includes reading of the reset level and reading of the optical signal level. The reset level is output to the column signal line PV through the amplification transistor 4 and the selection transistor 5 after the potential of the floating diffusion portion FD is reset by the reset transistor 3 and before the charge transfer transistor is activated. The optical signal level is output to the column signal line PV via the amplification transistor 4 and the selection transistor 5 in a state where the charge generated in the photodiode 1 is transferred to the floating diffusion portion FD via the charge transfer transistor 2.

  The signal (reset level, optical signal level) output to the column signal line PV is amplified by the column amplifier unit 11. The column amplifier unit 11 amplifies the signal output to the column signal line PV with an inversion gain determined by the ratio of the clamp capacitor 9 and the feedback capacitor 10. More specifically, when the reset level is read, the clamp control switch CS is turned on, the output and the inverting input terminal of the differential amplifier 8 are set to the reference potential VREF, and then the clamp control switch CS is turned off, so that the clamp capacitor 9 is turned on. The reset level is written. Next, when the charge transfer transistor 2 is activated and the charge generated in the photodiode 1 is transferred to the floating diffusion FD via the charge transfer transistor 2, the optical signal level appears on the column signal line PV. The column amplifier unit 11 inverts and amplifies the difference between the reset level written in the clamp capacitor 9 and the optical signal level and outputs the result.

  The output when the clamp control switch CS is turned on (the reset level of the column amplifier unit 11) is written to the reset level holding capacitor 14 via the reset level write transistor 12. The output when the difference between the reset level written in the clamp capacitor 9 and the optical signal level is input to the column amplifier unit 11 (the optical signal level of the column amplifier unit 11) is supplied to the optical signal level write transistor 13. To the optical signal level holding capacitor 15.

  After the reset level and the optical signal level are written to the reset level holding capacitor 14 and the optical signal level holding capacitor 15, respectively, the reset level transfer transistor 16 and the optical signal level transfer transistor 17 are activated in the column order. Thereby, the reset level and the optical signal level of the column amplifier unit 11 are provided to the output amplifier 19 in the column order. The output amplifier 19 calculates the difference between the optical signal level of the column amplifier unit 11 and the reset level and outputs it as a pixel signal.

  Here, the cause of the generation of the false signal will be described.

  When a current flows through the ground pattern, if the resistance of the ground pattern is large, for example, a potential difference occurs between a portion near the ground pad 20 and a portion far from the ground pad 20 due to a voltage drop. Therefore, it is desirable that the ground pattern has as low resistance as possible. Therefore, a common and continuously extending ground pattern 501 can be arranged in the constant current source region 200, the column amplifier region 300, and the storage capacitor region 400 so that the width of the ground pattern is as large as possible. This is illustrated in FIG. With such an arrangement, the potential difference between the portion close to and far from the ground pad 20 can be minimized.

  The reason why the false signal is generated in the photoelectric conversion device having such a ground pattern arrangement will be described. As described above, it is assumed that light is incident only on the central portion of the pixel array region 100 and no light is incident on the peripheral portion of the pixel array region 100. In this case, since a large amount of optical signal charge is generated in the central portion of the pixel array region 100, the optical signal level changes greatly. In addition, since no optical signal charge is generated in the peripheral portion of the pixel array region 100, the optical signal level is equal to the reset level.

  This optical signal level is sent to the column amplifier unit 11. At this time, the potential of the clamp capacitor 9 in the column corresponding to the central portion of the pixel array region greatly varies from a low potential in the initial state to a high potential. The fluctuation may cause the ground potential of the column amplifier unit 11 to fluctuate.

  In the ground pattern arrangement example shown in FIG. 3, the column amplifier region 300 and the constant current source region 200 are connected by a common continuously spreading ground pattern 501. Therefore, the resistance value between the constant current source region 200 and the column amplifier region 300 is smaller than the resistance value between the constant current source region 200 and the ground pad 20. Therefore, before the ground potential fluctuation of the column amplifier unit 11 converges, it propagates to the constant current source region 200 and fluctuates the ground potential of the constant current source 7.

  As a result, the current amount of the constant current source 7 when reading signals from the pixels in the peripheral portion of the pixel array region 100 is slightly different from the original current amount, and the signals from the pixels are also shifted. . Therefore, in the peripheral part of the image output from the solid-state imaging device, even when no optical signal charge is generated, the reset level and the optical signal level are different from each other, and a false signal is generated.

  The same applies when the reset level is written to the reset level holding capacitor 14 via the reset level writing transistor 12 and the optical signal level is written to the optical signal level holding capacitor 15 via the optical signal level writing transistor 13. is there. For the column corresponding to the central portion of the pixel array region, since a high potential is written in the optical signal level storage capacitor 15, the potential of the potential holding side node 15a of the optical signal level storage capacitor 15 is increased from a low potential in the initial state. It will fluctuate greatly to the potential. Due to the change, the potential of the ground-side node 15b of the optical signal level holding capacitor 15 also changes to a slightly higher potential. Similarly, it propagates to the constant current source region 200 and changes the ground potential of the constant current source 7. Further, the signal propagates to the column amplifier region 300 and changes the ground potential of the column amplifier unit 11. Therefore, a false signal is finally generated.

This slight shift is not a problem when shooting a normal image, but it is a problem when shooting a dark image such as a night view. In night scene shooting, most of the screen is black, so a slight shift in the black level tends to stand out. In night scene shooting, since the amount of light is small, a large gain is applied to the output of the solid-state imaging device, so that a slight deviation is amplified.
For this reason, the background that should originally be black can generate a false signal due to a bright subject such as a foreground light or illumination, resulting in a mottled black background.

Hereinafter, an improved ground pattern based on the above problem recognition will be described as an example.
[First Embodiment]
FIG. 1 is a diagram illustrating the arrangement of ground patterns in the photoelectric conversion device according to the first embodiment of the present invention. The ground pattern 502 in the photoelectric conversion device 30 according to the first embodiment of the present invention includes a first ground pattern 201 for the constant current source region (corresponding to the first region) 200 and a column amplifier region (corresponding to the second region). The second ground pattern 301 for 300, the third ground pattern 401 for the storage capacitor region (corresponding to the third region) 400, and the common ground pattern 510 are included. When the second area includes a difference circuit, the second area can also be referred to as a difference circuit area.

  The first and second ground patterns 301 and 401 are separated from each other inside the region CA including the constant current source region 200, the column amplifier region 300, and the storage capacitor region 400, and outside the region CA by the common ground pattern 510. Electrically connected. From another viewpoint, the first and third patterns 201 and 301 are separated from each other inside the constant current source region 200 inside the region CA including the column amplifier region 300 and the storage capacitor region 400, and outside the region CA. The common ground pattern 510 is electrically connected. In another aspect, the first, second, and third patterns 201, 301, and 401 are separated from each other inside the area CA including the column amplifier area 300 and the storage capacitor area 400 in the constant current source area 200, and the area CA In the outside, the common ground pattern 510 is electrically connected. According to such a ground pattern 502, propagation of potential fluctuations between the first, second, and third ground patterns is reduced, and generation of false signals can be suppressed.

  Here, the area CA includes at least a first area and a second area, and also includes an intermediate area arranged between the first area and the second area. In general, a constant current source, a differential circuit, a column amplifier, etc. often have a part of components (elements such as transistors) arranged on a semiconductor substrate, and the ground pattern is based on the element formation surface of the semiconductor substrate. And arranged above. Therefore, the first ground pattern and the second ground pattern are separated from each other on the first region, the intermediate region, or the second region with reference to the element formation surface. You can also The region between the first ground pattern and the second ground pattern may overlap the first region and / or the second region.

  In order to prevent the generation of false signals more effectively, the resistance of the common ground pattern 510 should be sufficiently small.

  FIG. 4 is a diagram showing the relationship between the resistance value of the common ground pattern 510 and the false signal level obtained by simulation. The horizontal axis represents the resistance value of the common ground pattern 510 normalized by the resistance value of the second ground pattern 301 for the column amplifier region 300. The vertical axis is read from the pixel portion of the peripheral portion (the portion where no light is incident) of the pixel array region 100 normalized by the optical signal level read from the pixel portion of the central portion (the portion where the light is incident) of the pixel array region 100. This is a false signal level generated in the optical signal level. Here, the resistance value of the second ground pattern 301 for the column amplifier region 300 is a resistance value between both ends of the second ground pattern 301 in the direction along the row of the pixel array region 100 (X direction). 1 is the resistance value of the portion indicated by the length L1. Further, the resistance value of the common ground turn 510 is a resistance value between the third ground pattern 401 and the ground pad 20 for the storage capacitor region 400 in the entire common ground pattern 510. In FIG. And the resistance value of the portion indicated by the length L2. The reason for evaluating the resistance value of the common ground pattern 510 in this way is that the potential fluctuation of the third ground pattern 510 for the storage capacitor region 400 has an influence on the potential of the second ground pattern 301 for the column amplifier region 300. This is to evaluate the resulting false signal.

  The pixel signal output from the photoelectric conversion device 30 can be digitally processed and output by an image processing unit disposed in the subsequent stage. When the image processing unit performs 10-bit digital processing, the resolution of the optical signal (pixel signal) is 1/1024. If the false signal level is 1/1024 or less with respect to the light signal level read from the light incident portion, that is, the pixel portion at the center of the pixel array region 100, the image quality of the output image will be an acceptable level. .

  4, when the normalized resistance value of the common ground pattern 510 is 1 (that is, when the resistance value of the common ground pattern 510 is the same as the resistance value of the second ground pattern 301 for the column amplifier region 300). .), The false signal level is 1/1024 or less of the maximum level of the optical signal.

  From the above discussion, when the image processing unit performs 10-bit digital processing, it can be said that the resistance value of the common ground pattern 510 is preferably smaller than the resistance value of the second ground pattern 301 for the column amplifier region 300. . In other words, the value obtained by dividing the length L2 of the portion of the common ground pattern 510 between the third ground pattern 401 and the ground pad 20 by the width W2 divided the length L1 of the second ground pattern 301 by the width W1. Preferably it is smaller than the value.

  The resolution when the image processing unit is performing 14-bit digital processing is 1/16382. In this case, it is preferable that the false signal level is 1/16382 or less of the maximum level of the optical signal. 4, when the normalized resistance value of the common ground pattern 510 is 0.2 (that is, the resistance value of the common ground pattern 510 is 1 / of the resistance value of the second ground pattern 301 for the column amplifier region 300). 5), the maximum false signal level of the optical signal is 1/16382 or less.

  Therefore, when the image processing unit performs 14-bit digital processing, the resistance value of the common ground pattern 510 only needs to be smaller than 1/5 of the resistance value of the second ground pattern 301 for the column amplifier region 300. In other words, the value obtained by dividing the length L2 of the portion of the common ground pattern 510 between the third ground pattern 401 and the ground pad 20 by the width W2 divided the length L1 of the second ground pattern 301 by the width W1. It is preferably smaller than 1/5 of the value.

[Second Embodiment]
FIG. 5 is a diagram illustrating the arrangement of ground patterns in the photoelectric conversion device according to the second embodiment of the present invention. In this embodiment, the resistance value of the common ground pattern 510 is smaller than that of the common ground pattern 510 in the first embodiment. Specifically, the first ground pattern 201, the second ground pattern 301, and the third ground pattern 401 are routed to the vicinity of the ground pad 20 and connected to the common ground pattern 510. According to such a ground pattern arrangement, for example, the resistance value of the common ground pattern 510 can be easily reduced to 1/5 or less of the resistance value of the second ground pattern 301 for the column amplifier region 300.

[Third Embodiment]
FIG. 6 is a diagram illustrating the arrangement of ground patterns in the photoelectric conversion device according to the third embodiment of the present invention. In this embodiment, the first ground pattern 201 for the constant current source region 200, the second ground pattern 301 for the column amplifier region 300, and the third ground pattern 401 for the storage capacitor region 400 are completely separated from each other. Has been. A ground pad is also provided separately. That is, the first ground pad 21 for the constant current source region 200, the second ground pad 22 for the column amplifier region 300, and the third ground pad 23 for the storage capacitor region 400 are individually provided.

  With this configuration, the common impedance between the first, second, and third ground patterns is 0 in the photoelectric conversion device, and propagation of ground potential fluctuations can be minimized.

[Fourth Embodiment]
FIG. 7 is a diagram illustrating a circuit configuration of a photoelectric conversion apparatus according to the fourth embodiment of the present invention. FIG. 8 is a diagram illustrating the arrangement of ground patterns in the photoelectric conversion device according to the fourth embodiment of the present invention.

  The solid-state imaging device 40 illustrated in FIG. 7 includes a pixel array region 100, a constant current source region 200, a clamp CDS region 600, and an output amplifier region 450. The pixel array region 100 is a region in which a plurality of pixel portions 6 are arranged in a matrix in the XY direction. Each pixel unit 6 can be configured to include, for example, a photodiode 1, a charge transfer transistor 2, a reset transistor 3, an amplification transistor 4, and a selection transistor 5. The constant current source region 200 is a region configured by arranging a plurality of constant current sources 7 in the X direction. The clamp CDS region 600 is a region where a plurality of clamp CDS portions (difference circuits) 42 are arranged in the X direction. Each clamp CDS unit 42 includes a clamp capacitor 9, a clamp capacitor reset transistor 41, an optical signal level holding capacitor 15, and an optical signal level transfer transistor 17. The output amplifier region 450 includes the output amplifier 19 ′. In this configuration, a signal corresponding to the difference between the optical signal level and the reset level is written to the optical signal level holding capacitor 15 by the clamp CDS unit 42, and the output amplifier 19 ′ is sequentially output via the optical signal level transfer transistor 17. Provided to.

  The first ground pattern 201 for the constant current source region 200 and the second ground pattern 601 for the clamp CDS region 600 are separated from each other inside the region CA ′ including the constant current source region 200 and the clamp CDS region 600. It is preferable. Thereby, it is possible to suppress the influence of the fluctuation of the ground potential generated in the clamp CDS region 600 on the ground potential of the constant current region 200.

[Fifth Embodiment]
FIG. 9 is a diagram illustrating the arrangement of the ground pattern 504 in the photoelectric conversion device according to the fifth embodiment of the present invention. In the photoelectric conversion device of this embodiment, the constant current source region 200, the column amplifier region 300, and the storage capacitor region 400 are respectively arranged above and below, and signal charges are read out simultaneously by two channels (or more).

  Also in the photoelectric conversion device having such a configuration, generation of a false signal can be suppressed by reducing the resistance value of the common ground pattern as in the first embodiment.

[Sixth Embodiment]
FIG. 10 is a diagram illustrating the arrangement of the ground pattern 505 in the photoelectric conversion device according to the sixth embodiment of the present invention. In this embodiment, the resistance value of the common ground pattern 501 is smaller than that of the fifth embodiment. Specifically, the first ground pattern 201, the second ground pattern 301, and the third ground pattern 401 are routed to the vicinity of the ground pad 20 and connected to the common ground pattern 510.

  According to such an arrangement of the ground pattern, for example, the resistance value of the common ground pattern 510 can be easily set to 1/5 or less of the resistance value of the second ground pattern 301 for the column amplifier region 300.

[Application example]
FIG. 14 is a diagram showing a schematic configuration of an imaging apparatus according to a preferred embodiment of the present invention. The imaging device 400 includes a solid-state imaging device 1004 typified by the photoelectric conversion devices of the first to sixth embodiments.

  An optical image of the subject is formed on the imaging surface of the solid-state imaging device 1004 by the lens 1002. On the outside of the lens 1002, a barrier 1001 serving both as a protection function of the lens 002 and a main switch can be provided. The lens 1002 can be provided with a diaphragm 1003 for adjusting the amount of light emitted therefrom. The imaging signal output from the solid-state imaging device 1004 through a plurality of channels is subjected to various corrections, clamping, and the like by the imaging signal processing circuit 1005. Imaging signals output from the imaging signal processing circuit 1005 through a plurality of channels are analog-digital converted by the A / D converter 6. The image data output from the A / D converter 1006 is subjected to various corrections, data compression, and the like by a signal processing unit (image processing unit) 1007. The solid-state imaging device 1004, the imaging signal processing circuit 1005, the A / D converter 1006, and the signal processing unit 1007 operate according to the timing signal generated by the timing generation unit 1008.

  The blocks 1005 to 1008 may be formed on the same chip as the solid-state image sensor 1004. Each block of the imaging apparatus 400 is controlled by the overall control / arithmetic unit 1009. In addition, the imaging apparatus 400 includes a memory unit 1010 for temporarily storing image data and a recording medium control interface unit 1011 for recording or reading an image on a recording medium. The recording medium 1012 includes a semiconductor memory or the like and can be attached and detached. The imaging apparatus 400 may include an external interface (I / F) unit 1013 for communicating with an external computer or the like.

  Next, the operation of the imaging apparatus 400 illustrated in FIG. 14 will be described. When the barrier 1001 is opened, the main power source, the control system power source, and the power source of the imaging system circuit such as the A / D converter 1006 are sequentially turned on. Thereafter, the overall control / calculation unit 1009 opens the aperture 1003 in order to control the exposure amount. A signal output from the solid-state imaging device 1004 passes through the imaging signal processing circuit 1005 and is provided to the A / D converter 1006. The A / D converter 1006 A / D converts the signal and outputs it to the signal processing unit 1007. The signal processing unit 1007 processes the data and provides it to the overall control / arithmetic unit 1009, and the overall control / arithmetic unit 1009 performs an operation for determining the exposure amount. The overall control / calculation unit 1009 controls the aperture based on the determined exposure amount.

  Next, the overall control / calculation unit 1009 extracts a high frequency component from the signal output from the solid-state imaging device 1004 and processed by the signal processing unit 1007, and calculates the distance to the subject based on the high frequency component. Thereafter, the lens 1002 is driven to determine whether or not it is in focus. When it is determined that the subject is not in focus, the lens 1002 is driven again to perform distance measurement.

  Then, after the in-focus state is confirmed, the main exposure starts. When the exposure is completed, the imaging signal output from the solid-state imaging device 1004 is corrected and the like in the imaging signal processing circuit 1005, A / D converted by the A / D converter 1006, and processed by the signal processing unit 1007. The image data processed by the signal processing unit 1007 is accumulated in the memory unit 1010 by the overall control / calculation 1009.

  Thereafter, the image data stored in the memory unit 1010 is recorded on the recording medium 1012 via the recording medium control I / F unit under the control of the overall control / calculation unit 9. The image data can be provided to a computer or the like through the external I / F unit 1013 and processed.

It is a figure which illustrates arrangement | positioning of the ground pattern in the photoelectric conversion apparatus of 1st Embodiment of this invention. It is a figure which shows an example of a photoelectric conversion apparatus (solid-state imaging device). It is a figure which illustrates arrangement | positioning of the ground pattern of a photoelectric conversion apparatus. It is a figure which shows the relationship between the resistance value of the common ground pattern calculated | required by simulation, and a false signal level. It is a figure which illustrates arrangement | positioning of the ground pattern in the photoelectric conversion apparatus of 2nd Embodiment of this invention. It is a figure which illustrates arrangement | positioning of the ground pattern in the photoelectric conversion apparatus of 3rd Embodiment of this invention. It is a figure which illustrates the circuit structure of the photoelectric conversion apparatus of 4th Embodiment of this invention. It is a figure which illustrates arrangement | positioning of the ground pattern in the photoelectric conversion apparatus of 4th Embodiment of this invention. It is a figure which illustrates arrangement | positioning of the ground pattern in the photoelectric conversion apparatus of 5th Embodiment of this invention. It is a figure which illustrates arrangement | positioning of the ground pattern in the photoelectric conversion apparatus of 6th Embodiment of this invention. This is an original image when light is incident only on the central portion of the pixel array region. This is an image when a false signal is generated when light is incident only on the central portion of the pixel array region and the peripheral portion of the screen sinks black. This is an image when a false signal is generated when light is incident only on the central portion of the pixel array region, and the peripheral portion of the screen floats white. 1 is a diagram illustrating a schematic configuration of an imaging apparatus according to a preferred embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Photodiode 2 ... Charge transfer transistor 3 ... Reset transistor 4 ... Amplification transistor 5 ... Selection transistor 6 ... Pixel part 7 ... Constant current source 8 ... Differential Amplifier 9 ... Clamp capacitor 10 ... Feedback capacitor 11 ... Column amplifier 12 ... Reset level write transistor 13 ... Optical signal level write transistor 14 ... Reset level holding capacitor 15 .. Optical signal level holding capacitor 15a ... potential holding node 15b ... ground side node 16 ... reset level transfer transistor 17 ... optical signal level transfer transistor 18 ... holding capacitor unit 19 ... output Amplifier 20 ... Ground pad 21 ... Ground pad 22 in constant current source region ... Ground pad 23 in column amplifier region ... Ground pad 41 in storage capacitor region ... Clamp capacitance reset transistor 42 ... Clamp CDS part 100 ... Pixel array area 200 ... Constant current source region 201 ... First ground pattern 300 for constant current source ... Column amplifier region 301 ... Second ground pattern 400 for column amplifier region ... Retention capacitance region 401... Third ground pattern 501 to 505 for the storage capacitor region Ground pattern 510. Common ground pattern 600... Clamp CDS region 601... Second ground pattern for clamp CDS region

Claims (10)

A pixel array in which a plurality of pixel portions are arranged and outputs signals through a plurality of column signal lines;
A plurality of constant current sources respectively connected to the plurality of column signal lines;
A plurality of differential circuits connected to the plurality of column signal lines, respectively, for outputting a signal corresponding to the difference between the optical signal level and the reset level;
A first ground pattern for a first region in which the plurality of constant current sources are arranged;
A second ground pattern for the second region in which the plurality of differential circuits are arranged;
With
At least a portion of the first ground pattern is disposed in the first region;
At least a portion of the second ground pattern is disposed in the second region;
Inside the region including the first region and the second region, the first ground pattern and the second ground pattern are separated from each other at least between the first region and the second region. A photoelectric conversion device characterized by the above. A plurality of holding capacitor units respectively holding signals output from the plurality of difference circuits;
A third ground pattern for a third region in which the plurality of storage capacitor portions are arranged;
The photoelectric conversion according to claim 1, further comprising: the second ground pattern and the third ground pattern separated from each other inside a region including the second region and the third region. apparatus.   3. The photoelectric conversion according to claim 1, wherein the first ground pattern and the second ground pattern are electrically connected outside a region including the first region and the second region. apparatus.   3. The photoelectric conversion device according to claim 2, wherein the second ground pattern and the third ground pattern are electrically connected outside a region including the second region and the third region.   The first ground pattern, the second ground pattern, and the third ground pattern are electrically connected outside a region including the first region, the second region, and the third region. The photoelectric conversion device according to claim 2. A common ground pattern that electrically connects the first ground pattern and the second ground pattern outside a region including the first region and the second region;
The photoelectric conversion device according to claim 1, wherein the common ground pattern is connected to a ground pad. A common ground pattern that electrically connects the first ground pattern, the second ground pattern, and the third ground pattern outside a region including the first region, the second region, and the third region;
The photoelectric conversion device according to claim 2, wherein the common ground pattern is connected to a ground pad.   2. The photoelectric conversion device according to claim 1, wherein the first ground pattern and the second ground pattern are connected to a first ground pad and a second ground pad, respectively.   3. The photoelectric conversion according to claim 2, wherein the first ground pattern, the second ground pattern, and the third ground pattern are connected to a first ground pad, a second ground pad, and a third ground pad, respectively. apparatus. The photoelectric conversion device according to any one of claims 1 to 9,
An image processing unit for processing an image output from the photoelectric conversion device;
An imaging apparatus comprising:

Images