JP2011018936A - Substrate for multilayer wiring, and multilayer wiring board - Google Patents

Substrate for multilayer wiring, and multilayer wiring board Download PDF

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JP2011018936A
JP2011018936A JP2010211267A JP2010211267A JP2011018936A JP 2011018936 A JP2011018936 A JP 2011018936A JP 2010211267 A JP2010211267 A JP 2010211267A JP 2010211267 A JP2010211267 A JP 2010211267A JP 2011018936 A JP2011018936 A JP 2011018936A
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multilayer wiring
layer
substrate
base material
conductive paste
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JP5055415B2 (en
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Koji Honto
孝治 本戸
Satoru Nakao
知 中尾
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Fujikura Ltd
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Abstract

PROBLEM TO BE SOLVED: To improve packability of an electronic component by avoiding occurrence of waving distortion in a laminate of substrates for multilayer wiring due to a difference in hardness between an adhesive layer and a conductive material for filling a via hole in the form of conductive paste etc., when the substrates for multilayer wiring are multilayered.SOLUTION: A deformation inhibition layer 15 composed of a metal foil and a resin sheet having higher rigidity than an insulating substrate 11 is provided between the insulating substrate 11 and an adhesive layer 16.

Description

この発明は、多層配線用基材および多層配線板に関し、特に、電子部品を実装する配線板やパッケージ基板に用いられる多層配線板用基材およびフレキジブル多層配線板に関するものである。   The present invention relates to a multilayer wiring board and a multilayer wiring board, and more particularly to a multilayer wiring board substrate and a flexible multilayer wiring board used for wiring boards and package substrates on which electronic components are mounted.

電子機器の軽薄短小化、半導体チップや部品の小型化および端子の狭ピッチ化に伴いプリント配線板(配線基板)にも実装面積の縮小や配線の精細化が進んでいる。同時に、情報関連機器では、信号周波数の広帯域化に対応して部品間を連結する配線の短距離化が求められており、高密度、高性能を達成するためのプリント配線板の多層化は必要不可欠となっている。   As electronic devices become lighter and shorter, semiconductor chips and components are miniaturized, and terminals have a narrower pitch, printed wiring boards (wiring boards) are also being reduced in mounting area and finer wiring. At the same time, in information-related equipment, it is required to shorten the distance of wiring connecting parts in response to the widening of signal frequency, and it is necessary to increase the number of printed wiring boards to achieve high density and high performance. It has become indispensable.

多層プリント配線板(多層配線板)には、絶縁性基材にバイヤホール(貫通孔)を形成し、そのバイヤーホールに導電性樹脂組成物(導電性ペースト)を充填することによって基板表裏の導通(層間導通)を得るもの(例えば、特許文献1、2)、絶縁性基材をポリイミド等の可撓性樹脂フィルムで構成したものがある(例えば、特許文献3)。そして、多層配線板の高密度化に伴い、配線板に形成される配線パターン(導体パターン)の微細化が進み、積層数が多くなる傾向がある。   In a multilayer printed wiring board (multilayer wiring board), a via hole (through hole) is formed in an insulating base material, and the conductive resin composition (conductive paste) is filled in the buyer hole, thereby providing conduction between the front and back of the substrate. There are those that obtain (interlayer conduction) (for example, Patent Documents 1 and 2), and those in which the insulating base material is formed of a flexible resin film such as polyimide (for example, Patent Document 3). And with the increase in the density of multilayer wiring boards, miniaturization of wiring patterns (conductor patterns) formed on the wiring boards has progressed, and the number of layers tends to increase.

多層配線板の多層積層の層間接続技術としては、上記の導電性ペーストを用いた多層配線板が実用化され、多層配線板の用途が急速に拡大し始めている。導電性ペーストを用いた多層配線板では、スクリーン印刷法によって導電性ペーストをプリント配線板の絶縁性基材に形成されたバイヤホールに作業性よく高速度で充填でき、めっきによるものに比べて生産性が著しく高い。   As an interlayer connection technique for multilayer lamination of multilayer wiring boards, multilayer wiring boards using the above-described conductive paste have been put into practical use, and the applications of multilayer wiring boards have begun to expand rapidly. Multi-layer wiring boards using conductive paste can be filled at high speed with good workability into via holes formed on the insulating substrate of printed wiring boards by screen printing. The property is remarkably high.

また、絶縁性基材の一方の面に配線パターンをなす導体層を有する銅箔付きフィルムを出発材として、絶縁性基材の表面(導体層とは反対側の表面)にPET等によるカバー層(マスクフィルム)を形成してバイヤホールを形成し、カバー層側からスクリーン印刷法等によって導電ペーストの充填を行ない、導電性ペーストを仮硬化させた後に、カバー層を除去することにより、カバー層の厚さに相当する高さの導電性ペーストによる突起部を形成した多層配線用基材が提案されている(例えば、特許文献4、5、6)。   Also, starting from a film with copper foil having a conductor layer forming a wiring pattern on one surface of the insulating base material, a cover layer made of PET or the like on the surface of the insulating base material (the surface opposite to the conductor layer) By forming a (mask film) to form a via hole, filling the conductive paste from the cover layer side by screen printing or the like, temporarily curing the conductive paste, and then removing the cover layer, the cover layer A multilayer wiring substrate in which a protrusion is formed by a conductive paste having a height corresponding to the thickness of the substrate has been proposed (for example, Patent Documents 4, 5, and 6).

この多層配線用基材では、多層化工程時のプレス圧によって導電性ペースト突起部を導通相手の配線パターン表面に押し付けたり、突き刺したりすることにより、バイアホールの導電性ペーストと配線パターンとの導通接触をよくし、導電性ペーストと配線パターンとの接触抵抗を下げることが行なわれている。   In this multi-layer wiring substrate, the conductive paste protrusions are pressed against or pierced the surface of the conductive wiring pattern by the pressing pressure during the multi-layering process, thereby conducting the conductive paste between the via hole and the wiring pattern. In order to improve the contact, the contact resistance between the conductive paste and the wiring pattern is lowered.

しかし、この手法を用いると、多層化工程のプレス時に、導電性ペーストによる突起と層間接着を行う接着剤の硬さとが異なるために、厚さ方向に歪みを生じると云う問題点がある。導電性ペーストによる突起部を有する多層配線用基材による多層配線板の問題点を図9(a)、(b)を参照して説明する。   However, when this method is used, there is a problem that distortion occurs in the thickness direction due to the difference in protrusion between the conductive paste and the hardness of the adhesive that performs interlayer adhesion when pressing in the multilayering process. Problems of the multilayer wiring board using the multilayer wiring substrate having the protrusions made of the conductive paste will be described with reference to FIGS. 9 (a) and 9 (b).

多層配線用基材は、2枚の多層配線用基材100と110とを積層接着したものである。   The multilayer wiring substrate is obtained by laminating and bonding two multilayer wiring substrates 100 and 110.

上層の多層配線用基材100は、ポリイミド樹脂フィルム等による絶縁性基材101の一方の面(上面)に導体パターン102を形成され、絶縁性基材101の他方の面(下面)にフィルム状接着層103を貼り合わされ、絶縁性基材101とフィルム状接着層103にあけられたバイヤホール104に導電性ペースト105が充填され、フィルム状接着層103の側に導電性ペースト105による突起部106を有する。   The upper-layer multilayer wiring substrate 100 has a conductive pattern 102 formed on one surface (upper surface) of an insulating substrate 101 made of a polyimide resin film or the like, and a film shape on the other surface (lower surface) of the insulating substrate 101. The adhesive layer 103 is bonded, and the conductive paste 105 is filled in the via hole 104 formed in the insulating base material 101 and the film-like adhesive layer 103, and the protrusion 106 by the conductive paste 105 is formed on the film-like adhesive layer 103 side. Have

最下層の多層配線用基材110は、ポリイミド樹脂フィルム等による絶縁性基材111の一方の面(上面)に導体パターン112を形成されている。   The lowermost multilayer wiring substrate 110 has a conductor pattern 112 formed on one surface (upper surface) of an insulating substrate 111 made of a polyimide resin film or the like.

多層配線用基材100と110は、加熱プレスによってフィルム状接着層103によって互いに接着され、積層される。突起部106は図9(b)に示されているように、積層時に、下層の多層配線用基材110の導体パターン112に強く密着し、電気的接続を強化する役割をはたす。   The multilayer wiring substrates 100 and 110 are bonded to each other by the film adhesive layer 103 by a hot press and laminated. As shown in FIG. 9 (b), the protrusion 106 strongly adheres to the conductor pattern 112 of the lower multilayer wiring substrate 110 during lamination, and plays a role of strengthening electrical connection.

しかし、多層配線用基材100、110の積層が加熱プレスにより行われることにより、この積層工程時に接着層103が軟化して流動性をもち、導電性ペースト105の突起106が接着層103に比べ硬いことから、図9(b)や図10に示されているように、積層体に波打ち状の歪みを生じる。   However, since the multilayer wiring substrates 100 and 110 are laminated by hot pressing, the adhesive layer 103 is softened and has fluidity during the lamination process, and the protrusion 106 of the conductive paste 105 is compared with the adhesive layer 103. Since it is hard, as shown in FIG. 9B and FIG. 10, wavy distortion occurs in the laminate.

この波打ち状の歪みは、絶縁性基材101がポリイミド等の可撓性フィルムによって構成されるフレキシブル多層配線板において顕著になる。   This wavy distortion becomes prominent in a flexible multilayer wiring board in which the insulating substrate 101 is made of a flexible film such as polyimide.

そして、このような波打ち状の歪みは、電子部品の実装性能を阻害する原因になる。また、図10に示されているように、ビア・オン・ビアでない層間導通部では、その接続信頼性に支障をきたす。   Such wavy distortion is a cause of hindering the mounting performance of the electronic component. Further, as shown in FIG. 10, in the interlayer conductive portion that is not via-on-via, the connection reliability is hindered.

特開平6−302957号公報JP-A-6-302957 特開平9−82835号公報Japanese Patent Laid-Open No. 9-82835 特開2001−237512号公報JP 2001-237512 A 特開平7−147464号公報JP-A-7-147464 特開2002−26522号公報JP 2002-26522 A 特開2002−353619号公報JP 2002-353619 A

この発明が解決しようとする課題は、多層配線用基材の多層化時に、接着層と導電性ペースト等によるバイヤホール充填の導電性材料との硬さの違いにより、多層配線用基材の積層体、つまり多層配線板に波打ち状の歪みが生じることを回避し、電子部品の実装性能の向上を図ることである。   The problem to be solved by the present invention is that the multilayer wiring substrate is laminated due to the difference in hardness between the adhesive layer and the conductive material filled with the via hole by the conductive paste when the multilayer wiring substrate is multilayered. This is to avoid the occurrence of wavy distortion in the body, that is, the multilayer wiring board, and to improve the mounting performance of the electronic component.

この発明による多層配線用基材は、絶縁性基材の一方の面に配線パターンを形成されて配線層をなす形成された導体層を有し、前記絶縁性基材の他方の面の側に接着層を有し、前記導体層と前記接着層を貫通した貫通孔に充填された導電性材料によって層間接続を取る多層配線用基材であって、前記絶縁性基材と前記接着層との間に歪み抑制層が設けられ、前記歪み抑制層は、前記絶縁性基材より高剛性の樹脂シートにより構成されている。   The multilayer wiring substrate according to the present invention has a conductor layer formed to form a wiring layer on one surface of the insulating substrate, and on the other surface side of the insulating substrate. A multi-layer wiring substrate having an adhesive layer and having interlayer connection by a conductive material filled in a through-hole penetrating the conductor layer and the adhesive layer, the insulating substrate and the adhesive layer A strain suppression layer is provided therebetween, and the strain suppression layer is made of a resin sheet having higher rigidity than the insulating base material.

この発明による多層配線用基材は、好ましくは、前記歪み抑制層が、複数個に分離して配置されている。   In the base material for multilayer wiring according to the present invention, preferably, the strain suppression layer is arranged separately in a plurality.

この発明による多層配線用基材は、好ましくは、前記歪み抑制が、格子状あるいは網目状のスリットにより、複数個に分離して配置されている。   In the multi-layer wiring substrate according to the present invention, preferably, the distortion suppression is arranged in a plurality of pieces by a lattice-like or mesh-like slit.

この発明による多層配線用基材は、好ましくは、前記絶縁性基材が可撓性材料により構成され、フレキジブル多層配線板用の基材である。   The base material for multilayer wiring according to the present invention is preferably a base material for a flexible multilayer wiring board in which the insulating base material is made of a flexible material.

この発明による多層配線基板は、上述の発明による多層配線用基材を含むものである。     The multilayer wiring board according to the present invention includes the substrate for multilayer wiring according to the above-described invention.

この発明による多層配線用基材では、金属箔や絶縁性基材より高剛性の樹脂シート等による歪み抑制層が絶縁性基材と接着層との間に存在することにより、積層時の接着層と貫通孔に充填されている導電性材料との硬さの違いによって多層配線用基材の積層体である多層配線基板(多層配線用基材)に波打ち状の歪みが生じることが回避される。   In the multilayer wiring substrate according to the present invention, a strain suppression layer made of a resin sheet or the like having a rigidity higher than that of the metal foil or the insulating substrate is present between the insulating substrate and the adhesive layer. And the conductive material filled in the through-holes avoids the occurrence of wavy distortion in the multilayer wiring substrate (multilayer wiring substrate) that is a laminate of the multilayer wiring substrate. .

これにより、多層配線基板の平坦性が改善され、多層配線基板における電子部品の実装性能が向上する。   Thereby, the flatness of the multilayer wiring board is improved, and the mounting performance of the electronic components on the multilayer wiring board is improved.

(a)〜(i)は、この発明による多層配線用基材、多層配線板およびその製造工程の一つの実施形態を示す工程図(断面図)である。(A)-(i) is process drawing (sectional drawing) which shows one Embodiment of the base material for multilayer wiring by this invention, a multilayer wiring board, and its manufacturing process. この発明による多層配線用基材を用いた多層配線板の一つの実施形態を示す断面図である。It is sectional drawing which shows one Embodiment of the multilayer wiring board using the base material for multilayer wiring by this invention. この発明による多層配線用基材の他の実施形態を示す断面図である。It is sectional drawing which shows other embodiment of the base material for multilayer wiring by this invention. この発明による多層配線用基材の他の実施形態を示す平面図である。It is a top view which shows other embodiment of the base material for multilayer wiring by this invention. 図4の線V−Vに沿った拡大断面図である。FIG. 5 is an enlarged sectional view taken along line VV in FIG. 4. この発明による多層配線用基材の他の実施形態を示す平面図である。It is a top view which shows other embodiment of the base material for multilayer wiring by this invention. 他の実施形態による多層配線用基材の斜視図である。It is a perspective view of the base material for multilayer wiring by other embodiment. 他の実施形態による多層配線用基材の拡大断面図である。It is an expanded sectional view of the base material for multilayer wiring by other embodiment. 従来における導電性ペーストによる突起部を有する多層配線用基材による多層配線板の問題点の説明図である。It is explanatory drawing of the problem of the multilayer wiring board by the base material for multilayer wiring which has the projection part by the conventional electrically conductive paste. 従来における導電性ペーストによる突起部を有する多層配線用基材による多層配線板の問題点の説明図である。It is explanatory drawing of the problem of the multilayer wiring board by the base material for multilayer wiring which has the projection part by the conventional electrically conductive paste.

この発明による多層配線用基材、多層配線板およびその製造工程の一つの実施形態を、図1を参照して説明する。   One embodiment of a substrate for multilayer wiring, a multilayer wiring board and a manufacturing process thereof according to the present invention will be described with reference to FIG.

図1(a)に示されているように、ポリイミド、熱可塑性ポリイミド、液晶ポリマ等による可撓性樹脂フィルム製の絶縁性基材11の両面に銅箔層(導体層)12、13を有する両面銅張り積層板(例えば、銅箔厚さ10μm、ポリイミドフィルム厚さ25μm)10を出発材とし、図1(b)に示されているように、銅箔層12と13を塩化鉄を用いた銅エッチング法によってエッチングする。   As shown in FIG. 1A, copper foil layers (conductor layers) 12 and 13 are provided on both surfaces of an insulating base material 11 made of a flexible resin film made of polyimide, thermoplastic polyimide, liquid crystal polymer, or the like. A double-sided copper-clad laminate (for example, copper foil thickness 10 μm, polyimide film thickness 25 μm) 10 is used as a starting material, and copper foil layers 12 and 13 are made of iron chloride as shown in FIG. Etching is performed by the copper etching method.

銅箔層12は、エッチングにより、配線パターンを形成されて配線層14をなす。   The copper foil layer 12 is formed with a wiring pattern by etching to form a wiring layer 14.

銅箔層13は、エッチングによって、層間導通のための貫通孔(バイアホール)形成予定部Aの部分を、後述の貫通孔18の内径より充分に大きい径をもって除去され、歪み抑制層15をなす。   The copper foil layer 13 is removed by etching so that a portion of a through hole (via hole) formation scheduled portion A for interlayer conduction is sufficiently larger than the inner diameter of a through hole 18 described later, thereby forming a strain suppression layer 15. .

歪み抑制層15は、図1(b)に示されているように、配線層14の配線パターンに重ならないようにパターンニングすることもできる。これにより、厚み及び厚さ方向の剛性が面内で均一になる。   The strain suppression layer 15 can also be patterned so as not to overlap the wiring pattern of the wiring layer 14 as shown in FIG. Thereby, the thickness and the rigidity in the thickness direction become uniform in the plane.

つぎに、図1(c)に示されているように、絶縁性基材11の歪み抑制層15の側の面に、例えば、エポキシ樹脂とアクリル系エラストマからなるフィルム状熱硬化接着剤シート(厚さ25μm)を、100℃、30秒で熱ラミネートして接着層16を形成する。   Next, as shown in FIG. 1C, a film-like thermosetting adhesive sheet (for example, made of an epoxy resin and an acrylic elastomer) is formed on the surface of the insulating base 11 on the strain suppression layer 15 side. The adhesive layer 16 is formed by heat laminating at a thickness of 25 μm) at 100 ° C. for 30 seconds.

これにより、絶縁性基材11と接着層16との間に、歪み抑制層15が、これらに挟まれた状態で介在する。   Thereby, between the insulating base material 11 and the contact bonding layer 16, the distortion suppression layer 15 is interposed in the state pinched | interposed into these.

そして、さらに、接着層16の表面に、カバー層17として、たとえば、ポリイミドフィルム(厚さ25μm)を、100℃、30秒で熱ラミネートして貼り合わせる。   Further, as a cover layer 17, for example, a polyimide film (thickness: 25 μm) is thermally laminated at 100 ° C. for 30 seconds and bonded to the surface of the adhesive layer 16.

つぎに、図1(d)に示されているように、所定位置(貫通孔形成予定部A)に、UV−YAGレーザ(波長335nm)により、絶縁性基材11と接着層16とカバー層17を貫通した貫通孔(バイヤホール)18を明ける。貫通孔18は、孔径が100μm程度で、配線層14の裏面に到達して配線層14の裏面を穴底面とする層間導通用の穴である。   Next, as shown in FIG. 1 (d), the insulating base material 11, the adhesive layer 16, and the cover layer are formed at a predetermined position (through hole formation scheduled portion A) by a UV-YAG laser (wavelength 335 nm). A through hole (via hole) 18 penetrating 17 is opened. The through hole 18 is a hole for interlayer conduction having a hole diameter of about 100 μm and reaching the back surface of the wiring layer 14 and having the back surface of the wiring layer 14 as a bottom surface of the hole.

配線層14が貫通孔18と対応する部分の中央位置には、孔径が30μm程度の小孔19が貫通形成されている。小孔19は、後の導電性ペースト充填工程で、空気抜き孔として作用して導電性ペースト充填がスムーズに行われるように設けられるものである。   A small hole 19 having a hole diameter of about 30 μm is formed through the central position of the portion where the wiring layer 14 corresponds to the through hole 18. The small holes 19 are provided so that the conductive paste can be filled smoothly by acting as an air vent hole in the subsequent conductive paste filling step.

つぎに、図1(e)に示されているように、小孔19から空気を減圧吸引しながら、カバー層17の側より導電性ペースト20をスキージ50によるスクリーン印刷法によって貫通孔18と小孔19に充填する。この導電性ペースト20の充填は、図1(f)に示されているように、カバー層17の表面に到達するまで、すり切り一杯に行う。   Next, as shown in FIG. 1 (e), while the air is sucked from the small holes 19 under reduced pressure, the conductive paste 20 is made small from the through holes 18 by screen printing using a squeegee 50 from the cover layer 17 side. The holes 19 are filled. As shown in FIG. 1 (f), the conductive paste 20 is completely filled until it reaches the surface of the cover layer 17.

導電性ペースト20は、銀、銅、カーボン混合物等、導電機能を有する金属粉末を樹脂バインダに混入したものを、溶剤を含む粘性媒体に混ぜてペースト状にしたである。   The conductive paste 20 is a paste obtained by mixing a metal powder having a conductive function such as a mixture of silver, copper, and carbon in a resin binder with a viscous medium containing a solvent.

導電性ペースト20の充填は、スキージ50によるスクリーン印刷法以外に、ディスベンス法、インクジェット法等によって行うこともできる。   The filling of the conductive paste 20 can also be performed by a dispersion method, an ink jet method, or the like other than the screen printing method using the squeegee 50.

導電性ペースト20の充填完了後、加熱によって導電性ペースト20の半硬化処理を行う。   After completing the filling of the conductive paste 20, the conductive paste 20 is semi-cured by heating.

この後に、図1(g)に示されているように、カバー層17を剥離等によって除去する。これにより、剥離されたカバー層17の厚さ相当分、接着層16の表面より外方に突出した突起部21を含む導電性ペースト20による層間導通部が形成され、歪み抑制層15を含む一枚の多層配線用基材30が完成する。   Thereafter, as shown in FIG. 1G, the cover layer 17 is removed by peeling or the like. As a result, an interlayer conductive portion is formed by the conductive paste 20 including the protruding portion 21 protruding outward from the surface of the adhesive layer 16 by an amount corresponding to the thickness of the peeled cover layer 17. A sheet of multilayer wiring substrate 30 is completed.

なお、歪み抑制層15は、導電性ペースト20による層間導通部においては、貫通孔18の内径より充分に大きい径をもって除去されているから、層間導通部の導電性ペースト20と電気的に短絡することがない。   In addition, since the strain suppression layer 15 is removed with a diameter sufficiently larger than the inner diameter of the through hole 18 in the interlayer conductive portion formed by the conductive paste 20, it is electrically short-circuited with the conductive paste 20 in the interlayer conductive portion. There is nothing.

図1(h)、(i)は、多層配線用基材30を用いた多層配線板の製造工程を示している。   1 (h) and 1 (i) show a manufacturing process of a multilayer wiring board using the multilayer wiring substrate 30. FIG.

多層配線用基材30は、多層配線板の上層側の多層配線用基材をなし、この実施形態では、最下層の多層配線用基材40とで、2層の多層配線板を構成する。   The multilayer wiring substrate 30 is a multilayer wiring substrate on the upper layer side of the multilayer wiring board. In this embodiment, the lowermost multilayer wiring substrate 40 forms a two-layer multilayer wiring board.

最下層の多層配線用基材40は、ポリイミド、熱可塑性ポリイミド、液晶ポリマ等による可撓性の絶縁性基材41の一方の面に、銅箔層をエッチングして形成された配線層42を有する。   The lowermost multilayer wiring substrate 40 has a wiring layer 42 formed by etching a copper foil layer on one surface of a flexible insulating substrate 41 made of polyimide, thermoplastic polyimide, liquid crystal polymer, or the like. Have.

図1(h)に示されているように、多層配線用基材30は、図1(g)に示されている状態より上下反転して、多層配線用基材40上に位置合わせ配置される。多層配線用基材30と40は、所定加熱温度、所定加圧力による加熱プレスにより図1(i)に示されているように、接着層16によって互いに積層接着される。この加熱により、層間導通部をなす導電性ペースト20が本硬化(完全硬化)する。   As shown in FIG. 1 (h), the multilayer wiring substrate 30 is vertically aligned from the state shown in FIG. 1 (g) and aligned and arranged on the multilayer wiring substrate 40. The The multilayer wiring substrates 30 and 40 are laminated and adhered to each other by the adhesive layer 16 as shown in FIG. By this heating, the conductive paste 20 forming the interlayer conductive portion is fully cured (completely cured).

この積層により、導電性ペースト20は、突起部21が符号22によって示されているように下層側の配線層42に突き当たって押し潰されたような状態で、上層側の配線層14と下層側の配線層42とを導通接続する。   As a result of this lamination, the conductive paste 20 is in a state in which the protrusion 21 hits the lower wiring layer 42 as indicated by reference numeral 22 and is crushed. The wiring layer 42 is electrically connected.

このような積層接着工程において、絶縁性基材11より高剛性(銅箔製:高硬度)の歪み抑制層15が、絶縁性基材11の接着層16の側に裏打ちされたような状態で存在するから、接着層16と導電性ペースト20との硬さの違いによって、絶縁性基材11ならびに接着層16に波打ち状の歪みが生じることが抑制される。これにより、図1(i)に示されているように、平滑性に優れた多層配線板、特に、フレキシブル多層配線板が得られ、フレキシブル多層配線板における電子部品の実装性能が向上する。   In such a laminating and bonding step, the strain suppressing layer 15 having higher rigidity (made of copper foil: high hardness) than the insulating base material 11 is lined on the adhesive layer 16 side of the insulating base material 11. Therefore, it is possible to suppress the occurrence of wavy distortion in the insulating base material 11 and the adhesive layer 16 due to the difference in hardness between the adhesive layer 16 and the conductive paste 20. Thereby, as shown in FIG. 1I, a multilayer wiring board excellent in smoothness, in particular, a flexible multilayer wiring board is obtained, and the mounting performance of electronic components on the flexible multilayer wiring board is improved.

図2は、2枚の多層配線用基材30と最下層の多層配線用基材40による3層の多層配線板の例を示している。なお、図2において、図1に対応する部分は、図1に付した符号と同一の符号を付けて、その説明を省略する。   FIG. 2 shows an example of a three-layer multilayer wiring board including two multilayer wiring substrates 30 and a lowermost multilayer wiring substrate 40. 2, parts corresponding to those in FIG. 1 are denoted by the same reference numerals as those in FIG. 1, and description thereof is omitted.

図2に示されているように、ビア・オン・ビアでない層間導通部を含む多層配線板でも、絶縁性基材11より高剛性(高硬度)の歪み抑制層15が、絶縁性基材11の接着層16の側に裏打ちされたような状態で存在するから、接着層16と導電性ペースト20との硬さの違いによって、絶縁性基材11ならびに接着層16に波打ち状の歪みが生じることが抑制される。   As shown in FIG. 2, even in a multilayer wiring board including an interlayer conductive portion that is not via-on-via, the strain suppressing layer 15 having higher rigidity (hardness) than the insulating base material 11 is provided with the insulating base material 11. Therefore, a wavy distortion occurs in the insulating substrate 11 and the adhesive layer 16 due to the difference in hardness between the adhesive layer 16 and the conductive paste 20. It is suppressed.

歪み抑制層15が、上述した実施形態のように、銅箔層である場合には、汎用の両面銅張り積層板を出発材とすることができるから、製造工程を簡素化できて安価に製造できるが、本発明は、これに限られることはなく、歪み抑制層15は、絶縁性基材11より高剛性(高硬度)のシート状材料であればよい。フレキシブル多層配線板の場合には、歪み抑制層15は、フレキシブル多層配線板の可撓性を大きく阻害しない程度の可撓性を有している必要がある。   When the strain suppression layer 15 is a copper foil layer as in the above-described embodiment, a general-purpose double-sided copper-clad laminate can be used as a starting material, so that the manufacturing process can be simplified and manufactured at low cost. However, the present invention is not limited to this, and the strain suppression layer 15 may be a sheet-like material having higher rigidity (high hardness) than the insulating base material 11. In the case of a flexible multilayer wiring board, the strain suppression layer 15 needs to have a degree of flexibility that does not significantly hinder the flexibility of the flexible multilayer wiring board.

この条件を満たす歪み抑制層として、銅箔層による歪み抑制層15以外に、図3に示されているように、接着性を有する樹脂フィルムによる歪み抑制層25がある。   As a strain suppression layer satisfying this condition, there is a strain suppression layer 25 made of a resin film having adhesiveness as shown in FIG. 3 in addition to the strain suppression layer 15 made of a copper foil layer.

樹脂フィルム製の歪み抑制層25は、電気絶縁性を有するから、層間導通部の導電性ペースト2と電気的短絡を避ける考慮を必要としない。従って、歪み抑制層25にも、バイアホール成形時に、貫通孔18(図1(d)参照)と同径の貫通孔が設けられればよく、工程増加を招かない。   Since the strain suppression layer 25 made of a resin film has electrical insulation, it does not require consideration to avoid an electrical short circuit with the conductive paste 2 in the interlayer conductive portion. Accordingly, the strain suppression layer 25 may be provided with a through-hole having the same diameter as the through-hole 18 (see FIG. 1D) at the time of via-hole molding, and the number of processes is not increased.

また、図4、図5に示されているように、一枚の大判の多層配線用基材60より複数の製品部61を打ち抜き、一枚の多層配線用基材60より複数個の製品部61を得る場合には、つまり、製品部61と、製品部61の周りにあって製品部61の打ち抜きにより、スケルトン状になる余剰代部62となる部分を有するようなものの場合には、この余剰代部62にのみ歪み抑制層15を配置するようにしても良い。   Also, as shown in FIGS. 4 and 5, a plurality of product parts 61 are punched out from one large multilayer wiring substrate 60 and a plurality of product parts are formed from one multilayer wiring substrate 60. In the case of obtaining 61, that is, in the case where the product part 61 has a part that becomes a skeleton-like surplus part 62 by punching the product part 61 around the product part 61, You may make it arrange | position the distortion suppression layer 15 only in the surplus margin part 62. FIG.

このような場合も、積層時に、接着層16と導電性ペースト20との硬さの違いによって、絶縁性基材11ならびに接着層16に波打ち状の歪みが生じることが、余剰代部62にある歪み抑制層15によって抑制される。そして、製品部61には、製品として不要な歪み抑制層15が存在することがないから、歪み抑制層15が製品部61の電気的信頼性を低下することがない。   Even in such a case, the surplus margin 62 may cause undulating distortion in the insulating base material 11 and the adhesive layer 16 due to the difference in hardness between the adhesive layer 16 and the conductive paste 20 during lamination. It is suppressed by the strain suppression layer 15. And since the distortion suppression layer 15 unnecessary as a product does not exist in the product part 61, the distortion suppression layer 15 does not reduce the electrical reliability of the product part 61.

また、図6、図7、図8に示されているように、歪み抑制層15は、格子状あるいは網目状にしてもよい。   Further, as shown in FIGS. 6, 7, and 8, the strain suppression layer 15 may have a lattice shape or a mesh shape.

この場合には、熱キュア時に、絶縁性基材11と歪み抑制層15との間に生じた水分が外部へ逃げ易くなり、絶縁性基材11と歪み抑制層15との接着力の低下が防止される。また、スリット24に接着層16が入り込むことにより、接着層16による層間接着強度も改善される。   In this case, during heat curing, moisture generated between the insulating base material 11 and the strain suppression layer 15 can easily escape to the outside, and the adhesive force between the insulating base material 11 and the strain suppression layer 15 is reduced. Is prevented. In addition, when the adhesive layer 16 enters the slit 24, the interlayer adhesive strength by the adhesive layer 16 is also improved.

10 両面銅張り積層板
11 絶縁性基材
12、13 銅箔層
14 配線層
15、25 歪み抑制層
16 接着層
17 カバー層
18 貫通孔
19 小孔
20 導電性ペースト
21 突起部
30 多層配線用基材
40 多層配線用基材
41 絶縁性基材
42 配線層
DESCRIPTION OF SYMBOLS 10 Double-sided copper clad laminated board 11 Insulating base material 12, 13 Copper foil layer 14 Wiring layer 15, 25 Strain suppression layer 16 Adhesive layer 17 Cover layer 18 Through-hole 19 Small hole 20 Conductive paste 21 Protrusion part 30 Base for multilayer wiring Material 40 Base material for multilayer wiring 41 Insulating base material 42 Wiring layer

Claims (5)

絶縁性基材の一方の面に配線パターンを形成されて配線層をなす導体層を有し、前記絶縁性基材の他方の面の側に接着層を有し、前記絶縁性基材と前記接着層を貫通した貫通孔に充填された導電性材料によって層間接続を取る多層配線用基材であって、
前記絶縁性基材と前記接着層との間に歪み抑制層が設けられ、前記歪み抑制層は、前記絶縁性基材より高剛性の樹脂シートにより構成されている多層配線用基材。
A wiring layer is formed on one surface of the insulating base material to form a wiring layer, and a conductive layer is formed on the other surface side of the insulating base material. The insulating base material and the insulating base material A multilayer wiring substrate that takes an interlayer connection with a conductive material filled in a through-hole penetrating an adhesive layer,
A multilayer wiring substrate, wherein a strain suppression layer is provided between the insulating substrate and the adhesive layer, and the strain suppression layer is made of a resin sheet having higher rigidity than the insulating substrate.
前記歪み抑制層は、複数個に分離して配置されている請求項1記載の多層配線用基材。   The base material for multilayer wiring according to claim 1, wherein the strain suppression layer is arranged separately in a plurality. 前記歪み抑制層は、格子状あるいは網目状のスリットにより、複数個に分離して配置されている請求項2記載の多層配線用基材。   The base material for multilayer wiring according to claim 2, wherein the strain suppression layer is arranged in a plurality of pieces by a lattice-like or mesh-like slit. 前記絶縁性基材が可撓性材料により構成され、フレキジブル多層配線板用の基材である請求項1〜3の何れか1項記載の多層配線用基材。   The substrate for multilayer wiring according to any one of claims 1 to 3, wherein the insulating substrate is made of a flexible material and is a substrate for a flexible multilayer wiring board. 請求項1〜4の何れか1項記載の多層配線用基材を含む多層配線板。   The multilayer wiring board containing the base material for multilayer wiring in any one of Claims 1-4.
JP2010211267A 2010-09-21 2010-09-21 Multilayer wiring substrate and multilayer wiring board Expired - Fee Related JP5055415B2 (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004031803A (en) * 2002-06-27 2004-01-29 Fujikura Ltd Multilayer wiring board and substrate for multilayer wiring board
JP2005026588A (en) * 2003-07-04 2005-01-27 Fujikura Ltd Multilayer wiring board, base material therefor and manufacturing methods therefor
JP4728054B2 (en) * 2005-06-17 2011-07-20 株式会社フジクラ Multilayer wiring substrate, multilayer wiring substrate manufacturing method, and multilayer wiring board

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004031803A (en) * 2002-06-27 2004-01-29 Fujikura Ltd Multilayer wiring board and substrate for multilayer wiring board
JP2005026588A (en) * 2003-07-04 2005-01-27 Fujikura Ltd Multilayer wiring board, base material therefor and manufacturing methods therefor
JP4728054B2 (en) * 2005-06-17 2011-07-20 株式会社フジクラ Multilayer wiring substrate, multilayer wiring substrate manufacturing method, and multilayer wiring board

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