JP2011003023A - Touch panel driving device and touch panel device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify the structure of a wiring board by further reducing the number of wirings for transmitting various signals.SOLUTION: The touch panel device 1 includes: a touch panel 2; driving substrate 3 and 4 installed in the periphery of the touch panel 2; and a control part 5. The driving boards 3 and 4 are equipped with a plurality of drivers IC6. The driver IC 6 is configured to apply a driving voltage to the transparent electrode of the touch panel 2 based on input data, and to capture a detection voltage to be output from the transparent electrode as detection data. Signals such as a clock to be supplied to each driver IC 6, data for outputting a drive voltage and a command specifying the processing operation of each driver IC6 are successively transmitted through daisy-chain wiring between each driver IC6. Only one system of wiring is required for transmitting each signal. Thus, cables can be routed on one of the surfaces of driving boards 3 and 4 by forming each wiring so as not to cross each other.

Description

  The present invention relates to a touch panel driving device for driving a matrix type touch panel and a touch panel device including the touch panel driving device.

  Since the matrix type touch panel can detect simultaneous touch operations at a plurality of points, it can be suitably used for inputting a command defined by touch input at a plurality of points. Such a matrix-type touch panel has a plurality of transparent electrodes arranged in a biaxial direction intersecting each other, and a driving voltage is applied to each transparent electrode in one direction, and each transparent electrode in the other direction is applied to each transparent electrode. By detecting the output voltage that appears, the coordinates of the touch input are specified.

  In order to apply the drive voltage to each transparent electrode, an instruction is given to the driver to output the drive voltage from the CPU. Further, in order to detect the output voltage from each of the transparent electrodes, the output voltage is transmitted to the CPU.

  However, in the touch panel as described above, as the resolution increases, the number of wiring lines for signal transmission between the CPU and each transparent electrode of the touch panel increases, resulting in an inconvenience of increasing the size.

  In order to eliminate such inconvenience, for example, Patent Document 1 discloses a configuration in which a plurality of transparent electrodes are grouped, and parallel conversion means and serial conversion means are provided in each group in order to reduce the number of wires. Yes. Specifically, in this configuration, the serial instruction signal from the CPU is shifted by the parallel conversion means to be converted into parallel and supplied to the drivers of each group, and the drive voltage is applied to the transparent electrodes of each group. Further, the parallel detection signals output from the transparent electrodes of each group are shifted to serial by the serial conversion means, and the serial detection signals from the serial conversion means are sequentially added and transmitted to the CPU. Thereby, since the signal is transmitted by one serial, the number of wirings can be greatly reduced.

JP 9-274538 A (published on October 21, 1997)

Application Note 4024 “SPI / I2C Bus Line Controlling Multiple Peripherals” [Online], October 29, 2007, Maxim, [Search March 6, 2009], Internet <URL: http: / /japan.maxim-ic.com/appnotes.cfm/an_pk/4024>

  In the configuration described in Patent Document 1, although the number of wires is reduced only for the transmission of a specific signal between the CPU and the touch panel, to transmit a clock or the like other than such a signal, Dedicated wiring is required between the CPU and each group. However, since these wirings cross on the substrate, in order to avoid this, it is necessary to use a multilayer substrate as a substrate on which the driver is mounted. Since such a multilayer substrate has a complicated structure, the production thereof is complicated and the cost is increased.

  Non-Patent Document 1 discloses that, in a serial interface, a plurality of devices are daisy chained to transmit data output from a microcontroller to each device via a daisy chain connection. Yes. However, in such a configuration, a clock and a chip select signal are individually supplied from the microcontroller to each device, and thus have the same problem as the configuration described in Patent Document 1.

  The present invention has been made in view of the above-described problems, and an object thereof is to further reduce the number of wires for transmitting various signals and to simplify the structure of a wiring board.

  The touch panel drive device according to the present invention applies a drive voltage to a plurality of first electrodes in a matrix-type touch panel based on drive data, and detects a detection voltage for detecting a touch from the plurality of second electrodes intersecting the first electrode. A touch panel driving device including a plurality of driving integrated circuits that output detection data, wherein each driving integrated circuit is connected in a daisy chain, and driving data to the plurality of first electrodes is continuously configured. The serial drive data is converted to parallel by shifting and output to each first electrode, and the detection data obtained in parallel from the plurality of second electrodes is shifted to thereby convert the parallel drive data Defined by data shift means for converting detection data into serial data and command data given from outside Shift control means for starting a shift operation of the drive data and the detection data by the data shift means by executing a command, and the drive data, the detection data, and the command data are the integrated circuit for driving The serial format is continuous every time and is transmitted to each driving integrated circuit connected in a daisy chain together with a clock.

  In the above configuration, each driving integrated circuit is daisy-chain connected, and serial-type driving data, the detection data, and the command data are transmitted to the next-stage driving integrated circuit. Further, in each driving integrated circuit, when the command of the command data is executed by the shift control unit, the driving operation of the drive data and the detection data by the data shift unit is started. By this shift operation, a driving voltage based on driving data is applied to each first electrode, and detection data based on a detection voltage is captured from each second electrode. The above shift operation is performed in synchronization with the clock. In this way, since each driving integrated circuit is connected in a daisy chain, the number of fan-outs to each driving integrated circuit becomes one for each data, and the number of wirings on the board on which the driving integrated circuit is mounted is reduced. can do. In addition, the daisy chain connection makes it possible to form the wirings so as not to cross each other. As a result, the wiring can be formed on the same surface of the substrate, and the substrate need not be formed of a multilayer substrate.

  In the touch panel driving device, each driving integrated circuit determines whether the driving data and the detection data are to be shifted by the data shifting unit, and whether the shifting is necessary or not. It is preferable that a direct output unit that directly outputs the input drive data and the detection data through a path that does not pass through the data shift unit when determined.

  Accordingly, in each driving integrated circuit, when the shift necessity determination unit determines that the drive data and the detection data do not need to be shifted, the input drive data and the detection data are directly shifted by the output unit. Output without passing through the means. Therefore, it is possible to suppress a decrease in the transmission speed of the drive data and detection data to the drive integrated circuit after the next stage.

  In the touch panel drive device, voltage application and voltage detection are performed on the electrodes arranged in the horizontal direction with the driving integrated circuits arranged in the horizontal direction, and the electrodes arranged in the vertical direction with the driving integrated circuits arranged in the vertical direction. The drive voltage is applied and the detection voltage is detected. Further, voltage application and voltage detection are individually performed in the horizontal driving integrated circuit and the vertical driving integrated circuit. For example, when the driving voltage is applied in the horizontal driving integrated circuit, the detection voltage is detected in the vertical driving integrated circuit. Conversely, when a drive voltage is applied in the vertical driving integrated circuit, the detection voltage is detected in the horizontal driving integrated circuit.

  Therefore, when data is shifted by the data shift means in the vertical driving integrated circuit, it is not necessary to shift the data by the data shifting means in the horizontal driving integrated circuit. In this case, the data can be transmitted as it is without being passed through the data shift means in the horizontal driving integrated circuit as described above. Conversely, when data is shifted by the data shift means in the horizontal driving integrated circuit, it is not necessary to shift the data by the data shifting means in the vertical driving integrated circuit. In this case, the data can be transmitted as it is without being passed through the data shift means in the vertical driving integrated circuit as described above. Thereby, data can be transmitted at high speed without unnecessarily increasing the number of shifts.

  In the touch panel driving device, each driving integrated circuit is set with a unique ID, and the driving integrated circuit at the final stage has a final value representing the driving integrated circuit at the final stage and the ID When the command is a shift command for executing a shift operation by the data shift means, the ID is the final value, and when the command is a command other than the shift command, the ID is the final value and When the command data is not given, when the ID is 0, and when the ID is the final value or a value other than 0, termination output means is provided for outputting a termination signal for distinguishing each. It is preferable.

  Thereby, when ID is 1, when a shift command or other command is executed from the termination output means, or when command data is not given, a termination signal for determining each is output, It can be confirmed that the execution of the shift command and other commands has been completed, or that there has been no command. Moreover, since the ID is 1, it can be confirmed by the termination signal that the ID is correctly set in the driving integrated circuit at the final stage. Further, when the ID is 0 (ID is not set), it can be determined by the termination signal, so that it can be confirmed that the driving integrated circuits are correctly connected to the substrate. Further, even when an ID other than 0 and 1 is set in the final stage driving integrated circuit, it can be discriminated by the termination signal, so that the correct ID (final value = 1) is set in the driving integrated circuit. I can confirm that there is no.

  In the touch panel drive device, it is preferable that the termination output unit outputs the termination signal immediately before the detection data is shifted by the data shift unit when the detection data is output.

  The detection data output from the final stage is once read into the storage device in the control unit having an interface function between the touch panel and the external CPU, and is output to the CPU. When the detection data is read into the storage device, the termination signal is output from the termination output means immediately before the detection data is shifted. Can be confirmed.

  Further, in the touch panel driving device, the driving integrated circuit includes a first flip-flop that takes in the driving data and the detection data, and a second flip-flop that takes in the command data, and the first and second flip-flops It is preferable that the capture operation is performed in synchronization with the falling edge of the clock.

  Thereby, the occurrence of the racing phenomenon can be avoided in the capturing operation of the first and second flip-flops.

  The touch panel device of the present invention is a touch panel device including a matrix type touch panel and a touch panel drive device that drives the matrix type touch panel, and the touch panel drive device is any one of the touch panel drive devices described above.

  As described above, the touch panel drive device according to the present invention applies a drive voltage to a plurality of first electrodes in a matrix-type touch panel based on drive data, and touches from a plurality of second electrodes intersecting the first electrode. A touch panel driving device including a plurality of driving integrated circuits that output detection voltages to be detected as detection data, wherein each driving integrated circuit is connected in a daisy chain, and driving data to the plurality of first electrodes is received. Shifting the serially-configured serial driving data into parallel by shifting and outputting to each first electrode, and shifting detection data obtained in parallel from the plurality of second electrodes The data shift means for converting the parallel detection data into serial data and outputting it, and the command data given from the outside Shift control means for starting a shift operation of the drive data and the detection data by the data shift means by executing a command defined by the above-mentioned drive data, the detection data, and the command data, The serial form is continuous for each driving integrated circuit, and is transmitted together with the clock to each driving integrated circuit connected in a daisy chain. Thereby, the number of fan-outs to each driving integrated circuit becomes one for each data, and the number of wirings on the substrate on which the driving integrated circuit is mounted can be reduced. In addition, the daisy chain connection makes it possible to form the wirings so as not to cross each other. Therefore, by forming the wiring on the same surface of the substrate, there is an effect that the structure of the wiring substrate can be simplified.

It is a figure which shows the structure of the principal part of the touchscreen apparatus which concerns on embodiment of this invention. It is a figure which shows the structure of the drive substrate connected to the touchscreen in the said touchscreen apparatus, and the said touchscreen periphery. It is a block diagram which shows the structure of the driver IC provided in the said drive board | substrate. It is a figure which shows the various commands given to the said driver IC. It is a timing chart which shows the transmission timing of the said command.

  An embodiment of the present invention will be described below with reference to FIGS.

  As shown in FIG. 1, the touch panel device 1 according to the present embodiment includes a touch panel 2, drive substrates 3 and 4, and a control unit 5. The drive substrates 3 and 4 and the control unit 5 constitute a touch panel drive device in the touch panel device 1.

  As shown in FIG. 2, the touch panel 2 is a high-definition matrix type touch panel. This touch panel 2 has a transparent substrate bonded so as to face each other at a predetermined interval, and surfaces of both transparent electrodes facing each other serve as electrode forming surfaces. A plurality of transparent electrodes Eh (first electrode or second electrode) arranged in parallel with each other in the horizontal direction are formed on the electrode forming surface of one transparent substrate. A plurality of transparent electrodes Ev (first electrode or second electrode) arranged in parallel to each other in the vertical direction are formed on the electrode forming surface of the other transparent substrate. Each of the transparent electrodes Eh and Ev is a strip-shaped electrode made of a resistance film made of ITO (indium tin oxide) or the like, and is arranged so as to cross each other between the two transparent substrates.

  In the touch panel device 1, when the touch panel 2 is touched, the intersecting portions of the transparent electrodes Eh and Ev come into contact with each other at the touched location. In this state, when a drive voltage is applied to either the transparent electrode Eh or the transparent electrode Ev, the drive voltage appears on the other side through the touched portion. Therefore, the position touched on the touch panel 2 is detected by taking out this voltage as the detection voltage.

  In the following description, when the description is common to the transparent electrodes Eh and Ev, the transparent electrode E is used.

  The drive substrate 3 is connected to one end side of the transparent electrode Eh, and the drive substrate 4 is connected to one end side of the transparent electrode Ev. Each of the driving substrates 3 and 4 is provided with a plurality of driver ICs 6 (driving integrated circuits). In the drive substrate 3, the driver ICs 6 are mounted so as to be aligned in the vertical direction along the vertical connection edge of the touch panel 2. On the other hand, in the drive substrate 4, the driver ICs 6 are mounted so as to be aligned in the horizontal direction along the connection edge in the horizontal direction of the touch panel 2.

  The driver IC 6 outputs a drive voltage based on the serial data DATAIN given from the control unit 5 to the plurality of transparent electrodes Eh and Ev of the touch panel 2. Specifically, the driver IC 6 converts the data DATAIN into parallel so as to correspond to each of the transparent electrodes Eh and Ev, and generates a drive voltage to be applied to each of the transparent electrodes Eh and Ev based on the parallel data. To do. Further, the driver IC 6 outputs detection data based on the detection voltage output from the transparent electrodes Eh and Ev to the control unit 5. Specifically, the driver IC 6 detects the detection voltage output from each of the plurality of transparent electrodes Eh and Ev as parallel data, converts the detected data into serial data, and outputs the serial data.

  The driver IC 6 has a function of shifting data in order to perform serial / parallel conversion of data as described above. The driver IC 6 including this function will be described in detail later.

  Each driver IC 6 mounted on the drive substrate 3 outputs drive voltages to the plurality of transparent electrodes Eh and inputs / outputs terminals on the touch panel 2 side so that detection voltages from the plurality of transparent electrodes Eh are input. (Pin). Similarly, each driver IC 6 mounted on the drive substrate 4 outputs drive voltages to the plurality of transparent electrodes Ev and inputs / outputs to / from the touch panel 2 so that detection voltages from the plurality of transparent electrodes Ev are input. It has a terminal (pin) for use.

  Various wirings W1 to W6 are formed on the drive substrates 3 and 4. The wiring W1 inputs the data DATAIN to each driver IC 6 and outputs the data DATAIN and the detection data obtained from each driver IC 6 to the next driver IC 6 as transmission data DATANEXT (see FIG. 3). Wiring. The wiring W2 is a wiring that transmits an input command CMDIN input to each driver IC 6 and an output command CMDOUT output from each driver IC 6. Details of the command will be described later in detail.

  The wiring W3 is a wiring for inputting the input clock CLKIN supplied from the control unit 5 to each driver IC6. The wiring W4 is a wiring for inputting the reset signal RST to each driver IC 6. The wiring W5 is a wiring for outputting the serial output data DATAOUT configured by sequentially adding the detection data to all the driver ICs 6 from the last driver IC 6 to the control unit 5. The wiring W6 is a wiring for returning the return clock CLKRTN (termination signal) output from the specific driver IC 6 to the control unit 5.

  Wirings W <b> 1 to W <b> 4 that transmit input signals from the control unit 5 are connected to the driver IC 6 (the driver IC 6 at the upper end in FIG. 2) farthest from the driving substrate 4 in the driving substrate 3. The driver IC 6 uses signals transmitted from these wirings W1 to W4 for internal processing and outputs them to the adjacent driver IC 6 via the wirings W1 to W4. The driver IC 6 outputs touch detection data (data DATAEXT) acquired from the output voltages of the transparent electrodes Eh and Ev to the adjacent driver IC 6 via the wiring W1. Signal transmission between these two adjacent driver ICs 6 is also performed using the wirings W1 to W4. This is the same for the other adjacent driver ICs 6. The driver ICs 6 adjacent to each other on the drive boards 3 and 4 and the driver ICs 6 adjacent to each other between the drive boards 3 and 4 are connected via the wirings W1 to W4. Connected by daisy chain. As a result, signals are sequentially transmitted between adjacent driver ICs 6.

  Wirings W5 and W6 for transmitting output signals to the control unit 5 are connected to the driver IC 6 (the driver IC 6 at the right end in FIG. 2) farthest from the driving substrate 3 in the driving substrate 4. The driver IC 6 outputs signals transmitted from the wirings W5 and W6 to the control unit 5.

  In order to enable such daisy chain connection, in each driver IC 6, terminals (pins) to which the wirings W1 to W4 are connected are provided at positions where the wirings W1 to W4 do not intersect between adjacent driver ICs 6. It has been. Thereby, the number of fan-outs to the driver IC 5 driven by the control unit 5 becomes one for each signal, and the number of wirings on the drive boards 3 and 4 can be reduced. Also, the daisy chain connection makes it possible to form the wirings W1 to W4 so as not to cross each other. As a result, the wirings W1 to W4 can be formed on the same surface of the drive substrates 3 and 4, and the drive substrates 3 and 4 need not be formed of a multilayer substrate.

  As described above, data is sequentially transferred between the driver ICs 6 and is shifted for serial / parallel conversion in each driver IC 6. In order to simultaneously output the drive voltage to the transparent electrodes Eh and Ev and input the detection voltage from the transparent electrodes Eh and Ev, it is necessary to synchronize the timing of the shift operation with each driver IC 6.

  Therefore, each driver IC 6 is individually set with a waiting time until the shift is started by the number of clocks of the input clock CLKIN. Specifically, the number of clocks is set so that a predetermined value (for example, one) decreases sequentially from the first driver IC 6 in the daisy chain connection, and the ID (final value) of the last driver IC 6 becomes 1. , And given as an ID for identifying each driver IC 6. The ID (maximum ID value) given to the first stage driver IC 6 is included in the ID setting command in the input command CMDIN (command data), and is subtracted by a predetermined value (for example, 1) in the driver IC 6. The ID setting command given to the driver IC 6 at the next stage includes the subtracted ID, and the ID is similarly subtracted in the driver IC 6 and the driver IC 6 thereafter. In this way, each driver IC 6 acquires an ID smaller than the ID set by the preceding driver IC 6.

  Here, the driver IC 6 operates at the CMOS level (5 V). The application of the power supply voltage to the driver IC 6 is not performed by the daisy chain connection as described above, but by the power supply wiring connected to each driver IC 6. For this reason, the power supply wiring is formed on a surface different from the surface on which the wirings W1 to W4 are formed in the drive substrates 3 and 4. For example, when the wirings W <b> 1 to W <b> 4 are formed on the mounting surface of the driver IC 6 on the driving substrates 3 and 4, the power supply wiring is formed on the surface opposite to the mounting surface on the driving substrates 3 and 4.

  In the above example, a signal is input from the drive board 3 side and a signal is output from the drive board 4 side. Conversely, a signal is input from the drive board 4 side and from the drive board 3 side. A signal may be output.

  The control unit 5 outputs the aforementioned input command CMDIN, input clock CLKIN, and data DATAIN. The control unit 5 includes a command register 51, a clock generator 52, and a data register 53.

  The command register 51 stores various input commands CMDIN. The clock generator 52 generates the input clock CLKIN.

  The data register 53 stores drive voltage pattern data constituting the data DATAIN. This pattern data differs depending on the detection method, and is prepared for each driver IC 6. For example, when a driving voltage is applied to a specific transparent electrode Eh and a touch input to the touch panel 2 is detected from the transparent electrode Ev, data of a pattern configured to apply the driving voltage only to the specific transparent electrode Eh. Is used as pattern data. That is, pattern data for supplying a driving voltage to the transparent electrode Eh and pattern data for supplying a driving voltage to the transparent electrode Ev are prepared. Data DATAIN is formed by sequentially outputting the pattern data for each driver IC 6 to be serial data.

  Further, the data register 53 receives the data DATAOUT output from the last driver IC 6 in the drive substrate 4 and the return clock CLKRTN output from the driver IC 6. The data register 53 reads and stores the data DATAOUT at the timing of the return clock CLKRTN.

  The writing of the pattern data to the data register 53 and the reading of the pattern data from the data register 53 are controlled by the CPU of the device on which the touch panel device 1 is mounted, for example.

  The control unit 5 is configured by a circuit, but may be realized by software using a microcomputer.

  Next, the driver IC 6 will be described.

  The driver IC 6 described below will be described as driving 33 transparent electrodes E.

  As illustrated in FIG. 3, the driver IC 6 includes a reset signal processing unit 100, a clock signal processing unit 200, a command processing unit 300, and a data processing unit 400.

  The reset signal processing unit 100 transmits the input reset signal RESIN within the driver IC 6 and outputs it. The clock signal processing unit 200 transmits the inputted input clock CLKIN in the driver IC 6 and outputs it. The clock signal processor 200 generates a return clock CLKRTN, which will be described later.

  The command processing unit 300 decodes the input command CMDIN and outputs various commands defined by the input command CMDIN as command signals. Further, the command processing unit 300 allows the input command CMDIN executed by the driver IC 6 in the subsequent stage to pass without decoding, and subtracts 1 from an ID specified in an ID setting command SETID (see FIG. 4) described later. Output.

  The data processor 400 shifts the input data DATAIN input to convert it into parallel drive data, applies a drive voltage to each transparent electrode E based on the drive data, and obtains from each transparent electrode E. The detected detection voltage is taken in as parallel detection data and shifted to output serial detection data. Further, the data processing unit 400 outputs the portion used by the other driver IC 6 in the input data DATAIN without shifting.

  Hereinafter, the processing units 100, 200, 300, and 400 will be described in detail.

  The reset signal processing unit 100 includes an input driver 101 and an output driver 102. The input driver 101 is configured as a Schmitt trigger type in order to shape the waveform of the reset signal RESIN input from the outside. The reset signal RESIN is supplied to each required part of the driver IC 6 (for the sake of convenience, detailed reset signal supply wiring is omitted in FIG. 2). The output driver 102 outputs the reset signal RESIN from the input driver 101 to the driver IC 6 at the next stage as the reset signal RESOUT. By providing the input driver 101 in the input stage and providing the output driver 102 in the output stage, the drive capability is enhanced so as to prevent the reset signal RESIN from being attenuated.

  The reset signal RESIN input to the first-stage driver IC 6 is a power-on reset signal generated in the device in which the touch panel device 1 is mounted, a reset signal generated by a user instruction, or the like.

  The clock signal processing unit 200 includes an input driver 201, an output driver 202, and a return clock generation circuit 203 (termination output means).

  The input driver 201 receives the input clock CLKIN and supplies it to required parts of the driver IC 6 (for the sake of convenience, detailed clock signal supply wiring is omitted in FIG. 2). The output driver 202 outputs the input clock CLKIN from the input driver 201 to the next-stage driver IC 6 as the output clock CLKOUT. By providing the input driver 201 in the input stage and providing the output driver 202 in the output stage, the drive capability is enhanced so as to prevent attenuation of the input clock CLKIN.

  The return clock generation circuit 203 includes a flip-flop 204, an AND gate 205, an OR gate 206, and an output driver 207.

  The return clock generation circuit 203 generates the return clock CLKRTN described above. The return clock CLKRTN output from the driver IC 6 at the final stage among the driver ICs 6 connected in a daisy chain is sent to the control unit 5 via the wiring W6. The control unit 5 can grasp the state of a series of driver ICs 6 connected in a daisy chain by monitoring the input signal of the return clock CLKRTN. The return clock CLKRTN from the driver IC 6 other than the final stage of the driver IC 6 connected in a daisy chain is not transmitted to the subsequent stage and is not used.

  That is, for example, the following three signals are input via the flip-flop 204 to one input terminal of the AND gate 205 in the return clock generation circuit 203. The first signal is “1” when the value of the ID stored in the ID register 412 is “0” (00000) (that is, when a series of driver ICs 6 connected in a daisy chain are reset). Is a signal. The second signal is an instruction execution signal CMDEX, which will be described later, which becomes an active (High) signal so that a one-pulse clock is output when the input command CMDIN is executed. The third signal is a shift control signal SHIFTFTSTR described later. An input clock CLKIN is input to the other input terminal of the AND gate 205.

  The OR gate 206 receives the ID determination signal and the output of the AND gate 205. The ID discrimination signal is “1” when the upper 4 bits of the ID held in the ID register 412 is (0000) (when the ID value of the final stage driver IC 6 is set correctly), In other cases (when the ID value of the final stage driver IC 6 is set incorrectly), this signal is “0”.

  Thus, when the ID is “0” (00000), the return clock generation circuit 203 outputs a clock having the same phase as the output clock CLKOUT based on the first signal.

  Further, when the ID is 1 (when the ID value of the final stage driver IC 6 is set correctly), the return clock generation circuit 203 performs the above operation at the timing when the input command CMDIN is executed (the timing at which the instruction execution ends). Based on the second signal, a return clock CLKRTN corresponding to one clock (one pulse) synchronized with the input clock CLKIN is output.

  When the ID is 1 and the above-described shift command is executed, the return clock generation circuit 203 generates one pulse for one clock synchronized with the input clock CLKIN based on the second and third signals. Then, a return clock CLKRTN consisting of a clock synchronized with the input CLKIN is output during a period when a shift control signal SHIFTFT, which will be described later, is High. As a result, it can be confirmed that the shift operation has been performed with the previous one pulse, and the return clock CLKRTN is output in the period (shift period) in which the subsequent shift control signal SHIFTSSTR is High, so that the shift control signal When SHIFTFTSTR changes from High to Low and the return clock CLKRTN is not output, it is understood that the shift operation is completed.

  When the ID is 1 and the input command CMDIN is not input to the driver IC 6, the return clock generation circuit 203 outputs a low level based on the second signal. Thereby, it is understood that the input command CMDIN is not given (not executed).

  Further, when the ID is other than the above values (when the ID value of the final stage driver IC 6 is erroneously set), the return clock generation circuit 203 is erroneously set based on the ID determination signal that is “1”. During this time, the High level is output.

  In this way, by using the return clock CLKRTN, the control unit 5 can determine the execution end timing of the instruction, the erroneous ID setting, and the like.

  The command processing unit 300 includes inverters 301 and 302, flip-flops 303 (second flip-flops) and 304, a subtraction circuit 305, a changeover switch 306, a flip-flop 307, a pull-up resistor R, an input driver 308, and the like. , A command buffer 309, a control circuit 310 (shift control means), a barrel register 312, and a shift counter 313.

  Prior to the description of the command processing unit 300, details of the input command CMDIN will be described.

  As shown in FIG. 4, each input command CMDIN is composed of lower 4 bits (OPT0 to OPT3) constituting an opcode and upper 5 bits (OPD0 to OPD4) constituting an operand. The opcode is a part in which an instruction in the input command CMDIN is defined, and the operand is a part in which various parameters in the input command CMDIN are set.

  As the input command CMDIN, as shown in FIG. 4, for example, a reset command RESALL, a drive OFF command DRIVEOFF, a buffer clear command CLRBUF, a buffer drive command DRIVEBUF, an all drive command DRIVEALL, a latch command LATCHTOUCH, a first shift command SHIFTF, a first command 2 shift command SHIFTM, shift bit number setting command SETHIFTNO, and ID setting command SETID are prepared.

  The reset command RESALL is a command for executing a function equivalent to the reset signal RESIN in order to reset each part that can be reset, and all bits of the opcode are “0”. When this reset command RESALL is input, the control circuit 310 outputs a reset signal equivalent to the reset signal RESIN.

  The drive OFF command DRIVEOFF resets all of the driver controllers 408 after the driving operation, but does not reset the shift buffer 406 (data shift means, shift necessity determination means). In this drive OFF command DRIVEOFF, only the bit OPT3 is “1”.

  The buffer clear command CLRBUF is a command for resetting the shift buffer 406. In this buffer clear command CLRBUF, only the bit OPT0 is fixed to “1”. The bit OPT3 defines whether the driver IC 6 is on the vertical side (“1”) or the horizontal side (“0”).

  Although not shown, a buffer inversion command INVBUF that inverts the value held in the shift buffer 406 can be configured by using the buffer clear command CLRBUF. Specifically, when used as the buffer clear command CLRBUF, the bit OPD0 in the operand is set to “0”, and when used as the buffer inversion command INVBUF, the bit OPD0 in the operand is set to “1”. The buffer inversion command INVBUF is not used in the driving algorithm described in this embodiment, but it is not necessary to create an inversion value and shift it in the shift buffer 406 in order to obtain an inversion value.

  The buffer drive command DRIVEBUF is a command for driving each line (transparent electrode E) based on the data pattern shifted to the shift buffer 406. The all drive command DRIVEALL is a command for actively driving all lines connected to the driver IC 6 regardless of the output of the shift buffer 406. The buffer drive command DRIVEBUF and all drive commands DRIVEALL are common in that the bit OPD1 in the operand is “1”, but are distinguished by the value of the bit OPD0. In the buffer drive command DRIVEBUF, the bit OPD0 is “1”, and in the all drive command DRIVEALL, the bit OPD0 is “0”. The bit OPT3 defines whether the driver IC 6 is on the vertical side (“1”) or the horizontal side (“0”).

  The latch command LATCHTOUCH is a command for latching (reading) data from all lines to the shift buffer 406. In this latch command LATCHTOUCH, the bits OPT0 and OPT1 are fixed to “1”. The bit OPT3 defines whether the driver IC 6 is on the vertical side (“1”) or the horizontal side (“0”).

  The first shift command SHIFTF is a command for executing the shift operation of the shift buffer 406 without using the above-described multiple value set in the barrel register 312. In the first shift command SHIFTF, as described above, the number of shifts when the number of bits of shift in the shift buffer 406 is 31 or less is defined by 5 bits of the operand.

  The second shift command SHIFTM is a command for executing the shift operation of the shift buffer 406 using the above-described multiple value set in the barrel register 312. In the second shift command SHIFTM, as described above, the number of shifts in the shift buffer 406 where the number of shift bits is 31 or less is defined by 5 bits of the operand.

  The shift bit number setting command SETSHIFTNO is a command for setting a multiple value of 32 in the barrel register 312 when the shift bit number in the shift buffer 406 is 32 or more as described above. In the shift bit number setting command SETSHIFTNO, a multiple value is defined by 4 bits of the operand.

  Also in the first shift command SHIFTF, the second shift command SHIFTM, and the shift bit number setting command SETSHIFTIFNO, it is defined whether the driver IC 6 is the vertical side (“1”) or the horizontal side (“0”) in the bit OPT3. Is done.

  The ID setting command SETID is a command for setting each ID. As described above, the ID setting command SETID has an operand that specifies the maximum ID value set in the first driver IC 6 in the daisy chain connection. This operand is set so that the ID of the last driver IC 6 becomes 1 as a result of sequentially subtracting the ID set for the second driver IC 6. The operation code uses three bits OPT0 to OPT2.

  As shown in FIG. 5, the input command CMDIN (basic command) is configured in the same manner as serial data used in normal serial communication. Specifically, the input command CMDIN has a low-level start bit at the beginning, and the value of 9 bits (OPT0 to OPT3, OPD0 to OPD4) (low active) continues in synchronization with the input clock CLK. Is transmitted. The input command CMDIN is a command sequence when a plurality of basic commands are configured in a sequence.

  The shift operation of the input data DATAIN by the shift buffer 406 is simultaneously performed in the driver IC 6 on either the drive substrate 3 or the drive substrate 4. For this reason, for example, when the shift operation is performed by the driver IC 6 on the drive substrate 3, the shift operation is not performed on the driver IC 6 on the drive substrate 4. Therefore, in this case, in the input command CMDIN which is a command string, each bit of the operand in the basic command given to the driver IC 6 of the driving board 4 is set to 0. As a result, the number of shift lines becomes zero, and the shift operation in the shift buffer 406 is not performed. Conversely, when a shift operation is performed in the driver IC 6 on the drive board 4, each bit of the operand in the basic command given to the driver IC 6 on the drive board 3 is set to 0 for the input command CMDIN.

  Next, the command processing unit 300 will be described.

  The flip-flop 303 takes in the input command CMDIN inverted by the inverter 301 at the timing of the input clock CLKIN. The flip-flop 303 holds the input command CMDIN at the falling timing in order to avoid the racing phenomenon.

  The subtraction circuit 305 subtracts “1” from the operation code in the setting command SETID and outputs the result. When the flip-flop 304 generates a borrow (digit reduction) as a result of the subtraction by the subtraction circuit 305, the flip-flop 304 holds the borrow. Then, the flip-flop 304 gives the held borrow to the subtraction circuit 305 for the carry-down operation. The subtractor 305 and the flip-flop 304 constitute a serial subtractor.

  The changeover switch 306 selects and outputs one of the input command CMDIN output from the flip-flop 303 and the input command CMDIN output from the subtraction circuit 305. Specifically, the changeover switch 306 connects the output terminal to the flip-flop 303 when the changeover control signal output from the control circuit 310 is “0”, and when the changeover control signal is “1”. The output terminal is connected to the subtraction circuit 305.

  The flip-flop 307 holds the input command CMDIN from the changeover switch 306 in synchronization with the input clock CLKIN. The inverter 302 inverts the input command CMDIN from the flip-flop 307 and outputs it as an output command CMDOUT to the driver IC 6 at the next stage.

  Here, the horizontal / vertical discrimination signal H / V is input to the driver IC 6. The horizontal / vertical discrimination signal H / V indicates that the driver IC 6 is disposed in the vertical direction on the drive substrate 3 by “1”, and “0” indicates that the driver IC 6 is disposed in the horizontal direction on the drive substrate 4. ". The input terminal of the horizontal / vertical discrimination signal H / V is connected to the input terminal of the input driver 308, but is pulled up by a resistor R in order to drive at the CMOS level.

  The command buffer 309 temporarily holds the 9-bit input command CMDIN that has passed through the flip-flop 303.

  The control circuit 310 receives a High signal obtained by decoding a 4-bit opcode included in the input command CMDIN held in the command buffer 309 and an instruction execution signal CMDEX output from an equal comparator 414 described later. ) And an effective command signal are output to each required part.

  Specifically, when the input command CMDIN is the aforementioned buffer clear command CLRBUF, the control circuit 310 outputs a buffer clear signal CBUF (High level) as an instruction signal. Further, when the input command CMDIN is the above-described all drive command DRIVEALL, the control circuit 310 outputs the all drive signal DALL (Low level) as a command signal. Further, when the input command CMDIN is the above-described drive OFF command DRIVEOFF, the control circuit 310 outputs a drive OFF signal DOFF (High level) as a command signal. Further, when the input command CMDIN is the above-described buffer drive command DRIVEBUF, the control circuit 310 outputs the buffer drive signal DBUF (High level) as an instruction signal. Further, when the input command CMDIN is the aforementioned latch command LATCHTOUCH, the control circuit 310 outputs the latch signal LOUT (High level) as a command signal. Further, when the input command CMDIN is the first shift command SHIFTF or the second shift command SHIFTM, the control circuit 310 outputs a shift instruction signal SHIFT (High level) as an instruction signal.

  In addition, the control circuit 310 is based on the horizontal / vertical discrimination signal H / V input via the input driver 308, and whether its own driver IC 6 is arranged in the horizontal direction or the vertical direction. Is determined.

  Further, the control circuit 310 determines whether or not the input command CMDIN is an ID setting command SETID. According to the result, the control circuit 310 outputs a switching control signal of “1” when the input command CMDIN is the ID setting command SETID, while it is “0” when the input command CMDIN is not the ID setting command SETID. A switching control signal is output. This switching control signal is also used as an ID load signal for loading the ID into the ID register 412.

  The control circuit 310 outputs a counter control signal for starting a count operation of a wait counter 413 described later. For this reason, the control circuit 310 determines whether or not the input command CMDIN is a command other than the ID setting command SETID from the result of decoding the operation code of the input command CMDIN written in the command buffer 309. Thereby, when the control circuit 310 recognizes that the written input command CMDIN is a command other than the ID setting command SETID, the control circuit 310 determines that the input command CMDIN to be executed is written in the command buffer 309, and The counter control signal is changed to active (High).

  The control circuit 310 also includes horizontal / vertical discrimination bits included in buffer control commands (CLRBUF, DRIVEBUF / DRIVER, SHIFTF, SHIFTM, SETSHIFTIF, LATCHTOUCH) relating to control of the shift buffer 406, and horizontal / vertical discrimination signals H / The value of V is compared to determine whether they match. In the buffer control system command and the latch command LATCHTOUCH, the most significant bit OPT3 (see FIG. 4) in the operation code defines whether the driver IC 6 is vertical (“1”) or horizontal (“0”). ing.

  The control circuit 310 outputs a shift control signal SHIFTFTSTR for causing the shift buffer 406 to perform a shift operation. The shift control signal SHIFTTSTR becomes High when both the shift command signal SHIFT and the command execution signal CMDEXE described above become High, and becomes Low when a count value from a load value of a shift counter 313 described later becomes 0.

  The control circuit 310 outputs a select signal for controlling switching of a selector 407 (direct output means) described later. Specifically, the control circuit 310 performs “0” when the above two match and “1” when they do not match (obtained by the exclusive OR gate) and instruction execution. It has an RS flip-flop (not shown) that is set by the logical product of the signal CMDEX and reset by the logical product of the inverted signal of the coincidence determination signal and the instruction execution signal CMDEXE. The control circuit 310 uses the RS flip-flop to match the determination bit with the horizontal and vertical determination signal H / V and the instruction execution signal CMDEX becomes active. A select signal that remains High until the value of the vertical discrimination signal H / V does not match and the instruction execution signal CMDEX becomes active next time is output.

  The number of bits for shifting input data DATAIN in a shift buffer 406, which will be described later, is set by the first shift command SHIFTF described above. The first shift command SHIFTF represents the number of bits by a 5-bit operand. Therefore, if the number of bits is 31 or less, the first shift command SHIFTF can define a shift operation according to the number of bits.

  However, when the number of bits for shifting the input data DATAIN exceeds 31, the above-mentioned 5-bit operand cannot define the shift operation. Therefore, when the number of bits to be shifted exceeds 31, a multiple value (n) for multiplying 32 by an integer is defined in advance, and 32 × n and the second shift command SHIFTM that defines the number of bits of 31 or less are used. , Represents a bit number of 32 or more. As a result, even with a 5-bit operand, the number of bits of 32 or more can be defined.

  The barrel register 312 is provided to store the above multiple value. The multiple value is expressed by using the 4 bits of the operand in the above-described shift bit number setting command SETSHIFTIF. The barrel register 312 includes, for example, a D latch, and holds a 4-bit value corresponding to each of the horizontal driver IC 6 and the vertical driver IC 6. The multiple value for the horizontal or vertical driver IC 6 stored in the barrel register 312 is output to the shift counter 313.

  The barrel register 312 temporarily holds 4 bits (multiple value) of the operand in the shift bit number setting command SETSHIFTNO among the 5-bit operands output from the command buffer 309.

  The shift counter 313 includes the operand (5 bits) in the first shift command SHIFTM from the command buffer 309 or the multiple value n (4 bits) from the barrel register 312 and the operand in the second shift command SHIFTM. (5 bits) is input as a preset value. The shift counter 313 is a down counter that counts down the input clock CLKIN from the loaded preset value to 0 during the period when the shift control signal SHIFTSSTR is High. The shift counter 313 may be an up counter.

  Here, as will be described later, the shift operation of the input data DATAIN in the shift buffer 406 is performed during the period in which the shift control signal SHIFTSSTR is High. Thus, the number of bits to be shifted by the shift buffer 406 is defined according to the preset value loaded into the shift counter 313.

  The data processing unit 400 includes an input driver 401, an output driver 402, flip-flops 403 to 405, a shift buffer 406, a selector 407, a driver controller 408, an output driver 409, an input driver 410, and a noise filter 411. An ID register 412 (), a wait counter 413, and an equal comparator 414.

  The flip-flop 403 (first flip-flop) takes in the input data DATAIN input via the input driver 401 at the timing of the input clock CLKIN. The flip-flop 403 holds the input data DATAIN at the falling timing in order to avoid the racing phenomenon. The flip-flop 404 holds the input data DATAIN from the flip-flop 403 in synchronization with the input clock CLKIN.

  The shift buffer 406 shifts the input data DATAIN input through the flip-flop 403 bit by bit in synchronization with the input clock CLKIN up to a specified number of bits, and holds and outputs the data as parallel data. The number of bits is defined by the operand value of the first shift command SHIFTF developed in the command buffer 309 when it is 31 bits or less, and the second shift developed in the command buffer 309 when it is 32 bits or more. It is defined by the operand value (9 bits) of the command SHIFTM and the shift bit number setting command SETSHIFTIF. Thereby, the shift buffer 406 can shift the input data DATAIN by a desired number of bits and convert a necessary portion of the input data DATAIN into parallel data.

  Further, the shift buffer 406 takes in parallel data (detection data) acquired from each 33-bit transparent electrode E output from a noise filter 411 described later when the latch signal LOUT becomes active (High). The shift buffer 406 outputs the received data as serial data by shifting the fetched data bit by bit as defined above in synchronization with the input clock CLKIN.

  Further, the shift buffer 406 performs a shift operation when the above-described shift control signal SHIFTFTSTR becomes valid (High) when the input command CMDIN is a shift-related command related to shift (the above-mentioned SHIFTF, SHIFTM, SETSHIFTNO). , The start of the shift is delayed by the number of clocks of the input clock CLKIN specified by the ID. The shift buffer 406 is reset when the above-described buffer clear signal CBUF becomes valid and stops outputting.

  The ID register 412 stores a part (5-bit operand) in which an ID is set in the ID setting command SETID held in the command buffer 309. The ID register 412 is constituted by, for example, a D latch, and writes the above 5-bit data by an ID load signal from the control circuit 310.

  The wait counter 413 counts the input clock CLKIN from 0 and outputs a count value. The wait counter 413 starts counting when the counter control signal output from the control circuit 310 becomes active.

  The equal comparator 414 compares the ID from the ID register 412 with the count value from the wait counter 413, and outputs a High level instruction execution signal CMDEXE if they match. When this instruction execution signal CMDEXE becomes High level, each of the above-described instruction signals from the control circuit 310 becomes valid, and commands other than the ID setting command SETID are executed. Since the count value of the wait counter 413 changes at the timing of one clock of the input clock CLKIN, the instruction execution signal CMDEX is High only for one clock period.

  The shift buffer 406 starts a shift operation in response to the shift command signal SHIFTFTSTR among the above command signals. Thereby, the shift buffer 406 can delay the start of the shift operation according to the value of the ID.

  The selector 407 selects and outputs one of the input data DATAIN output from the flip-flop 404 and the input data command CMDIN output from the shift buffer 406. Specifically, the selector 407 uses the output terminal of the shift buffer 406 as an output driver when the select signal output from the control circuit 310 is “1”, that is, when the above-described buffer control command is executed. Connect to 402. On the other hand, the selector 407 connects the output terminal of the flip-flop 404 to the output driver 402 when the select signal is “0”, that is, when the buffer control command and the latch command LATCHTOUCH are not executed.

  The driver controller 408 outputs a driving signal of “0” when a driving voltage is applied to the transparent electrode E, and outputs a driving signal of “1” when a driving voltage is not applied to the transparent electrode E. Such a driver controller 408 is configured by a logic circuit. The driver controller 408 controls the operation of the output driver 409 based on the above-described various command signals output from the control circuit 310 in response to drive commands (DRIVEOFF, DRIVEBUF, DRIVEALL). Specifically, when all the drive signals DALL are valid (Low level = “0”), the driver controller 408 connects “0” of all the drive signals DALL to the driver IC 6 regardless of the output of the shift buffer 406. Is output as a drive signal to the all transparent electrode E. Further, when the buffer drive signal DBUF is valid, the driver controller 408 outputs each bit of data from the shift buffer 406 as a drive signal to the corresponding transparent electrode E. Further, the driver controller 408 stops outputting data (“0” or “1”) from the shift buffer 406 when the drive OFF signal DOFF becomes valid.

  The output driver 409 applies a drive voltage to the transparent electrode E and stops the application based on a drive signal from the driver controller 408. Specifically, the output driver 409 has the same number of transistor circuits connected between the transparent electrode E and the ground as the number of transparent electrodes E connected to the driver IC 6, and the output driver is connected to the gate of each transistor circuit. A corresponding drive signal from 409 is input. Further, a power supply voltage is applied between each transparent electrode E and the transistor circuit via a resistor. Thus, when the drive signal “0” is output, the transistor circuit is turned off, so that the power supply voltage is applied as the drive voltage to the transparent electrode E, and when the drive signal “1” is output, the transistor circuit Is turned on, the drive voltage is not applied to the transparent electrode E.

  The input driver 410 also has an inverter function, and inverts and outputs the detection voltage from the transparent electrode E. Similarly to the output driver 409, the input driver 410 is also provided for each of the transparent electrodes E connected to the driver IC 6.

  The detection voltage from each transparent electrode E from the input driver 410 is input to the shift buffer 406 after the noise is removed by the noise filter 411 as parallel data.

  The noise filter 411 includes a shift register in which a plurality of D flip-flops are connected in series in a plurality of stages to shift input data, and a majority circuit that takes a majority vote of the output of each stage in the shift register. The noise filter 411 outputs “0” when the majority circuit determines that the output of each stage of the shift register is “0” continuously, and outputs the predetermined number of outputs of each stage of the shift register. If it is determined that it is “1”, the output data “1” is output to remove noise of the input data.

  The drive operation of the touch panel 2 in the touch panel device 1 configured as described above will be described.

  First, in the touch panel device 1 described below, nine driver ICs 6 are provided, the drive substrate 3 mounts four driver ICs 6, and the drive substrate 4 mounts five driver ICs 6. In FIG. 1 and FIG. 2, illustration of some driver ICs 6 is omitted for convenience.

  When a device on which the touch panel device 1 is mounted is turned on or reset by a reset operation after activation, a reset signal RESIN is input to the touch panel device 1. When the reset signal RESIN is input to the first driver IC 6 via the wiring W4 in the drive substrate 3, the reset signal RESIN is sequentially transmitted to the subsequent driver IC 6 via the driver IC 6. As a result, each driver IC 6 is reset. The driver IC 6 at the final stage does not output the reset signal RESOUT because the output terminal of the reset signal RESOUT is not connected.

  The reset operation is also performed by executing the reset command RESALL of the input command CMDIN.

  Further, when the input clock CLKIN is output from the clock generator 52 of the control unit 5, like the reset signal RESIN, the input clock CLKIN is input to the driver IC 6 at the first stage via the wiring W3 on the drive substrate 3, and the subsequent driver IC 6 Are transmitted sequentially. The output clock CLKOUT output from each driver IC 6 is input as the input clock CLKIN to the driver IC 6 at the next stage. Thereby, each driver IC 6 operates based on the input clock CLKIN. The driver IC 6 at the final stage does not output the output clock CLKOUT because the output terminal of the output clock CLKOUT is not connected, but instead outputs the return clock CLKRTN to the control unit 5 via the wiring W6.

  After the reset, the input command CMDIN is output from the command register 51 of the control unit 5 according to an instruction from the external CPU. The input command CMDIN passes through the flip-flop 307 in each driver IC 6 and is transmitted to the driver IC 6 in the next stage while being delayed by one clock of the input clock CLKIN.

  When the system is started, first, the ID setting command SETID is output as the input command CMDIN. Since the touch panel device 1 described here has nine driver ICs 6, the maximum ID value set in the operand in the ID setting command SETID is “9” (01001).

  When this ID setting command SETID is inverted and input to the driver IC 6 at the first stage by the inverter 301, it is once input to the command buffer 309, and is operated as an operand by a serial subtractor comprising the flip-flop 303 and the subtracting circuit 305. 1 is subtracted from The ID setting command SETID held in the command buffer 309 is decoded by the control circuit 310. Then, the control circuit 310 determines that the input command CMDIN is the ID setting command SETID. At this time, the operand of the ID setting command SETID held in the command buffer 309 is written to the ID register 412 by the load signal (“1”) output from the control circuit 310, so that the ID is assigned to the driver IC 6. Is set.

  Further, the switching control signal output from the control circuit 310 is switched from “0” to “1” by the above determination. As a result, the ID setting command SETID obtained by subtracting 1 from the operand (ID value) by the serial subtractor is output via the changeover switch 306, the flip-flop 307, and the inverter 302. As a result, the ID setting command SETID is output as the output command CMDOUT to the driver IC 6 at the next stage. When the ID setting command SETID is input as the input command CMDIN, the driver IC 6 at the next stage also sets the ID as described above and performs subtraction (−1) of the ID. By performing such processing in each driver IC 6 in the same manner, an ID that is decreased by one from the first stage is set in each driver IC 6. As a result, the ID set in the last-stage driver IC 6 becomes “1”.

  When an ID is set for each driver IC 6 in this way, each driver IC 6 can execute an input command CMDIN other than the ID setting command SETID. Since the serial input command CMDIN is delayed by one clock of the input clock CLKIN by the flip-flop 307 in each driver IC6, there is a time difference to reach each driver IC6 to be executed. Therefore, after the input command CMDIN reaches the final stage driver IC 6, the input command CMDIN is executed in all the driver ICs 6. At this time, in each driver IC 6, when the ID set in the ID register 412 matches the number of clocks of the input clock CLKIN counted by the wait counter 413, a high instruction execution signal CMDEXE is output from the equal comparator 414. Is done. Thereby, all the driver ICs 6 simultaneously execute the input command CMDIN based on the instruction execution signal CMDEXE.

  Next, the application of the drive voltage to the transparent electrode E and the detection of the drive voltage from the transparent electrode E using the input command CMDIN will be described.

  First, in order to apply a drive voltage, a buffer drive command DRIVEBUF or an all drive command DRIVEALL, which is a drive command, is used. Further, when a buffer drive command DRIVEBUF for performing electrode driving using the shift buffer 406 is executed, a shift command is used. When the number of shift bits is 31 or less, the first shift command SHIFTF is used, and when the number of shift bits is 32 or more, the second shift command SHIFTM and the shift bit number setting command SETSHIFTIFNO are used.

  When the control circuit 310 determines that the input command CMDIN is the first shift command SHIFTF based on the operation code, the operand of the first shift command SHIFTF is loaded into the shift counter 313. Further, the shift control signal SHIFTFT output from the control circuit 310 reaches 0 when the shift counter 313 counts up the input clock CLKIN to the value of the loaded operand or counts down the value of the loaded operand. , Low. As a result, the shift operation of the shift buffer 406 performed during the period in which the shift control signal SHIFTFTSTR is High is stopped.

  On the other hand, the input data DATAIN input to the driver IC 6 is input from the flip-flop 403 to the shift buffer 406 bit by bit in synchronization with the input clock CLKIN. In the shift buffer 406, the input data DATAIN input is shifted bit by bit in synchronization with the input clock CLKIN. When the shift operation of the shift buffer 406 is stopped as described above, the value of the input data DATAIN at that time is held.

  When the buffer IC command is not executed by the driver IC 6, the input data DATAIN is output as transmission data DATAIN through the selector 407 and the output driver 402 with the flip-flop 404 delayed by one clock of the input clock CLKIN. The As a result, it is not necessary to shift by the driver IC 6, and the input data DATAIN shifted by the driver IC 6 in the subsequent stage does not pass through the shift buffer 406 of the driver IC 6 and is transmitted as the transmission data DATAIN in the next stage driver IC 6. Is input as input data DATAIN. For example, when data is shifted by each driver IC 6 on the driving substrate 3 while data is not shifted by each driver IC 6 on the driving substrate 4, the input data DATAIN shifts each driver IC 6 on the driving substrate 3, In the substrate 4, each driver IC 6 only bypasses the shift buffer 406 and passes through the driver IC 6. That is, a series of shift registers in the vertical direction and a series of shift registers in the horizontal direction are formed by a plurality of driver ICs 6 existing on each of the drive board 3 (vertical direction) and the drive board 4 (horizontal direction). Therefore, as described above, the data shifted in the vertical direction passes only through the flip-flop 404 without being shifted in the horizontal direction. In this manner, data shifts among the plurality of driver ICs 6.

  In this way, the input data DATAIN is transmitted at high speed without being shifted by each passing driver IC 6 (without increasing the number of shifts unnecessarily) until it is input to the shifted driver IC 6.

  On the other hand, when the control circuit 310 determines that the input command CMDIN is the second shift command SHIFTM based on the operation code, a 9-bit value consisting of the shift bit number setting command SETSHIFTIFNO and the operand of the second shift command SHIFTM is obtained. The data is loaded into the shift counter 313. Then, the shift operation of the shift buffer 406 is stopped while being performed while the count operation by the shift counter 313 is performed in the same manner as described above. As a result, the shift buffer 406 stops shifting the input data DATAIN and holds the value at that time.

  Thus, when the number of shift bits is 31 or less, the number of shift bits can be defined by the 5-bit operand of the first shift command SHIFTF. When the number of shift bits is 32 or more, the operand of the shift bit number setting command SETSHIFTIFNO defines an integer multiple of 32 bits. Therefore, this and the second shift command SHIFTM that defines the shift bit number of 31 or less are used. By combining with the operand, the number of shift bits of 32 bits or more can be defined. As a result, the number of shift bits of 32 bits or more can be specified within the specified number of bits of the input command CMDIN without increasing the operand to 6 bits or more.

  In this state, the buffer drive command DRIVEBUF is subsequently input to the driver IC 6. Then, the command buffer 309 generates a buffer drive signal DBUF (High level) by decoding the buffer drive command DRIVEBUF. In the shift buffer 406, the value of each bit held as described above is output to the driver controller 408 by the buffer drive signal DBUF.

  Then, the driver controller 408 receives the buffer drive signal DBUF, and outputs the value of each bit output from the shift buffer 406 to the control terminal of the output driver 409. As a result, when the value of the output bit is “0”, the output driver 409 is turned off, so that the power supply voltage is applied to the transparent electrode E as the drive voltage. Further, when the value of the output bit is “1”, the output driver 409 is turned on, so that the power supply voltage is not applied to the transparent electrode E.

  As described above, when the buffer drive command DRIVEBUF is used, a desired bit of the serial input data DATAIN is held in the shift buffer 406, and the application of the power supply voltage to the transparent electrode E or the Non-application is performed.

  Further, when the all drive command DRIVEALL is executed, it is not necessary to shift the input data DATAIN by the shift buffer 406, so that a shift command is not required. When the all drive command DRIVEALL is input to the driver IC 6, the command buffer 309 decodes the command to generate an all drive signal DALL (High level).

  Then, in response to the all drive signal DALL, the driver controller 408 outputs all bit values (“0”) output from the shift buffer 406 to the control terminal of the output driver 409. Thereby, the power supply voltage is applied to all the transparent electrodes E connected to the driver IC 6 as a drive voltage.

  By performing such processing simultaneously on all the driver ICs 6 on the drive substrate 3, all the transparent electrodes Eh are driven. Then, since the transparent electrode Ev corresponding to the touched position on the touch panel 2 is electrically connected to the corresponding transparent electrode Eh at the position, a detection voltage appears on the electrode Ev. At this time, reading of the touch position is performed by all the driver ICs 6 on the drive substrate 4.

  A latch command LATCHTOUCH is used to detect the drive voltage. When the control circuit 310 determines that the input command CMDIN is the latch command LATCHTOUCH based on the operation code, the latch signal LOUT (High level) is supplied to the shift buffer 406. Then, the state (“0” or “1”) of the detection voltage appearing on each transparent electrode E is captured and held in the shift buffer 406 via the inverter 410 and the noise filter 411 as detection data. This is performed simultaneously for all of the driver ICs 6 for which the latch command LATCHTOUCH is executed.

  The data held in the shift buffer 406 of each driver IC 6 is output after being shifted from the shift buffer 406 when a shift command is given to each driver IC 6 and held in the shift buffer 406 of the driver IC 6 in the next stage. The data is shifted following the existing data. In this way, the data held in each shift buffer 406 is serially connected serially by shifting the data between the plurality of driver ICs 6. Therefore, serial output data DATAOUT is output from the driver IC 6 at the final stage.

  Further, when an input command CMDIN other than the ID setting command SETID and the shift command is executed from the last stage driver IC 6, a return clock CLKRTN of only one clock is output for each input command CMDIN. The output data DATAOUT is read into the data register 53 of the control unit 5 via the level shifter 7 in synchronization with the return clock CLKRTN. Thus, since the output clock CLKOUT that is delayed by the transmission of each driver IC 6 is not used, the output data DATAOUT can be read at an appropriate timing.

  In the above example, the drive voltage is applied by the vertical driver IC 6 and the drive voltage is detected by the horizontal driver IC 6, but the reverse is also performed.

  As described above, in the touch panel device 1 according to the present embodiment, the adjacent driver ICs 6 are connected in a daisy chain via the wirings W1 to W4, so that various signals passing through the driver IC 6 are delayed. .

  Even if the reset signal RESIN is delayed, if it is transmitted to each driver IC 6, resetting is performed, so there is no problem. However, when the input clock CLKIN reaches the final stage driver IC 6, delays in the respective driver ICs 6 accumulate, so that a large phase difference is generated from the time when the input clock CLKIN is output from the control unit 5. Therefore, it is possible to avoid malfunction by detecting the completion of the shift by the return clock CLKRTN.

  In each driver IC 6, the serial data is shifted and serial / parallel converted by the shift buffer 406, and the captured parallel data is shifted and serial / parallel converted. On the other hand, data that does not need to be shifted by each driver IC 6 is output via the selector 407. Thereby, a delay in data transmission time can be suppressed.

  The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope shown in the claims. That is, embodiments obtained by combining technical means appropriately modified within the scope of the claims are also included in the technical scope of the present invention.

  The touch panel device according to the present invention sequentially transmits signals transmitted between a plurality of driver ICs mounted on the driving substrate via the daisy chain-connected wirings. Therefore, one line for transmitting each signal is provided. Since the wirings can be provided on one side of the driving substrate by forming the wirings so as not to cross each other, the cost can be reduced by using a driving substrate with a simple structure. It can utilize suitably for the apparatus which mounts.

1 Touch Panel Device 2 Touch Panel (Matrix Touch Panel)
3, 4 Drive board 5 Control unit 6 Driver IC (Drive integrated circuit)
203 Return clock generation circuit (termination output means)
310 Control circuit (shift control means)
303 flip-flop (second flip-flop)
403 flip-flop (first flip-flop)
406 Shift buffer (data shift means, shift necessity determination means)
407 Selector (direct output means)
CLKIN input clock (clock)
CLKRTN Return clock (Termination signal)
CMDIN input command (command data)
DATAIN input data (drive data)
DATAINOUT output data (detection data)
DATANEXT transmission data (drive data, detection data)
Eh Transparent electrode (first electrode, second electrode)
Ev Transparent electrode (first electrode, second electrode)
E Transparent electrodes W1 to W6 Wiring

Claims (6)

A driving integrated circuit that applies a driving voltage to a plurality of first electrodes in a matrix type touch panel based on driving data, and outputs a detection voltage for detecting a touch from a plurality of second electrodes intersecting the first electrode as detection data. A touch panel drive device comprising a plurality of
Each driving integrated circuit is daisy chained,
The drive data to the plurality of first electrodes is serially configured by shifting the drive data to be converted to parallel and output to each first electrode, and from the plurality of second electrodes A data shift means for converting the detection data in parallel into serial data by shifting the detection data obtained in parallel;
Shift control means for starting a shift operation of the drive data and the detection data by the data shift means by executing a command defined by command data given from outside;
The drive data, the detection data, and the command data are in a serial format continuous for each of the drive integrated circuits, and are transmitted to each of the drive integrated circuits connected in a daisy chain together with a clock. Drive device. Each driving integrated circuit
Shift necessity determination means for determining whether to shift the drive data and the detection data by the data shift means;
And a direct output means for directly outputting the input drive data and the detection data through a path that does not pass through the data shift means when the shift necessity determination means determines NO. The touch panel drive device according to claim 1. Each driving integrated circuit is set with a unique ID,
In the final stage driving integrated circuit, when the ID is a final value representing the final stage driving integrated circuit and the command is a shift command for executing a shift operation by the data shift means, the ID is When the command is a command other than the shift command, the ID is the final value, and when the command data is not given, when the ID is 0, the ID is the final value. The touch panel drive device according to claim 1, further comprising termination output means for outputting a termination signal for discriminating each of the termination signals when the value is other than 0.   4. The touch panel driving device according to claim 3, wherein the termination output means outputs the termination signal immediately before the detection data is shifted by the data shift means when the detection data is output.   The integrated circuit for driving includes a first flip-flop that captures the drive data and the detection data, and a second flip-flop that captures the command data, and the first and second flip-flops fall at the falling edge of the clock. The touch panel drive device according to claim 1, wherein the capturing operation is performed in synchronization. A touch panel device comprising a matrix type touch panel and a touch panel drive device for driving the matrix type touch panel,
The touch panel drive device is the touch panel drive device according to any one of claims 1 to 5.

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