JPH05274084A - Display-integrated tablet - Google Patents

Abstract

PURPOSE:To obtain a display-integrated tablet with a short X-coordinate detection period, a simplified circuit, and high detection accuracy for X-coordinate. CONSTITUTION:In a coordinate detection period, a serial input/output terminal functions as a shift data input/output terminal, and shift data inputted from a serial input terminal E101 is shifted as outputting in series to a serial output terminal E102 by a shift register 27, and a driving signal based on the shift data shifted by the shift register 27 is outputted sequentially by an LCD driver 25. Therefore, a scanning process can be simplified, and the coordinate detection period can be shortened. The detection accuracy of the X-coordinate can be heightened by setting the pulse width of the shift data higher than the cycle of a clock signal. Also, it is possible to dispense with a chip select setting circuit, etc., which simplifies a circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display-integrated tablet used in personal computers, word processors and the like.

[0002]

2. Description of the Related Art As a means for inputting handwritten characters and figures into a computer, a word processor, etc., for example, a liquid crystal display and an electrostatic induction type tablet are combined,
Characters and figures to be input to the electrostatic induction type tablet have been put into practical use so that they can be input as if they were written on paper with a writing instrument and displayed on a liquid crystal display. However, in this electrostatic induction type tablet, since the reflectance and the transmittance are different between the portion with the electrode and the portion without the electrode, the electrodes can be seen in a grid pattern on the display screen, which causes the quality of the liquid crystal display to deteriorate. ..

Therefore, the present inventor has recently proposed a display-integrated tablet as shown in FIG. 7 as a tablet without such drawbacks. In this display-integrated tablet, the display electrodes of the liquid crystal display also serve as coordinate detection (also referred to as position detection) electrodes, and as shown in FIG. 8, coordinate detection and display are performed in a time-division manner within one frame. It is a thing. In FIG. 7, the liquid crystal panel 1 is configured by interposing a liquid crystal layer between the common electrodes Y (Y _{1 to} Yn) and the segment electrodes X (X _{1 to} Xm) arranged in the direction intersecting with each other. The liquid crystal layer at the intersection of the common electrode Y and the segment electrode X constitutes each pixel. That is, here
Pixels of n × m dots are arranged in a matrix. This display-integrated tablet has the advantage that the grid-like electrode pattern is eliminated and it is easier to see, compared to the tablet placed on the liquid crystal display described above. There is an advantage that it is easy to reduce the size and weight.
Common drive circuit 2 for driving the common electrode Y
And the segment drive circuit 3 for driving the segment electrodes X, the display control circuit 5 via the switching circuit 4.
Is connected to the position detection control circuit 6. The switching circuit 4 is controlled by the control circuit 7, outputs the output from the display control circuit 5 to the drive circuits 2 and 3 during the display period, and outputs the output from the position detection control circuit 6 during the coordinate detection period. , 3 is output.

During the display period, the display control circuit 5 outputs the shift data S from the output terminal S, the inverted signal FR from the output terminal FR, and the clock CP from the clock output terminal CP1.
1 from the clock output terminal CP2 to the clock CP2,
The display data D0 to D3 are output from the data output terminals D0 to D3, respectively. The clock CP1 is a clock having a scanning period for scanning pixels for one row as a cycle, and from the output terminal CP10 of the switching circuit 4 to the clock input terminal CK of the common drive circuit 2 and the latch pulse input terminal LP of the segment drive circuit 3. Is entered. In addition, the shift data S
Is a pulse signal for designating each common electrode Y, which is output from the output terminal S0 of the switching circuit 4 and input from the shift data input terminal D101 of the common drive circuit 2 in synchronization with the clock CP1. According to the shift of the shift data S, a drive signal is output to the common electrode Y from the output terminals 01 to n of the common drive circuit 2 corresponding to the shift position. This drive signal is applied to the DC power supply circuit 12
Is generated based on the biases V0 to V5 supplied from The clock CP2 is a clock whose period is a period obtained by dividing a scanning period for scanning pixels for one column into several periods, and is output from the output terminal CP20 of the switching circuit 4 and input to the clock input terminal XCK of the segment drive circuit 3. .. The display data D0 to D3 are output terminals Dou of the switching circuit 4.
output from the input terminal t of the segment drive circuit 3
The data is input to D3 and sequentially captured by the registers in the segment drive circuit 3. Then, when the display data corresponding to the pixels of one row is fetched, these display data are latched at the timing of the clock CP1 input to the latch pulse input terminal LP, and the drive signal corresponding to each display data is segmented. Output from the output terminals 01 to m of the drive circuit 3 to the segment electrode X. This drive signal is also created based on the biases V0 to V5 supplied from the DC power supply circuit 12. The inversion signal FR is a signal for periodically reversing the polarity of the voltage applied to the liquid crystal to prevent deterioration of the liquid crystal due to electrolysis. The common drive circuit 2
The pixels of the liquid crystal panel 1 are driven in the row order by the operation of the segment drive circuit 3, and an image corresponding to the display data is displayed on the liquid crystal panel 1.

On the other hand, during the coordinate detection period, the position detection control circuit 6 outputs the shift data Sd from the output terminal Sd, the inverted signal FRd from the output terminal FRd, and the clock output terminal CP1d.
To clock CP1d, clock output terminal CP2d to clock CP2d, and data output terminals D0 to D3 to output drive data D0d to D3d, respectively. Clock C
P1d is a clock whose period is a scanning period for scanning the common electrode for one row, and which is an output terminal CP of the switching circuit 4.
10 is input to the clock input terminal CK of the common drive circuit 2 and the latch pulse input terminal LP of the segment drive circuit 3. The shift data Sd is a pulse signal for designating each common electrode Y, is output from the output terminal S0 of the switching circuit 4, and is synchronized with the clock CP1d from the shift data input terminal D101 of the common drive circuit 2. Is entered. According to the shift of the shift data Sd, a drive signal is output to the common electrode Y from the output terminals 01 to n of the common drive circuit 2 corresponding to the shift position. This drive signal is generated based on the biases V0 to V5 supplied from the DC power supply circuit 12. Clock CP
2d is a clock for transferring D0d to D3d to the segment drive circuit 3, and an output terminal CP20d of the switching circuit 4
And is input to the clock input terminal XCK of the segment drive circuit 3. The drive data D0 to D3 are output from the output terminal Dout of the switching circuit 4, input to the input terminals D0 to D3 of the segment drive circuit 3, and sequentially captured by the data latch in the segment drive circuit 3. Then, when the drive data corresponding to the segment electrodes X for one row is fetched, these drive data are latched by the line latch at the timing of the clock CP1d input to the latch pulse input terminal LP and correspond to each drive data. The drive signal to be output is the output terminal 01 to
It is output from m to the segment electrode X. This drive signal is also created based on the biases V0 to V5 supplied from the DC power supply circuit 12. The inversion signal FRd is a signal for periodically reversing the polarity of the voltage applied to the liquid crystal to prevent deterioration due to electrolysis of the liquid crystal, but is fixed to or H during the coordinate detection period.

FIG. 9 is a diagram showing drive timing in the coordinate detection period of the display-integrated tablet. The coordinate detection period is divided into an X coordinate detection period and a Y coordinate detection period that follows the X coordinate detection period.
During the Y coordinate detection period, the pulse voltage signal is sequentially applied to the common electrode Y. By applying the pulse voltage signal, a voltage is induced in the detection pen 8 by the stray capacitance between the electrodes X and Y and the position detection pen (hereinafter referred to as detection pen) 8. The induced voltage of the detection pen 8 is the amplifier 9
Is amplified by and input to the X coordinate detection circuit 10 and the Y coordinate detection circuit 11. The X-coordinate detection circuit 10 and the Y-coordinate detection circuit 11 output the output signal from the amplifier 9 and the control circuit 7.
The time until the induced voltage reaches the maximum value is detected on the basis of the timing signal from (3) to detect the X coordinate and the Y coordinate of the position indicated by the detection pen 8, respectively. The detection order of the X coordinate and the Y coordinate may be reversed.

Next, the X coordinate detection scanning in the coordinate detection period, that is, the operation of the segment drive circuit will be described in detail. In FIG. 7, the segment drive circuit 3 is shown as a single block diagram. However, in an actual device, for example, the segment drive LSI 3 shown in FIG. 10 has the configuration of 3 ₁ , 3 ₂ , 3 ₃ ... 3n in FIG. XCK, FR, L
P. D _{0 to} D ₃ , V _{0 to} V _5, etc. are connected to all the LSIs and signals are supplied. Serial input / output terminal E, which is a chip select terminal for input data D _{0 to} D ₃ to each LSI
Chip selection is sequentially performed by IO1 ₁ , EIO1 ₂ , ....

To describe the LSI of FIG. 10 in some detail, the serial input / output terminals EIO1 and EIO2 switch the shift direction depending on the input level of L / R, and are set to either input or output. For example, EIO1 becomes an input when L / R = L and a cascade output when H. See E
IO2 is the opposite of EIO1. Each bit of the shift register 21 has a parallel output function, and this output has a 4 × 20 bit data latch 22 having one gate in units of 4 bits.
Is connected to each gate. Therefore, the display data transferred by the clock XCK is sequentially stored in the data latch 22, and all the 80-bit data is stored in the data latch 22 by the clock of 20 times.
I is in the non-selected state. In this state, the shift data from EIO1 is simultaneously output to the chip select EIO2, and the next LSI is selected by the chip select EIO1 of the next LSI connected in the cascade. The line latch 23 is connected to the level shifter 24 by a bit bus. LP is an input terminal of a latch pulse, and the data of the data latch 22 is line latch 23 at the falling edge.
The contents of the line latch 23 are determined by the level shifter 24 according to the contents of the line latch and the FR signal, and the output terminal OUT1 ...
Output from OUT80 at the same time. At the same time, when the LP drops, the chip select is cleared by the control circuit 26.

In FIG. 11, 101, 102, ... Are multiplexers, and 101 is connected to L as shown in the figure during the display period.
After 102, it is connected to the EIO2 of the preceding LSI. With the initial state by the latch pulse LP, all chip select output terminal EIO2 _1, EIO2 ₂ ... becomes H, in EIO1 _2, EIO1 ₃ ... is H it to connect, 3 ₁
Only the selected state. The data D _{0 to} D ₃ corresponding to the output terminal group 1 are chip-selected by XCK.
The data is transferred to _one data latch 22 and the number of outputs of one chip (80 channels in the LSI of FIG. 10) is sequentially stored in 20 data latches 22 by the shift register 21,
When all (80 bits) has been entered, shift register 2
The output of ₁ is EIO2 _1, the next stage EIO1 ₂ connected to it is also L, the second stage LSI3 ₂ is selected, and the subsequent data is transferred to the second stage LSI3 ₂ and It is stored in the data latch. When the data is stored in the data latch of the final stage LSI 3n by repeating such operations in sequence, LP is applied to all the LSIs.
The data in the data latch of
The voltage corresponding to the signal and the display data is selected by the level shifter, and the voltage is simultaneously output from the output terminal groups OUT1 to OUT80 by the LCD driver and applied to the electrode group connected thereto.

During the coordinate detection period, the multiplexers 101, 102, ... Of FIG. 11 are connected to the separately provided chip select setting circuit 50 instead of the EIO2 in the preceding stage, and E
IO1 is chip-selected by the output of the chip-select setting circuit. FIG. 12 shows scanning timings of the segment electrodes, that is, scanning timings in the X direction in the coordinate detection period according to FIG. In the coordinate detection scan, the contents of the shift register 21 and the line latch 23 are cleared as an initial process, and the scan shown in FIG. 12 is started after a period in which the influence of spike noise due to the alternating display period is not exerted. 12E
During the period T _{01 in} which IO1 ₁ is L, the first-stage LSI is selected, and although not shown, the second-stage, third-stage, ... LSIs are sequentially selected. Here, the case where a in FIG. 9 is 4 and a voltage is simultaneously applied to four select electrodes will be described as an example. In actual application, a is set to about 8-16. Therefore, the same signal is applied to D ₀ d to D ₃ d as shown in FIG. This data is sequentially transferred to the data latch 22 of the first chip-selected LSI 31 ₁ selected by the chip by CP2d, and all the data D ₀ d to D ₃ d between T ₁ are transferred.
Is transferred to the data latch 22, CP1 is applied to the LP terminal.
By applying d, the contents of the data latch are transferred to the line latch, and at the same time, the voltage is applied to the first four electrodes X ₁ X ₂ X ₃ X _{4 from} the drive circuit for the period of T ₂ , and at the same time the contents of the data latch 22 are changed. Cleared. At the next step T ₂ , EIO1 ₁ is set to L by the chip select setting circuit, 3 ₁ is chip selected, and data is still CP2d.
Is transferred to the data latch by CP2.
Transfer is delayed by the period of d, and when the transfer is completed, CP1d
As a result, a voltage is applied to the four electrodes X ₅ X ₆ X ₇ X _{8 from} the drive circuit for a period of T ₃ . This scanning is sequentially repeated thereafter, and when a scanning voltage is applied to all the X electrodes connected to the first LSI at T ₀₁ , the select drive LSI of the next stage 3 ₂ is chip-selected and the same operation is performed during the period of T _02. Scan. The X coordinate detection period ends by applying a voltage to all the segment electrodes by all the segment drive LSIs (3 ₁ 3 ₂ 3 ₃ ... 3n).

The input signal of the chip select is the EIO of the preceding stage.
Instead of 2, the chip select setting circuit supplies EIO2 ₁ to L when all the data enters the data latch at the end of T ₁ as described in the previous display period, and EIO1 ₂ also This is because it becomes L and the LSI 3 ₂ is selected by T ₂ . Therefore, in the coordinate detection period, the chip select setting circuit is provided, and EIO1 ₁ , EIO1 ₂ ...
Is to control.

[0012]

As is apparent from the above description, the L used in the conventional segment drive circuit.
In SI, the operation in the coordinate detection period is the same as the operation in the display period, after storing the input data D0 to D3 in the data latch, it is transferred to the line latch, and a voltage is applied based on the data transferred to the line latch. Therefore, there is a drawback that the X coordinate detection scanning time becomes long. For example, since the common drive circuit has almost the same display scan and coordinate detection scan and the scan is extremely simple, the coordinate detection period is 100 μS or less, whereas the coordinate detection period of the conventional segment drive circuit is complicated as described above. Since it requires a different process, it reaches 400 μS. As the coordinate detection period interrupts during the display period as shown in Fig. 8,
It is desirable that the coordinate detection period is as short as possible, but the X coordinate detection period hinders it. Normally, one frame frequency is selected to be about 72 HZ, so that its cycle is approximately 13.
It becomes 9 mS and the X coordinate detection period occupies almost 3.0%.
Further, the conventional segment drive circuit requires multiplexers 101, 102, ... For each LSI as shown in FIG. 11, and further requires a chip select setting circuit 50, which makes the circuit complicated. There is. Also, X
There is a drawback that the coordinate detection accuracy is low. FIG. 4 (a) is an exaggerated waveform of the induced voltage in the case of stepwise scanning in the X-coordinate detection of FIG. 12 and FIG. 9, in which high-frequency components are actually removed, and as shown in FIG. 4 (b). However, the shoulders are actually gentler. The waveform of the induced voltage is left-right symmetrical when the detection pen is located approximately at the center of the electrode group to which a voltage is applied simultaneously, but if it is outside that, it becomes asymmetric as shown in the figure. After the induction voltage is amplified, it is binarized by the slice voltage g, as shown in FIG. 4 (c). The coordinates of the pen are obtained by measuring the times T ₁ and T ₂ from the reference point with a counter and obtaining the center value from the average value. In the case of FIG. 4B, when the slice level g-g ′ is near the shoulder, T ₁ becomes unstable as shown in FIG. It becomes stable and the detection accuracy drops. Therefore, an object of the present invention is to provide a display-integrated tablet having a short X-coordinate detection period, a simple circuit, and high X-coordinate detection accuracy.

[0013]

To achieve the above object, the present invention provides a display panel having a segment electrode group and a common electrode group, a segment drive circuit for applying a voltage to the segment electrode group, and the common electrode. A common drive circuit for applying a voltage to the group, a detection pen electrostatically coupled to the electrode group, and means for amplifying the electrostatic induction voltage of the detection pen, and displaying an image on the display panel, In a display-integrated tablet configured to perform time-division and coordinate detection for fixing the position of the detection pen by a voltage induced in the detection pen brought into contact with the display panel surface,
The segment drive circuit comprises a plurality of drive integrated circuits connected in cascade by serial input / output terminals,
The driving integrated circuit has a scanning mode setting means for setting the scanning mode of the driving integrated circuit to the first mode for the display period and the second mode for the coordinate detection period, the serial input / output terminal, and the display period. A data input terminal to which display data is input, a data latch for latching the data input from the data input terminal, a line latch, a shift register, a drive signal output means, and a control means. In the first mode, the serial input / output terminal acts as a chip select terminal, the display data input from the data input terminal is latched by a data latch, and the data for one row latched by the data latch is stored. Transfer to a line latch, and drive signals based on the data transferred to the line latch are simultaneously parallelized by the drive signal output means. In the second mode, the serial input / output terminal is made to act as a shift data input / output terminal, and the shift data input from the serial input terminal is serially output to the serial output terminal by the shift register and shifted. The drive signal based on the shift data shifted by the shift register is sequentially and serially output by the drive signal output means.

Further, in the present invention, it is desirable that the pulse width of the shift data is larger than the cycle of the clock signal for transferring the shift data. Further, the present invention is
In the case where the scanning of the segment drive circuit and the scanning of the common drive circuit are performed in a time division during the coordinate detection period, the shift data is output from the final stage of the drive circuit that scans first, and the shift data of the drive circuit that scans next is output. Shift data control means for inputting to the first stage may be provided. Further, the shift data control means delays the shift data output from the last stage of the drive circuit to be scanned first for a predetermined time and then inputs the shift data to the first stage of the drive circuit to be scanned next. You can also Further, the present invention is
The common drive circuit is an integrated circuit having the same configuration as the drive integrated circuit that constitutes the segment drive circuit, and the scan mode setting means always sets the scan mode to the second mode. Can be connected in cascade.

[0015]

In the above structure, the scanning mode setting means sets the scanning mode to the first mode during the display period.
Then, the control means causes the serial input / output terminal to act as a chip select terminal, causes the display data input from the display data input terminal to be latched by a data latch, and one row of data latched by the data latch is line latched. And the drive signal output means outputs the drive signals based on the data transferred to the line latch in parallel at the same time. On the other hand, during the coordinate detection period, the scanning mode setting means sets the scanning mode to the second mode. And
The control means causes the serial input / output terminal to act as a shift data input / output terminal, shifts the shift data input from the serial input terminal while serially outputting the shift data to the serial output terminal by the shift register, and by the shift register. A drive signal based on the shifted shift data is sequentially output serially by the drive signal output means. Therefore, the data transfer operation during the coordinate detection period is much simpler than the data transfer operation during the display period, and therefore the X coordinate detection period is much shorter than the conventional example. Further, since the shift data input from the serial input terminal is output from the serial output terminal and input to the serial input terminal of the driving integrated circuit of the next stage, the multiplexer 101 for each LSI as in the conventional example, .. and the chip select setting circuit 50 are not required, and the circuit becomes simple.

Further, when the pulse width of the shift data is made larger than the cycle of the clock signal for transferring the shift data, that is, as shown in FIG. 3, the pulse width of the shift data (SD) is the clock signal. When it is longer than the period of (DST), the drive signals applied to the segment electrodes X1, X2, ... At the falling edge of DST overlap by four electrodes, and the waveform of the voltage induced in the detection pen is As illustrated in FIG. 5, the smoothness is achieved, and the detection accuracy of the X coordinate is increased. Further, as illustrated in FIG. 6, the shift data is output from the final stage 2p of the common drive circuit and delayed directly or by the delay circuit 200 for a predetermined time, and then input to the first stage 3 ₁ of the segment drive circuit. Or
Alternatively, the shift data may be output from the final stage 3n of the segment drive circuit, and may be input to the first stage 2 ₁ of the common drive circuit either directly or after being delayed for a fixed time, so that both the common drive circuit and the segment drive circuit It is not necessary to separately apply the shift data to each of them, and the entire circuit configuration can be simplified. Further, by using an integrated circuit having the same structure as the driving integrated circuit of the segment driving circuit for the driving integrated circuit of the common driving circuit, inventory management of parts can be facilitated.

[0017]

The present invention will be described in detail below with reference to the embodiments shown in the drawings. 1 is a block diagram of an LSI constituting a segment drive circuit used in an embodiment of the present invention, FIG. 2 is a circuit diagram of a segment drive circuit in which a plurality of the LSIs are connected in cascade, and FIG. 6 is a timing chart of X coordinate detection in the example. LSI3 shown in FIG.
Has a configuration in which a MODE terminal and a bidirectional shift register 27 are added to the LSI shown in FIG. The MODE circuit sets the display terminal to H (high) and the coordinate detection period to L (low) by the control circuit 7 shown in FIG. When the MODE terminal becomes H, the control circuit 26 as the control means and the scanning mode setting means sets the scanning mode to the "display mode" which is the first mode.
When set to L, the scanning mode is set to the second mode, that is, "detection mode". Then, in the display mode, E101 and E102 are replaced with EIO1 and E102 in FIG.
Just like IO2, it functions as a chip select input / output terminal, and in the detection mode, E101 and E102 have new functions to function as shift data input / output terminals. In the detection mode, EIO1 becomes a serial input when L / R = H and a serial output when L / R = H. See E
IO2 is the opposite of EIO1. XCK is used to transfer the data D _{0 to} D _{3 in} the display mode and is used as the shift register 21.
However, it is not used in the detection mode. The DST operates as an LP input terminal in the display mode, and operates as a shift data clock in the detection mode. The terminals D _{0 to} D ₃ are display data input terminals in the display mode, but are not used in the detection mode.

Next, the operation of this LSI 3 will be described. When the scan mode is the display mode, EIO1 and EIO2 are
Just like EIO1 and EIO2 in 0, they work as input / output terminals for chip select, and both shift register 2
It is set to 1 serial input / output, and the display data D _{1 to} D ₃ are transferred by the transfer clock XCK. Shift register 2
Each bit of 1 has a parallel output function, and this output is a 4 × 20 bit data latch 22 having one gate in units of 4 bits (FIG. 1 shows the case of 4 bits but 8 or 16 bits are also possible) 22 Is connected to each gate. Therefore, the display data transferred by the clock XCK is sequentially stored in the data latch 22 and all the data is stored in the data latch 22 by the clock of 20 times, and at the same time, this LSI is in the non-selected state. Shift register 2
Since the input / output of 1 is connected to EIO1 and EIO2 respectively, the shift data from EIO1 is simultaneously output to the chip select EIO2 in this state, and the next LSI is selected by the chip select EIO1 of the next LSI connected to the cascade. To do. In this display mode, the line latch 23 is a bit bus and the level shifter 2 is
4 is connected. DST is a data strobe (latch pulse) input terminal, which latches the data of the data latch 22 in the line latch 23 at the falling edge, and the level shifter 24 according to the contents of the line latch and the FR signal.
A voltage required for scanning is selected from V _{0 to} V ₅ , and the LCD driver 25 outputs the voltages simultaneously from the output terminals OUT1 to OUT80. At the same time (falling down of DST), the chip select is cleared by the control circuit 26.

When the scanning mode is the detection mode, EIO
1, EIO2 become shift data input / output terminals, and R ₁ , R
It becomes the input / output of the bi-directional shift register 27 consisting of 80 registers of ₂ , ..., R ₈₀ . or,
The level shifter 24 is connected to the parallel output of the bidirectional shift register 27, and the line latch 2
Separated from 3. Therefore, the shift data given to EIO1 (EIO2 by L / R) is output as a parallel output of the bidirectional shift register 27.
LCD driver 25 through the level shifter 24 in sequence
Is output to the electrode group via OUT1 ... OUT80. In this detection mode, EIO1 serves as a shift data input terminal, and the shift data input to EI01 is transferred to the bidirectional shift register 27 by the clock pulse applied to DST and then output from EI02. .. That is, LSI3 ₁
The data input to EIO1 ₁ → R ₁ → R ₂ → R ₃ … →
R ₈₀ → EIO2 ₁ is transferred in this order, and E of the next LSI 3 ₂ is transferred.
It is input to IO1 ₂ and the same process is followed by L at the final stage.
Transfers up to SI3n.

As shown in FIG. 2, E of the first stage LSI 3 ₁
IO1 ₁ is connected to the output of the multiplexer 100, and the input of the multiplexer 100 is either Y1 or Y2 selected by the MODE signal. In the display mode, the MODE signal is H, and the input of the multiplexer 100 is Y ₁ set to L (Vss),
EIO1 ₁ becomes L. MODE, XCK, FR, DST,
D _{0 to} D ₃ , V _{0 to} V _5, etc. are connected to all LSIs, and each L
SI is sequentially chip-selected by the chip select terminals EIO1 ₁ , EIO1 ₂ , ... In this display mode, E
IO1 ₁ is fixed to L via the multiplexer 100, but in the initial state after the latch pulse is applied to the DST terminal, all other chip select output terminals E
102 ₁ , E 102 ₂ ... Are H, EIO _{1 2} , EIO 1 ₃ ... Connected thereto are also H, and only 3 ₁ is selected. Data D corresponding to output terminal group 1
_{0 to} D ₃ are transferred to 3 ₁ by XCK, and the number of outputs of one chip (80 channels in FIG. 1) consists of 4 bits 2.
EIO2 ₁ is set to L and EIO connected to it is stored in 0 sets of data latches sequentially (by 20-bit shift register) and all (4 × 20 bits) have been stored.
1 ₂ also becomes L, the first stage LSI is in the non-selected state, and the second stage LSI 3 ₂ is selected. Then be transferred to the LSI 3 ₂ of the second stage data is accommodated within the data latch. The selection of the data latch that stores the data D _{0 to} D ₃ is performed by the 20-bit shift register 21. This operation is repeated in sequence, and the final stage LSI
When the data is stored in the 3n data latch, LP is applied from the DST, the data in the data latches of all the LSIs are transferred to the line latches, and the voltage corresponding to the FR signal is output to the output terminal group OUT1 to OUT1 by the LCD driver. OU
The signals are simultaneously output from T80 and applied to the electrode group connected thereto. Thus, in the display mode, the same operation as in the case of using the conventional LSI shown in FIG. 10 is performed.

In the detection mode, the MODE signal is L and the input of the multiplexer 100 is Y ₂ .
The shift data SD is applied to EIO1 ₁ . EIO
1 have been SD is input to _1, is transferred to the bi-directional shift register 27 by a clock pulse CP2d applied to LSI 3 ₁ of DST, the shift register of _{R 1 → R 2 → R 3} ... R 80 Are transferred in order and EIO
It is output to 2 ₁ . The SD output to this EI02 ₁ is
Subsequently entered into EIO1 ₂ of the next stage LSI 3 _2, below, it is transferred to successively LSI3n. The contents of the bidirectional shift register 27 are sequentially output OUT1 → ... → OUT80 as a voltage set by the FR signal through the level shifter 24 without passing through the latch.
→… is output.

FIG. 3 is a time chart of detection scanning when this LSI is used. The output overlaps by four electrodes and is shifted by one electrode.
This is different from scanning 4 electrodes of 2 collectively. This is Figure 9
The Y-coordinate detection is the same as the above, and the voltage applied to the electrodes is smoothly shifted.
As compared with the case of (X coordinate detection scanning in FIG. 9), the waveform of the voltage induced in the detection pen becomes smoother without any stepwise portion.

FIG. 5 (a) is an exaggerated voltage induced by the scanning of FIG. 3 according to the present embodiment for the purpose of explanation. Actually, a high frequency component is taken out as shown in FIG. 5 (b) due to stray capacitance or the like. Is in a closed state. Since the voltage is applied to each electrode independently, it may be strictly asymmetrical to the left and right, but since it has a small number of steps, it can be considered to be practically symmetrical. After the induction voltage is amplified, it is binarized by the slice voltage g, as shown in FIG. The coordinates of the pen are obtained by measuring the time T ₁ T ₂ from the reference point with a counter and obtaining the center value from the average value. In the case of FIG. 5 according to the present embodiment, as compared with the case of FIG. 4 according to the conventional example, since the waveform has a shoulderless left-right symmetry, even if the slice level and the level of the detection voltage fluctuate, it fluctuates symmetrically. The average value of ₁ and T ₂ is constant and the accuracy is high. In the description, the pulse width of the shift data is 4 clocks,
The larger the pulse width, the larger the induced voltage of the detection pen. However, the saturation is more than about 20, and the effect decreases even if the number is increased more, and conversely, the maximum level (peak portion) of the detection voltage waveform of the detection pen in FIG. Not only that, the non-detection region in the peripheral portion becomes wide, which is not preferable. The optimum number depends on the distance between the display electrode and the detection pen, but it is within 32 when a protective panel is placed on a normal display panel, but it is set to about 8 to 16 clocks and overlaps 8 to 16 electrodes. It is appropriate to scan in the form of a circle.

As described above, in the display-integrated tablet of this embodiment, the LSI shown in FIG. 1 is used as the LSI of the segment drive circuit instead of the conventional LSI shown in FIG. Input / output terminals E101, E
Since the drive signal is applied based on the shift data input / output from 102, the scanning can be extremely simplified, the circuit can be simplified, and the X coordinate scanning time can be remarkably shortened. For example, X which is about 500 μS in the conventional method
The coordinate detection period can be shortened to about 100 μS. Further, as shown in FIG. 3, by making the pulse width of the shift data SD four times the cycle of the clock signal DST, the X coordinate detection scanning is performed by shifting by one electrode in the form of overlapping by four electrodes. Therefore, the waveform of the induced voltage of the detection pen becomes smooth, and the detection accuracy is improved. Also, the fact that the coordinate detection period can be shortened makes it possible to increase the display duty ratio, but if the coordinate detection period is the same, it is possible to perform multiple scans within the detection period, further increasing detection accuracy. Can be done.

Further, both the common and segment drive circuits in the coordinate detection period transfer shift data by clock pulses, and finally output from the output terminal. Therefore, the common drive circuit 2 is scanned as shown in FIG. 6, for example. The last stage LS after
The output of the I2p shift data output terminal EIO2p can also be used as the shift data of the segment drive circuit 3. Further, the output of the common drive circuit 2 may be delayed by a delay circuit 200 such as a shift register instead of being directly connected to the input of the segment drive circuit 3. As a matter of course, the segment drive circuit 3 may be scanned first and then the common drive circuit 2 may be scanned. With this configuration, the circuit configuration can be simplified.

As is apparent from the above description, the operation in the detection mode in the segment drive circuit using the LSI of FIG. 1 is the same as the operation in the display and coordinate detection of the common drive circuit. Therefore, the LSI of FIG. 1 can also be used for the common drive circuit. Being able to share the LSI for the common drive circuit and the segment drive circuit is convenient for inventory management of parts.

In the above embodiment, the display data is described as 4 bits of D _{0 to} D ₃ , but it can be applied to 8 and 16 bits. In this case, the number of bits of the shift register 21, the data latch, etc. are different from those in FIG. Further, the number of output channels of the LSI has been described using 80 channels as a model, but the number of output channels is not limited to this. Although the liquid crystal panel has been described as the display panel, the present invention can be applied to an EL display panel.

[0028]

As is apparent from the above, the display-integrated tablet of the present invention comprises a plurality of drive integrated circuits in which segment drive circuits are connected in cascade by serial input / output terminals. In the coordinate detection period, the shift data input from the serial input terminal is serially output to the serial output terminal by the shift register while being shifted, and the drive signal is a drive signal based on the shift data shifted by the shift register. Since the output means sequentially outputs serially, the scanning process is simplified and the time required for coordinate detection can be significantly shortened. In addition, multiplexers 101 and 10 for each LSI as in the conventional example
The circuit becomes simple because the 2, .. and chip select setting circuits 50 are not required. Further, by making the pulse width of the shift data larger than the cycle of the clock signal for transferring the shift data, the waveform of the voltage induced in the detection pen can be smoothed, and the X coordinate detection accuracy is improved.
In addition, the shift data is output from the final stage of the common drive circuit and directly or after being delayed for a certain period of time, and then input to the first stage of the segment drive circuit, so that the common drive circuit and the segment drive circuit separately. There is no need to apply shift data, and the entire circuit configuration can be simplified. Further, by using an integrated circuit having the same structure as the driving integrated circuit of the segment driving circuit for the driving integrated circuit of the common driving circuit, inventory management of parts can be facilitated.

[Brief description of drawings]

FIG. 1 is a block diagram of an LSI used in an embodiment of the present invention.

FIG. 2 is a circuit diagram of a segment drive circuit in which the above LSIs are connected in cascade.

FIG. 3 is a time chart of X coordinate detection in the above embodiment.

FIG. 4 is a waveform diagram of a detected voltage in a conventional example.

FIG. 5 is a waveform diagram of a detected voltage in the above embodiment.

FIG. 6 is an explanatory diagram of a case where data from a common drive circuit is used as input data for a segment drive circuit in the above embodiment.

FIG. 7 is a circuit configuration diagram of a general display-integrated tablet.

FIG. 8 is a diagram showing a display period and a coordinate detection period in the display-integrated tablet.

FIG. 9 is a timing chart for coordinate detection in a conventional example.

FIG. 10 is a block diagram of an LSI used in a conventional segment drive circuit.

FIG. 11 is a circuit diagram of the conventional segment drive circuit.

FIG. 12 is a time chart of X-coordinate detection in the conventional example.

[Explanation of symbols]

1 ... Display panel, 2 ... Common drive circuit, 3 ... Segment drive circuit, 2 ₁ , ..., 2p ... Common drive LSI, 3 ₁ , ..., 3
n ... Segment drive LSI, 8 ... Position detection pen, 21 ...
Shift register, 22 ... data latch, 23 ... line latch, 24 ... level shifter, 25 ... LCD driver, 2
6 ... Control circuit, 27 ... Bi-directional shift register, X ₁ , .., Xm ... Segment electrodes,
Y _1, .. Yn ... common electrode, EI01, EI02 ... serial input and output terminals, D0 to D3 ... data input terminal, MODE ...
Mode setting terminals, UT1, ..., UT80 ... Output terminals.

Claims (5)

[Claims] 1. A display panel having a segment electrode group and a common electrode group, a segment drive circuit for applying a voltage to the segment electrode group, a common drive circuit for applying a voltage to the common electrode group, and the electrode group. A detection pen that is electrostatically coupled and a means that amplifies the electrostatic induction voltage of the detection pen are provided, and by the display of an image by the display panel and the voltage induced in the detection pen brought into contact with the display panel surface, In a display-integrated tablet adapted to perform coordinate detection for fixing the position of the detection pen in time division, the segment drive circuit includes a plurality of drive integrated circuits connected in cascade by serial input / output terminals,
The driving integrated circuit has a scanning mode setting means for setting the scanning mode of the driving integrated circuit to the first mode for the display period and the second mode for the coordinate detection period, the serial input / output terminal, and the display period. A data input terminal to which display data is input, a data latch for latching the data input from the data input terminal, a line latch, a shift register, a drive signal output means, and a control means. In the first mode, the serial input / output terminal acts as a chip select terminal, the display data input from the data input terminal is latched by a data latch, and the data for one row latched by the data latch is stored. Transfer to a line latch, and drive signals based on the data transferred to the line latch are simultaneously parallelized by the drive signal output means. It is outputted, in the second mode,
The serial input / output terminal is caused to act as a shift data input / output terminal, and the shift data input from the serial input terminal is serially output to the serial output terminal by the shift register while being shifted, and then shifted by the shift register. A display-integrated tablet characterized in that a drive signal based on shift data is sequentially output serially by the drive signal output means. 2. The display-integrated tablet according to claim 1, wherein a pulse width of the shift data is larger than a cycle of a clock signal for transferring the shift data. 3. The display-integrated tablet according to claim 1, wherein when the scanning of the segment drive circuit and the scanning of the common drive circuit are performed in time division during the coordinate detection period, the shift data is first transmitted. The first stage of the drive circuit to be scanned next is output from the final stage of the drive circuit to scan.
A display-integrated tablet characterized by comprising shift data control means for inputting to a stage. 4. The display-integrated tablet according to claim 3, wherein the shift data control means delays the shift data output from the last stage of the driving circuit for scanning first by a predetermined time, and then, First drive circuit to scan
A display-integrated tablet characterized in that it is adapted to input in stages. 5. The display-integrated tablet according to claim 1, wherein the common drive circuit is an integrated circuit having the same configuration as the drive integrated circuit that constitutes the segment drive circuit, A display-integrated tablet characterized in that a plurality of integrated circuits are connected in cascade so that the scanning mode setting means always sets the scanning mode to the second mode.