CN107885638A - Hard disk backboard - Google Patents
Hard disk backboard Download PDFInfo
- Publication number
- CN107885638A CN107885638A CN201711102906.4A CN201711102906A CN107885638A CN 107885638 A CN107885638 A CN 107885638A CN 201711102906 A CN201711102906 A CN 201711102906A CN 107885638 A CN107885638 A CN 107885638A
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- Prior art keywords
- hard disk
- load signal
- level
- signal
- cpld
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
- G06F11/3037—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a memory, e.g. virtual memory, cache
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/32—Monitoring with visual or acoustical indication of the functioning of the machine
- G06F11/324—Display of status information
- G06F11/328—Computer systems status display
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Quality & Reliability (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Mathematical Physics (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
Abstract
The invention discloses a kind of hard disk backboard to have substrate, communication interface and CPLD.Communication interface is located at substrate, and suitable for being plugged in a server to receive hard disk load signal and clock signal.CPLD is electrically connected with communication interface, relation of the CPLD according to hard disk load signal and clock signal, judges that hard disk load signal comes from the platform path controller of server or the host bus adaptor of server.
Description
Technical field
The present invention has automatic identification hard disk controlling signal type ability on a kind of hard disk backboard, especially in regard to a kind of
Hard disk backboard.
Background technology
Server is used as the processor of server and the interface of hard disk usually using hard disk backboard.In order to correctly show
The operating state of hard disk and/or the correctly running of control hard disk, the running of hard disk backboard must be arranged in pairs or groups mutually with server.
However, server with tandem universal input export (serial general purpose input/output,
SGPIO) the hard disk controlling signal of form output does not only have a kind of form.Specifically, hard disk controlling signal may be from
The platform path controller (platform controller hub, PCH) of server, it is also possible to come from the main frame of server
Bus adapter (host bus adaptor, HBA).For the user or guardian of server, whenever setting, safeguard
During server, it is necessary to carefully confirm hard disk controlling signal that it is exported for the model or specifications (spec) of server
Form, so as to select correct hard disk backboard.So for user/guardian of server, suitable trouble is caused.
The content of the invention
In view of this, the present invention is intended to provide a kind of hard disk backboard, has automatic hard disk controlling of the identification from server
The function of signal.
Hard disk backboard according to one embodiment of the invention has substrate, communication interface and CPLD
(complex programmable logic device,CPLD).Communication interface is located at substrate, and suitable for being plugged in a clothes
Device be engaged in receive hard disk load signal and clock signal.CPLD is electrically connected at communication interface, and complexity can
Relation of the programmed logic device according to hard disk load signal and clock signal, judge that hard disk load signal comes from the flat of server
Host bus adaptor (the host bus of platform path controller (platform controller hub, PCH) or server
adapter,HBA)。
In another embodiment of the present invention, the first level or second electrical level, and complex programmable is presented in hard disk load signal
Logical device is presented according to hard disk load signal in the time interval of the first level, and the periodicity of clock signal judges that hard disk loads
Signal comes from PCH or HBA to produce judged result.
In further embodiment of this invention, if hard disk load signal is presented in the time interval of the first level, clock signal
Periodicity be 12, then CPLD judge that hard disk load signal comes from HBA.
In further embodiment of this invention, if hard disk load signal is presented in the time interval of the first level, clock signal
Periodicity be 24, then CPLD judge that hard disk load signal comes from PCH.
In further embodiment of this invention, when hard disk load signal is changed into the first level from second electrical level, complexity can
Programmed logic device starts to calculate the periodicity of clock signal, and when periodicity is 12, judges that hard disk load signal is presented the
One level or second electrical level, to judge that hard disk load signal comes from PCH or HBA.
In further embodiment of this invention, if periodicity is 12, second electrical level is presented in hard disk load signal, then judges hard
Disk load signal comes from PCH, otherwise judges that hard disk load signal comes from HBA.
In further embodiment of this invention, when hard disk load signal is changed into the first level from second electrical level, complexity can
Programmed logic device starts to calculate the periodicity of clock signal, and stops when hard disk signal is second electrical level from the first level transitions
Only calculate the periodicity of clock signal.
In further embodiment of this invention, communication interface more receives indication signal, and CPLD has
There are one group of first shift registor, one group of second shift registor and selection circuit.The shift registor of group first has 12 1
Position buffer, the shift registor of group second have 24 1 buffers.Selection circuit, to when hard disk load signal is from
When one level transitions are second electrical level, more the first storage values of the shift registor of group first are exported according to judged result selection
Or more the second storage values of the shift registor of group second.Wherein when hard disk load signal is changed into the first electricity from second electrical level
Usually, the shift registor of group first starts to read in indication signal according to clock signal with the shift registor of group second.
In summary, the hard disk backboard according to one embodiment of the invention, according to the hard disk load signal for coming from server
With the relation of clock signal, it is able to automatically judge the source of hard disk load signal, so as to which hard disk backboard is able to according to judging to tie
Fruit correctly shows disk state and/or controlled accordingly.
More than on the explanation of present invention and the explanation of following embodiment demonstrating and explain the present invention
Spirit and principle, and provide the present invention patent application claims protection domain further explain.
Brief description of the drawings
Figure 1A is the organigram of the hard disk backboard according to one embodiment of the invention.
Figure 1B is the functional block diagram of the hard disk backboard according to one embodiment of the invention.
Fig. 2A is according to signal timing diagram of the hard disk load signal from platform path controller in one embodiment of the invention.
Fig. 2 B are according to signal timing diagram of the hard disk load signal from host bus adaptor in one embodiment of the invention.
Fig. 3 is the functional block diagram of the first shift registor according to one embodiment of the invention.
Wherein, reference：
1000 hard disk backboards
1100 substrates
1200 communication interfaces
1300 CPLDs
1310 first shift registors
1320 second shift registors
1330 selection circuits
2000 servers
2100 platform path controllers
2200 host bus adaptor
VH high level
VL low levels
LOAD hard disk load signals
IND indication signals
CLK clock signals
P1, P2 time interval
Embodiment
The detailed features and advantage of the narration present invention, its content are enough to make any ability in detail in embodiments below
The technical staff in domain understands the technology contents of the present invention and implemented according to this, and is wanted according to content disclosed in this specification, right
Protection domain and accompanying drawing are asked, any those skilled in the art can be readily understood upon the purpose and advantage of correlation of the invention.Below
Embodiment the viewpoint of the present invention is further described, it is but non-anyways to limit scope of the invention.
Figure 1A and Figure 1B are refer to, wherein Figure 1A is the organigram of the hard disk backboard according to one embodiment of the invention,
And Figure 1B is the functional block diagram of the hard disk backboard according to one embodiment of the invention.As illustrated, one embodiment of the invention is hard
Disk backboard 1000 has substrate 1100, communication interface 1200 and CPLD (complex programmable
logic device,CPLD)1300.Communication interface 1200 is respectively positioned on substrate 1100 with CPLD 1300, and
And communication interface 1200 is suitable to be plugged in server 2000 to receive hard disk load signal LOAD and clock pulse letter from server 2000
Number CLK.The present invention is not any limitation as the shape size of machine plate 1100 and the structure of communication interface.
CPLD 1300 is electrically connected with communication interface 1200, the foundation of CPLD 1300
Hard disk load signal LOAD and clock signal CLK relation, judges that hard disk load signal comes from the platform road of server 2000
Host bus adaptor (the host bus of footpath controller (controller hub, PCH) 2100 or server 2000
adapter,HBA)2200。
In particular, CPLD 1300 is in low level state according to hard disk load signal LOAD
In time interval, clock signal CLK periodicity number, determining the source of hard disk load signal, so control exactly
Hard disk/hard disk cresset.In an embodiment, Fig. 2A and Fig. 2 B are refer to, wherein Fig. 2A is according to hard in one embodiment of the invention
Signal timing diagram of the disk load signal from platform path controller, and Fig. 2 B are to be loaded according to hard disk in one embodiment of the invention
Signal timing diagram of the signal from host bus adaptor.As shown in Figure 2 A, if hard disk load signal comes from server
The situation of 2000 platform path controller 2100, hard disk load signal LOAD level are low level VL time interval P1 meetings
Substantial equivalence clock signal CLK 24 cycles.As shown in Figure 2 B, if hard disk load signal comes from the master of server 2000
The situation of machine bus adapter 2200, the time interval P2 that hard disk load signal LOAD level is low level VL can substantial equivalence
Clock signal CLK 12 cycles.
Therefore, in an embodiment, CPLD 1300 is set at hard disk load signal LOAD electricity
Put down for low level VL when, the number of detecting clock signal CLK positive edge (positive edge).So-called clock signal CLK is just
Edge, the level for being exactly clock signal CLK are converted to the event of high level VH (second electrical level) from low level VL (the first level).Instead
It, so-called clock signal CLK negative edge, is exactly that clock signal CLK level is converted to low level VL event from high level VH.
If hard disk load signal LOAD level be low level VL time interval between, calculating clock signal has
11 positive edges, it can estimate since hard disk load signal LOAD negative edge untill hard disk load signal LOAD positive edge
Clock signal CLK periodicity is 12 in this period, so as to which CPLD 1300 judges hard disk load signal
Host bus adaptor 2200 of the LOAD from server 2000.
If hard disk load signal LOAD level be low level VL time interval between, calculating clock signal has
23 positive edges, it can estimate since hard disk load signal LOAD negative edge untill hard disk load signal LOAD positive edge
Clock signal CLK periodicity is 24 in this period, so as to which CPLD 1300 judges hard disk load signal
Platform path controllers 2100 of the LOAD from server 2000.
Specifically, usual clock signal CLK positive edge can be substantially right with hard disk load signal LOAD negative edge/positive edge
Together, so if hard disk load signal LOAD level is in low level VL time interval, clock signal CLK experienced 12
Cycle, then CPLD 1300 be only capable of calculating to 11 positive edges or 12 negative edges.If hard disk load signal
LOAD level is in low level VL time interval, and clock signal CLK experienced 24 cycles, then complicated programmable logic device
Part 1300 is only capable of calculating to 23 positive edges or 24 negative edges.
Therefore in another embodiment, CPLD 1300 is set at hard disk load signal LOAD electricity
Put down for low level VL when, the number of detecting clock signal CLK negative edge (negative edge).
If hard disk load signal LOAD level be low level VL time interval between, calculating clock signal has
12 negative edges, it can estimate since hard disk load signal LOAD negative edge untill hard disk load signal LOAD positive edge
Clock signal CLK periodicity is 12 in this period, so as to which CPLD 1300 judges hard disk load signal
Host bus adaptor 2200 of the LOAD from server 2000.
If hard disk load signal LOAD level be low level VL time interval between, calculating clock signal has
24 negative edges, it can estimate since hard disk load signal LOAD negative edge untill hard disk load signal LOAD positive edge
Clock signal CLK periodicity is 24 in this period, so as to which CPLD 1300 judges hard disk load signal
Platform path controllers 2100 of the LOAD from server 2000.
In addition, in a more embodiment of the invention, when hard disk load signal LOAD level is from high level VH (the second electricity
It is flat) when being changed into low level VL (the first level), CPLD 1300 starts to calculate clock signal CLK cycle
Number, and when periodicity be 12 when, CPLD 1300 judge hard disk load signal LOAD presentation low level VL or
High level VH, to judge that hard disk load signal LOAD comes from the platform path controller 2100 or host bus of server 2000
Adapter 2200.
In this embodiment specifically, hard disk load signal LOAD is transformed into low level VL from high level VH and causes complexity can
Programmed logic device 1300 starts to detect clock signal CLK positive edge, and it is accumulative to start from scratch.When accumulative positive edge number is 12
Afterwards and before accumulative positive edge number reaches 13, CPLD 1300 detects hard disk load signal LOAD electricity
It is flat.
If periodicity is 12 (namely accumulative positive edge number is 12), high level VH is presented in hard disk load signal LOAD,
Then CPLD 1300 judges that hard disk load signal LOAD comes from host bus adaptor 2200.If periodicity
For 12 when (namely accumulative positive edge number be 12), hard disk load signal LOAD presentation low level VL, then complex programmable logic
Device 1300 judges that hard disk load signal LOAD comes from platform path controller 2100.
In another embodiment of the present invention, Figure 1B is gone back to, communication interface 1200 is more from server in this embodiment
2000 receive indication signal IND.Wherein indication signal IND is to export (serial general with tandem universal input
Purpose input/output, SGPIO) specification transmitting.CPLD 1300 has one group first and moved
Position 1310, one group of second shift registor 1320 of buffer and selection circuit 1330.Wherein first shift registor of group 1310
With 12 1 buffers (one-bit register) in first in first out (first in first out, FIFO) mode
It is electrically connected with, and there are second shift registor of group 1,320 24 1 buffers to be electrically connected with a manner of first in first out.
Selection circuit 1330 is electrically connected to first shift registor of group 1310 and second shift registor of group 1320.
When hard disk load signal LOAD is changed into high level VH from low level VL, selection circuit 1330 is to according to judged result selection
Export first shift registor of group 1310 more the first storage values or more second of second shift registor of group 1320
Storage values.
In order to understand the function mode of the first shift registor 1310 and the second shift registor 1320, moved below with first
Illustrate exemplified by the buffer 1310 of position, refer to Fig. 3, it is the function side of the first shift registor according to one embodiment of the invention
Block figure.First shift registor 1310 has 1 buffer REG_0~REG_9 and REG_A~REG_B.Wherein, 1 buffer
REG_0 input is electrically connected to selection circuit 1330 to receive indication signal IND, 1 buffer REG_0 output end
With 1 buffer REG_1 input.1 buffer REG_1 output end is electrically connected to selection circuit 1330 and 1 temporary
Storage REG_2 input.1 buffer REG_2 output end is electrically connected to selection circuit 1330 and 1 buffer REG_
3 input.By that analogy, 1 buffer REG_9 output end is electrically connected to selection circuit 1330 and 1 buffer
REG_A input.1 buffer REG_A output end is electrically connected to selection circuit 1330 and 1 buffer REG_B's
Input.1 buffer REG_B output end is electrically connected to selection circuit 1330.Also, in an embodiment, complexity can
Programming in logic device 1300 passes through appropriate setting, so that when hard disk load signal LOAD is low level VL, the
Each 1 buffer REG_0~REG_B of one shift registor 1310 clock signal end is all set reception and comes from server
2000 clock signal CLK.So as to which since hard disk load signal LOAD negative edge, hard disk load signal LOAD is low level VL
Time interval in, the first shift registor 1310 is based on clock signal CLK and starts to read in indication signal IND and from 1
Buffer REG_0 starts to transmit to 1 buffer REG_B direction.The running of second shift registor 1320 and the first displacement
Buffer 1310 is roughly the same, and difference is that the quantity of 1 buffer is different.
If the indication signal IND sent from server 2000 and hard disk load signal LOAD comes from host bus adapter
Device 2200, then before the time interval that hard disk load signal LOAD is low level VL terminates, with the indication signal of SGPIO form transmission
IND amounts to 12 bits and is read into 1 buffer REG_0~REG_B just.And when hard disk load signal LOAD turns from low level VL
When being changed into high level VH (positive edge), according to judged result, (hard disk load signal LOAD comes from host bus to selection circuit 1330
Adapter 2200) and select the storage values in 1 buffer REG_0~REG_B of the first shift registor 1310 to export.
Similarly, if coming from platform from the indication signal IND that server 2000 is sent and hard disk load signal LOAD
Path controller 2100, then before the time interval that hard disk load signal LOAD is low level VL terminates, with SGPIO form transmission
Indication signal IND amounts to 24 1 buffers that 24 bits are read into the second shift registor 1320 just.And when hard disk loads
Signal LOAD from low level VL be changed into high level VH (positive edge) when, selection circuit 1330 according to judged result (hard disk load letter
Number LOAD comes from platform path controller 2100) and select in 24 1 buffers of the second shift registor 1320
Storage values export.
In summary, the hard disk backboard according to one embodiment of the invention, according to the hard disk load signal for coming from server
With the relation of clock signal, it is able to automatically judge the source of hard disk load signal, so as to which hard disk backboard is able to according to judging to tie
Fruit correctly shows disk state and/or controlled accordingly.
Although the present invention is disclosed as above with embodiment, so it is not limited to the present invention, any art technology
Personnel, without departing from the spirit and scope of the present invention, when can be used for a variety of modifications and variations, therefore protection scope of the present invention
It is defined when depending on the scope of which is defined in the appended claims.
Claims (8)
1. a kind of hard disk backboard, it is characterised in that the hard disk backboard includes：
One substrate；
An at least communication interface, positioned at the substrate, suitable for being plugged in a server and receiving an at least hard disk load signal and one
Clock signal；And
One complex programmable logic device (CPLD), an at least communication interface is electrically connected with, the CPLD loads according to the hard disk to be believed
Relation number with the clock signal, judge the hard disk load signal come from the server a platform path controller PCH or
One host bus adaptor HBA of the server.
2. hard disk backboard as claimed in claim 1, it is characterised in that one first level or one the is presented in the hard disk load signal
Two level, and the CPLD is presented in the time interval of first level according to the hard disk load signal, one week of the clock signal
Issue judges that the hard disk load signal comes from the PCH or HBA and produces a judged result.
3. hard disk backboard as claimed in claim 2, it is characterised in that if the hard disk load signal present first level when
Between in section, the periodicity of the clock signal is 12, then the CPLD judges that the hard disk load signal comes from the HBA.
4. hard disk backboard as claimed in claim 2, it is characterised in that if the hard disk load signal present first level when
Between in section, the periodicity of the clock signal is 24, then the CPLD judges that the hard disk load signal comes from the PCH.
5. hard disk backboard as claimed in claim 2, it is characterised in that when the hard disk load signal is changed into from the second electrical level
During first level, the CPLD starts to calculate the periodicity of the clock signal, and when the periodicity is 12, judges the hard disk
First level or the second electrical level is presented in load signal, to judge that the hard disk load signal comes from the PCH or HBA.
6. hard disk backboard as claimed in claim 5, it is characterised in that if the periodicity is 12, the hard disk load signal is in
The now second electrical level, then judge that the hard disk load signal comes from the HBA, otherwise judge that the hard disk load signal comes from the PCH.
7. hard disk backboard as claimed in claim 2, it is characterised in that when the hard disk load signal is changed into from the second electrical level
During first level, the CPLD starts to calculate the periodicity of the clock signal, and when the hard disk signal turns from first level
It is changed into stopping calculating during the second electrical level periodicity of the clock signal.
8. hard disk backboard as claimed in claim 2, it is characterised in that at least a communication interface more receives an indication signal for this,
Wherein the CPLD includes：
One group of first shift registor, there are 12 1 buffers；
One group of second shift registor, there are 24 1 buffers；And
One selection circuit, to when the hard disk load signal from first level transitions be the second electrical level when, according to the judgement
As a result selection export the shift registor of group first more the first storage values or more second of the shift registor of group second
Storage values；
Wherein when the hard disk load signal is changed into first level from the second electrical level, the shift registor of group first is with being somebody's turn to do
The second shift registor of group starts to read in the indication signal according to the clock signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711102906.4A CN107885638A (en) | 2017-11-10 | 2017-11-10 | Hard disk backboard |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711102906.4A CN107885638A (en) | 2017-11-10 | 2017-11-10 | Hard disk backboard |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107885638A true CN107885638A (en) | 2018-04-06 |
Family
ID=61779858
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711102906.4A Pending CN107885638A (en) | 2017-11-10 | 2017-11-10 | Hard disk backboard |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107885638A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110347555A (en) * | 2019-07-09 | 2019-10-18 | 英业达科技有限公司 | Hard disk operating state determination method |
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| JP2004062738A (en) * | 2002-07-31 | 2004-02-26 | Hitachi Ltd | Electronic board, signal control method of electronic board and diskarray device using the same |
| CN104267638A (en) * | 2014-09-19 | 2015-01-07 | 北京空间机电研究所 | Serializer/deserializer clock source based on clock managers and FPGA |
| CN105740116A (en) * | 2014-12-12 | 2016-07-06 | 环旭电子股份有限公司 | Hard disk backboard and detection method of serial general input/output signal of hard disk backboard |
| CN106155972A (en) * | 2016-07-04 | 2016-11-23 | 英业达科技有限公司 | Control system and control method thereof |
| CN106919492A (en) * | 2017-03-09 | 2017-07-04 | 郑州云海信息技术有限公司 | A kind of system and method that SGPIO is parsed by CPLD |
-
2017
- 2017-11-10 CN CN201711102906.4A patent/CN107885638A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004062738A (en) * | 2002-07-31 | 2004-02-26 | Hitachi Ltd | Electronic board, signal control method of electronic board and diskarray device using the same |
| CN104267638A (en) * | 2014-09-19 | 2015-01-07 | 北京空间机电研究所 | Serializer/deserializer clock source based on clock managers and FPGA |
| CN105740116A (en) * | 2014-12-12 | 2016-07-06 | 环旭电子股份有限公司 | Hard disk backboard and detection method of serial general input/output signal of hard disk backboard |
| CN106155972A (en) * | 2016-07-04 | 2016-11-23 | 英业达科技有限公司 | Control system and control method thereof |
| CN106919492A (en) * | 2017-03-09 | 2017-07-04 | 郑州云海信息技术有限公司 | A kind of system and method that SGPIO is parsed by CPLD |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110347555A (en) * | 2019-07-09 | 2019-10-18 | 英业达科技有限公司 | Hard disk operating state determination method |
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