JP6323065B2 - Microcomputer and electronic equipment - Google Patents

Description

  The present invention relates to a microcomputer, an electronic device, and the like.

  In a microcomputer, since a circuit element that operates according to an instruction (instruction) being executed is determined, there is a correlation between the instruction being executed and the current consumption of the power supply. Therefore, the traveling instruction can be estimated by measuring the change in current consumption over time.

  For example, if hardware for security measures such as security tokens is hacked by the above method, the algorithm can be decrypted, the password can be decrypted, and the hardware can be duplicated using the decrypted information, breaking the security. There is a risk.

Japanese translation of PCT publication No. 2002-508549 JP 2000-259799 A

  As a technique for obstructing the hacking as described above, a technique for reducing the correlation between an instruction and current consumption using a random number is known (for example, Patent Documents 1 and 2). For example, a method may be considered in which the generated random number is a binary bit string, one bit is extracted from the bit string, and the operation timing is shifted in the case of “1”.

  However, the random number may be continuously followed by “0” or “1”. Therefore, when “0” continues, the period for performing the normal operation continues for a long time, and a correlation occurs between the command and the current consumption. When “1” continues, the period for shifting the operation timing continues for a long time. There exists a subject that processing speed falls.

  According to some aspects of the present invention, it is possible to provide a microcomputer, an electronic device, and the like that can reduce the correlation between instructions and current consumption while suppressing a decrease in processing speed.

  One aspect of the present invention includes a processing unit that performs an instruction process, and a control data generation unit that generates control data that changes operation timing of the instruction process, and the control data generation unit generates random number data. A random number generation unit; and a code conversion unit that processes the random number data and generates the control data in which a predetermined number of bits of the same logic are not continuously generated. The processing unit is based on the control data The microcomputer relates to a microcomputer that performs the instruction process in which the operation timing changes.

  According to one aspect of the present invention, by processing random number data, control data that does not generate a predetermined number of consecutive bits of the same logic is generated, and the operation timing of instruction processing is changed based on the control data. The As a result, since the case where the operation timing is changed or the case where the operation timing is not changed can be prevented from continuing for a long period of time, it is possible to reduce the correlation between the command and the current consumption while suppressing a decrease in processing speed.

  In one aspect of the present invention, the random number generator generates random data of n bits (n is a natural number of 2 ≦ n), and the code converter includes j bits (j is 2 ≦ n). The random number data may be processed so that it does not continuously occur (natural number of j <n), and the control data of m bits (m is a natural number of n <m) may be generated.

  When the operation timing of the instruction process is changed, the processing speed is reduced, and when it is not changed, the correlation between the instruction and the current consumption is increased. In this regard, according to one aspect of the present invention, the number of consecutive bits of the same logic in the control data can be less than j bits. Since this bit number j is smaller than the bit number n of random number data, the number of consecutive bits of the same logic can be reduced as compared with the case where the bit string of random number data is used as it is as control data. Since whether or not to change the operation timing of the instruction processing is controlled by the bit logic, it is possible to shorten the period during which the operation timing is changed or not changed.

  One embodiment of the present invention includes a clock supply unit that supplies a clock signal having a cycle changed based on the control data to the processing unit, and the processing unit is based on the clock signal from the clock supply unit. Then, the operation timing of the instruction process may be changed by performing the instruction process.

  As described above, the operation timing of the instruction process can be changed by changing the cycle of the clock signal for executing the instruction process by the processing unit based on the control data. Since a predetermined number of the same logic does not continue in the control data, the case where the period is normal and the case where the period is changed do not continue for a long time, and a randomly distributed clock signal can be supplied.

  In one embodiment of the present invention, the clock supply unit may increase the cycle of the clock signal when the control data is at a first logic level.

  In this way, the period of the clock signal can be increased when the control data is at the first logic level without changing the period of the clock signal when the control data is at the second logic level. Since the first logic level and the second logic level are randomly generated by the random number data, the correlation between the instruction and the current consumption is reduced. In addition, when the second logic level continues, the processing speed decreases, but the predetermined number of the same logic does not continue, so that unevenness in processing speed is dispersed.

  According to another aspect of the present invention, the code conversion unit may include an 8b10b conversion unit that generates the control data that does not continuously generate a predetermined number of bits of the same logic by converting the random number data using the 8b10b method. Good.

  The 8b10b method is a method of converting 8-bit data into 10-bit data, and after the conversion, the data having the same logic bit is only 5 bits at the maximum. By converting the random number data by the 8b10b method, it is possible to generate control data in which only 5 bits of the same logic are continuous at the maximum.

  Further, according to one aspect of the present invention, the random number generation unit generates n-bit (n is a natural number of 2 ≦ n) random number data, and the code conversion unit includes the MSB side of the n-bit random number data. a first 8b10b converter to which n / 2-bit first random number data is input; and second of which n / 2-bit second random number data on the LSB side of the n-bit random number data is input. 1b sequentially selected from the conversion data comprising the 8b10b conversion unit, the first conversion data from the first 8b10b conversion unit, and the second conversion data from the second 8b10b conversion unit. And a selector that outputs the control data.

  In the case of using the 8b10b method, it is conceivable to simply use 8-bit random data, but there is a problem that the number of random data is limited in 8 bits. In this regard, by performing code conversion on the MSB side 8 bits and the LSB side 8 bits respectively by the 8b10b method, it is possible to secure the number of random numbers and improve the randomness of the control data.

  One embodiment of the present invention includes a clock supply unit that supplies a clock signal to the processing unit, and the clock supply unit has a cycle of the clock signal when the bit selected by the selector is a first logic level. May be increased.

  In this way, the selector sequentially selects one bit at a time from the control data, and controls the cycle of the clock signal according to the logic level of the selected bit, thereby randomly changing the operation timing of the instruction processing performed by the processing unit. be able to.

  One aspect of the present invention includes a bus control unit, and the bus control unit changes the access timing when the processing unit accesses the bus based on the control data, so that the operation of the instruction processing is performed. The timing may change.

  In this way, when the processing unit processes an instruction to access the bus, the bus access timing is changed according to the logic level of the control data. Since the bus access timing is randomly changed by the control data, the instruction processing timing can also be randomly changed.

  Another embodiment of the present invention relates to an electronic device including the microcomputer described above.

Operation | movement explanatory drawing of a comparative example. 2 is a configuration example of a microcomputer according to the present embodiment. Operation | movement explanatory drawing of this embodiment. An example of random data. Code conversion example. The 2nd structural example of the microcomputer of this embodiment. 3 shows detailed configuration examples of a clock supply unit and a control data generation unit. The operation | movement timing chart of a clock supply part and a control data generation part. Configuration example of an electronic device. Configuration example of an electronic device.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

1. Comparative Example FIG. 1 is an operation explanatory diagram of a comparative example of the present embodiment.

  The microcomputer includes a CPU (Central Processing Unit) for processing instructions and peripherals including a storage device, an interface, and the like. It is assumed that the clock signal CK_CPU is supplied to the CPU, and the CPU is operating in synchronization with the rising edge of the clock signal CK_CPU.

  That is, an instruction is fetched at the rising edge of the clock signal CK_CPU, the instruction is decoded at the next rising edge, and an address is calculated. In the address calculation, for example, the address of the main storage device in which data used for execution is stored is calculated. Then, the instruction is executed at the rising edge of the next clock signal CK_CPU, and the execution result is written in the register. In executing the instruction, for example, data is read from an address obtained by address calculation, and an arithmetic unit performs processing on the data.

  When pipeline processing is performed, processing of the first instruction, the second instruction,... Is started every clock, and a plurality of instructions are processed in parallel. In this case, an instruction execution result is obtained every clock.

  In such an operation, the current consumption (IDD) of the microcomputer differs depending on the content of the command. For example, in the case of instructions having different contents of calculation, the number and types of logic circuits used in the calculation device are different, and the current consumed by the logic circuit is different. Alternatively, an instruction using the arithmetic unit and an instruction not using it, and an instruction accessing the main storage device and an instruction not accessing the current consumption are different because the operating circuits are different.

  As described above, since the instruction is processed in synchronization with the rising edge of the clock signal CK_CPU, the consumption current is generated at the rising edge of each clock, and the consumption current corresponds to the instruction being executed at that time. Become. Therefore, by analyzing the current consumption (for example, the time change pattern), it is possible to infer an instruction executed by the microcomputer or an algorithm composed of the instruction.

2. Microcomputer FIG. 2 shows a configuration example of a microcomputer according to the present embodiment that can solve such a problem.

  The microcomputer includes a clock supply unit 10 (clock generator), a control data generation unit 20, a CPU 30 (processing unit), a ROM 40, a RAM 50 (main storage device), a bus 60, and first to s-th peripherals. PH1 to PHs (s is a natural number).

  The CPU 30 is a processing unit that performs instruction processing. The instruction process is a series of processes including the above-described instruction fetch, decode, address calculation, execution, and register write. The CPU 30 includes, for example, an instruction decoder, a register, an arithmetic unit (ALU: Arithmetic Logic Unit), and the like. The CPU 30 is connected to each unit such as the RAM 50 and the peripherals PH1 to PHs via the bus 60, and communicates with each unit via the bus 60.

  ROM 40 and RAM 50 are internal memories of the microcomputer. The RAM 50 is used as a main storage device (primary storage device) that stores programs and data processed by the CPU 30.

  The peripherals PH1 to PHs are devices that realize peripheral functions of the microcomputer, such as counters, timers, interrupt controllers, serial interfaces (for example, UART: Universal Asynchronous Receiver Transmitter), AD converters, DA converters, oscillation circuits, etc. .

  The clock supply unit 10 receives clock signals CKS1 to CKSt (t is a natural number) supplied from a clock source and generates a plurality of clock signals. The clock source is, for example, a clock generation circuit outside the microcomputer, an oscillation circuit inside the microcomputer, or the like. The clock supply unit 10 supplies the generated clock signals CK_PH1 to CK_PHs, CK_SYS, and CK_CPU to the peripherals PH1 to PHs, the control data generation unit 20, and the CPU 30 (and the ROM 40 and the RAM 50), respectively.

  The control data generation unit 20 generates control data CTL that changes the operation timing of the instruction processing. The CPU 30 performs an instruction process in which the operation timing changes based on the control data CTL.

  Specifically, the control data generation unit 20 includes a random number generation unit 21 that generates random number data, and the control data generation unit 20 outputs control data CTL based on the random number data. The clock supply unit 10 changes the cycle of the clock signal CK_CPU based on the control data CTL. Then, the CPU 30 changes the operation timing of the instruction processing by performing the instruction processing with the clock signal CK_CPU whose cycle changes.

  FIG. 3 shows an operation timing chart of the present embodiment.

  The control data generation unit 20 outputs a bit string of random numbers as control data CTL bit by bit from the MSB side (or LSB side). For example, when the random number is hexadecimal “4”, the binary bit string is “0100”, so that the control data CTL is output in the order of “0”, “1”, “0”, “0”. For example, in the example of FIG. 3, one bit is output every two clocks of the clock signal CK_SYS.

  When the control data CTL is “0”, the clock supply unit 10 outputs the clock signal CK_CPU at a reference cycle. In the example of FIG. 3, the cycle is the same as that of the clock signal CK_SYS. On the other hand, when the control data CTL is “1”, the clock signal CK_CPU is output at a cycle slower than the reference cycle. In the example of FIG. 3, the period is half of the reference period, and the second pulse of the two pulses of the clock signal CK_SYS is lost. Since the control data CTL is generated from random number data, the timing at which the cycle is delayed is random.

  Since the CPU 30 operates with the clock signal CK_CPU whose cycle changes at random, the generation timing of the consumption current (IDD) of the microcomputer is also random. Specifically, when the pulse of the clock signal CK_CPU is missing, the instruction process enters the wait state without proceeding to the next step, so that the current consumption is reduced and the timing is random. Correlation can be reduced.

  However, using random numbers has the following problems. As shown in FIG. 4, for example, when random number data of “0000” to “FFFF” is generated in hexadecimal, a 16-bit bit string is generated in binary. If this bit string is used as it is as the control data CTL, the random number data includes “0000” and “FFFF”, and therefore, a maximum of “0” or “1” bits continues 16 times or more.

  When bit “0” continues, since the CPU 30 operates at a normal timing during that period, the correlation between the instruction and the current consumption increases. Therefore, there is a possibility that an algorithm or a password may be hacked by analyzing the current consumption. On the other hand, when the bit “1” continues, the operating frequency of the CPU 30 becomes slow during that time, and the performance (processing speed) of the microcomputer is lowered (or the performance is uneven).

  Therefore, in the present embodiment, the control data generation unit 20 includes a code conversion unit 22, and the code conversion unit 22 processes the random number data to generate control data CTL in which a predetermined number of bits of the same logic are not generated continuously. To do.

  FIG. 5 shows an example of code conversion. In this example, the random number data is converted into a 20-bit bit string, and the control data CTL is generated so that the same logic bit of “0” or “1” does not occur five or more times consecutively. For example, when the random number data is “0000”, the bit “0” only lasts 3 times at maximum, and when the random number data is “FFFF”, the bit “1” only lasts 3 times at maximum. is there.

  In this way, by processing the random number data so that bits of the same logic do not continue for a long time, it is possible to prevent the possibility of hacking due to “0” continuity and performance degradation due to “1” continuation. .

  More specifically, the code conversion unit 22 converts the random number data by the 8b10b method. The 8b10b system is a code conversion method for converting an 8-bit bit string into a 10-bit bit string. In the present embodiment, the MSB side (upper) 8 bits and the LSB side (lower) 8 bits of random number data are converted into 10 bits, respectively, to generate a 20-bit bit string.

  In the 8b10b system, it is possible to output a bit string in which the same logic bits do not continue more than 5 bits. This is not only true when an 8-bit bit string is converted, but also when a bit string of 8 × 2 bits, 8 × 3 bits,... Below bit. That is, in the bit string of the control data CTL obtained by converting the random number data string, the same logic bit can be set to 5 bits at the maximum regardless of the portion. FIG. 5 shows an example of conversion between the random numbers “00” and “FF”. However, when the random number “00” is converted into the bit string “1001110100” in addition to the example shown in FIG. 1010110001 "in some cases. The bit string to be converted is determined so that the same bits do not continue according to the conversion result immediately before. The 8b10b system is described in detail in US Pat. No. 4,486,739.

  The code conversion method is not limited to the above. That is, the random number generator 21 generates random data of n bits (n is a natural number of 2 ≦ n), and the code converter 22 has j bits of the same logic (j is a natural number of 2 ≦ j <n). The random number data is processed so as not to be generated continuously, and m-bit (m is a natural number where n <m) control data CTL may be generated.

  By using such code conversion, the number of bits in which the same logic continues in the control data CTL becomes the number of bits j smaller than the number of bits n of the random number data. That is, since the number of consecutive bits of the same logic can be reduced as compared with the case where the bit string of the random number data is used as it is, it is possible to reduce the correlation between the instruction and the current consumption and to prevent the performance from being deteriorated.

3. Modification of Method for Changing Operation Timing In the above embodiment, the operation timing of CPU 30 is changed by changing the cycle of clock signal CK_CPU supplied to CPU 30, but the method for changing the operation timing is not limited to this.

  FIG. 6 shows a configuration example of a microcomputer when changing the bus access timing.

  The microcomputer includes a clock supply unit 10, a control data generation unit 20, a CPU 30, a ROM 40, a RAM 50, a bus 60, a bus control unit 70, and first to s-th peripherals PH1 to PHs. . In addition, the same code | symbol is attached | subjected about the component same as the component already mentioned above, and description is abbreviate | omitted suitably.

  The bus control unit 70 controls communication via the bus 60 constituted by a data bus, an address bus, or the like. This control enables data transfer and control between the CPU 30 and each unit. In this configuration example, the bus control unit 70 changes the access timing when the CPU 30 accesses the bus 60.

  Specifically, the control data generation unit 20 outputs the above-described bit string control data CTL to the bus control unit 70. The bus control unit 70 performs normal control without changing the access timing when the control data CTL is “0”, and delays the access timing when the control data CTL is “1”.

  For example, it is assumed that data is read from the RAM 50 (main storage device) when the CPU 30 executes an instruction. In this case, the CPU 30 accesses the RAM 50 via the bus 60, but when the control data CTL is "1", the bus control unit 70 delays the access timing. For example, the time from when the access request is received from the CPU 30 to when the RAM 50 is actually accessed is delayed. Alternatively, the access timing is substantially changed by temporarily returning a busy signal to the CPU 30.

  According to the present embodiment, when an instruction to access the RAM 50 and the peripherals PH1 to PHs is executed via the bus 60, the access timing is randomly changed by the random number as described above. As a result, the timing of the instruction processing is randomly changed, so that the correlation between the instruction and the current consumption can be reduced.

4). Clock Supply Unit and Control Data Generation Unit FIG. 7 shows a detailed configuration example of the clock supply unit 10 and the control data generation unit 20.

  The clock supply unit 10 includes a clock gear output unit 170, a clock gear selection register 180, and a clock generation unit 190. The control data generation unit 20 includes an on / off control register 110, a 16-bit random number generation unit 120, a frequency division unit 130, a first 8b10b conversion unit 140, a second 8b10b conversion unit 150, and a selector 160. Including.

  The ON / OFF control register 110 is set with an enable / disable signal for generating control data. When the enable is set, the control data generation unit 20 generates random control data CTL, and when the disable is set, the control data generation unit 20 outputs “0” as the control data CTL.

  The frequency divider 130 is a counter that divides the clock signal CK_CPU by 40, and outputs a shift control signal to the 16-bit random number generator 120 every 40 counts.

  The 16-bit random number generator 120 updates the 16-bit random number data when receiving the shift control signal from the frequency divider 130. The 16-bit random number generation unit 120 is configured by, for example, a linear feedback shift register (LFSR).

  The first 8b10b conversion unit 140 performs code conversion on the MSB side 8-bit first random number data of the 16-bit random number data by the 8b10b method, and the MSB side 10-bit of the 20-bit conversion data. Output as first conversion data. The second 8b10b conversion unit 150 performs code conversion on the LSB side 8-bit second random number data of the 16-bit random number data by the 8b10b method, and the LSB side 10-bit of the 20-bit conversion data. Output as second conversion data.

  The selector 160 selects 20-bit converted data bit by bit from the LSB side based on the count value of the frequency divider 130 and outputs it as control data CTL. The count value of the frequency divider 130 is a decimal number from “0” to “39”, and the selector 160 selects one bit every two counts.

  In the clock gear selection register 180, a signal for selecting a frequency ratio (gear ratio) between the clock signal CK_SYS and the clock signal CK_CPU is set. For example, when setting values 0, 1, 2, and 3 are set, the frequency ratio is set to 1/1, 1/2, 1/4, and 1/8.

  When the control data CTL is “0” (second logic level), the clock gear output unit 170 outputs the set value of the clock gear selection register 180 as it is, and the control data CTL is “1” (first logic level). (Logic level), 1 is added to the set value of the clock gear selection register 180 and output.

  The clock generation unit 190 decelerates the clock signal CK_SYS at a frequency ratio corresponding to the set value from the clock gear output unit 170, and outputs the clock signal CK_CPU. For example, when the setting value of the clock gear selection register 180 is 0, if the control data CTL is “0”, the clock gear output unit 170 outputs the setting value 0, so the clock generation unit 190 has the same frequency as the clock signal CK_SYS. The clock signal CK_CPU is output. On the other hand, if the control data CTL is “1”, the clock gear output unit 170 outputs the set value 0 + 1 = 1, so that the clock generation unit 190 outputs the clock signal CK_CPU having a frequency ½ of the clock signal CK_SYS.

  As described above, the control data CTL can be generated by the selector 160 selecting bit by bit from the 20-bit conversion data. Then, when the control data CTL is “1” (first logic level), the cycle of the clock signal CK_CPU can be increased to generate the clock signal CK_CPU whose cycle changes at random.

  The 8b10b method is a method for converting 8-bit data. However, when 8-bit random number data is used as the input, the number of random numbers is limited. In this regard, 16-bit random number data is generated, and the MSB side 8 bits and LSB side 8 bits are code-converted by the 8b10b method, respectively, to secure the number of random numbers and increase the randomness of the control data. Can do.

  FIG. 8 shows an operation timing chart of the clock supply unit 10 and the control data generation unit 20 described above.

  As indicated by A1, the frequency divider 130 counts up the count value count40 at the rising edge of the clock signal CK_CPU. As indicated by A2, the frequency divider 130 activates the shift control signal shift_en (H level) when the count value count40 is zero. As shown in A3, the 16-bit random number generator 120 updates the random number data LFSRout [15: 0] at the falling edge of the shift control signal shift_en. As shown in A4, the first 8b10b converter 140 and the second 8b10b converter 150 convert the random number data LFSRout [15: 0] into converted data 8b10bout.

  As shown in A5, the selector 160 selects the bit at the position (bit position) 17 when the count value count40 is 34 or 35, for example. Since the bit position is designated by 0 to 19, the bit position 17 is the 18th from the LSB side, and the control data CTL is “0”. As shown in A6, when the setting value cgear_r_in [1: 0] of the clock gear selection register 180 is 0, the clock gear output unit 170 outputs the setting value cgear_r_out [1: 0] = 0 as shown in A7. To do.

  As indicated by A8, the control data CTL is “1” at the next bit position 18 (19th from the LSB side). As indicated by A9, the clock gear output unit 170 outputs the set value cgear_r_out [1: 0] = 1. The set value cgear_r_out [1: 0] changes from 0 to 1 at the rise of the clock signal CK_CPU indicated by A10. At the next rising edge indicated by A11, the clock generation unit 190 switches the frequency ratio. That is, the cycle of the clock signal CK_CPU actually changes after one clock from the change of the logic level of the control data CTL.

5. Electronic Device FIGS. 9 and 10 show configuration examples of electronic devices to which the microcomputer of this embodiment can be applied. In the following description, the case where the present invention is applied to a security token will be described as an example. However, the present invention is not limited to this, and the microcomputer of this embodiment can be applied to various electronic devices.

  The electronic device 200 includes a display unit 210, a microcomputer 220 (integrated circuit device), an operation unit 230, a storage unit 240, and a communication unit 250.

  When the user performs a specific operation on the electronic device 200, the microcomputer 220 calculates security information such as a one-time password and causes the display unit 210 to display the security information.

  For example, in the case of a token that is synchronized with the server, when the user connects the terminal and the electronic device 200 by contact or non-contact communication, the communication unit 250 communicates with the terminal to acquire, for example, key information from the server, The microcomputer 220 calculates security information using the key information.

  Alternatively, in the case of a token that issues security information independently, for example, common key information is stored in the storage unit 240, and when the user operates the operation unit 230 (for example, presses a button), the microcomputer 220 The common key information is read from 240, and the security information is calculated using the common key information.

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, a term described at least once together with a different term having a broader meaning or the same meaning in the specification or the drawings can be replaced with the different term in any part of the specification or the drawings. All combinations of the present embodiment and the modified examples are also included in the scope of the present invention. The configuration and operation of the clock supply unit, the control data generation unit, the CPU, the microcomputer, and the electronic device are not limited to those described in this embodiment, and various modifications can be made.

10 clock supply unit, 20 control data generation unit, 21 random number generation unit,
22 code conversion unit, 30 CPU, 40 ROM, 50 RAM, 60 bus,
70 bus control unit, 110 on / off control register,
130 divider, 140 first 8b10b converter,
150 second 8b10b converter, 160 selector,
170 clock gear output section, 180 clock gear selection register,
190 clock generation unit, 200 electronic device, 210 display unit,
220 microcomputer, 230 operation unit, 240 storage unit,
250 communications department,
CK_CPU, CK_SYS clock signal, CTL control data,
IDD current consumption

Claims (7)

A processing unit for performing an instruction process;
A control data generating unit for generating control data for changing the operation timing of the instruction processing;
Including
The control data generation unit
A random number generator for generating random data;
A code conversion unit including an 8b10b conversion unit that generates the control data in which a predetermined number of bits of the same logic are not generated consecutively by converting the random number data by the 8b10b method;
Have
The processor is
A microcomputer that performs the instruction process in which the operation timing changes based on the control data. In claim 1,
A clock supply unit that supplies the processing unit with a clock signal having a cycle changed based on the control data;
The microcomputer in which the operation timing of the instruction processing is changed by the processing unit performing the instruction processing based on the clock signal from the clock supply unit. In claim 2,
The clock supply unit
A microcomputer for increasing the period of the clock signal when the control data is at a first logic level. In claim 1,
Including bus control unit,
The microcomputer in which the bus control unit changes the operation timing of the instruction processing by changing an access timing when the processing unit accesses the bus based on the control data. A processing unit for performing an instruction process;
A control data generating unit for generating control data for changing the operation timing of the instruction processing;
Including
The control data generation unit
a random number generator for generating random data of n bits (n is a natural number of 2 ≦ n);
A code conversion unit that processes the random number data and generates the control data that does not continuously generate a predetermined number of bits of the same logic;
Have
The code converter is
A first 8b10b conversion unit to which n / 2-bit first random number data on the MSB side of the n-bit random number data is input;
A second 8b10b converter to which n / 2-bit second random number data on the LSB side of the n-bit random number data is input;
The control data is selected one by one from the conversion data composed of the first conversion data from the first 8b10b conversion unit and the second conversion data from the second 8b10b conversion unit. A selector to output,
Have
The processor is
A microcomputer that performs the instruction process in which the operation timing changes based on the control data. In claim 5,
A clock supply unit for supplying a clock signal to the processing unit;
The clock supply unit
A microcomputer that increases the period of the clock signal when a bit selected by the selector has a first logic level. An electronic apparatus comprising a microcomputer according to any of claims 1 to 6.

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