JP2010536159A - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

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Publication number
JP2010536159A
JP2010536159A JP2009519684A JP2009519684A JP2010536159A JP 2010536159 A JP2010536159 A JP 2010536159A JP 2009519684 A JP2009519684 A JP 2009519684A JP 2009519684 A JP2009519684 A JP 2009519684A JP 2010536159 A JP2010536159 A JP 2010536159A
Authority
JP
Japan
Prior art keywords
barrier metal
metal layer
layer
platinum group
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2009519684A
Other languages
English (en)
Japanese (ja)
Other versions
JP2010536159A5 (https=
Inventor
喜明 垂水
真一 小川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Panasonic Holdings Corp
Original Assignee
Panasonic Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp, Matsushita Electric Industrial Co Ltd filed Critical Panasonic Corp
Publication of JP2010536159A publication Critical patent/JP2010536159A/ja
Publication of JP2010536159A5 publication Critical patent/JP2010536159A5/ja
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/42—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a gas or vapour
    • H10P14/44—Physical vapour deposition [PVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H10W20/035—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425—Barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/047—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by introducing additional elements therein
    • H10W20/051—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by introducing additional elements therein by ion implantation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Physical Vapour Deposition (AREA)
  • Electrodes Of Semiconductors (AREA)
JP2009519684A 2007-08-03 2008-07-29 半導体装置及びその製造方法 Withdrawn JP2010536159A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007202965 2007-08-03
PCT/JP2008/002019 WO2009019827A1 (en) 2007-08-03 2008-07-29 Semiconductor device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JP2010536159A true JP2010536159A (ja) 2010-11-25
JP2010536159A5 JP2010536159A5 (https=) 2011-09-15

Family

ID=39869726

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009519684A Withdrawn JP2010536159A (ja) 2007-08-03 2008-07-29 半導体装置及びその製造方法

Country Status (3)

Country Link
US (1) US20100007022A1 (https=)
JP (1) JP2010536159A (https=)
WO (1) WO2009019827A1 (https=)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012131756A1 (en) 2011-03-28 2012-10-04 Hitachi, Ltd. Computer system and computer system management method
US10796996B2 (en) 2017-03-10 2020-10-06 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method of forming the same
CN109148356A (zh) * 2017-06-15 2019-01-04 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
US11322502B2 (en) * 2019-07-08 2022-05-03 Micron Technology, Inc. Apparatus including barrier materials within access line structures, and related methods and electronic systems

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3528665B2 (ja) * 1998-10-20 2004-05-17 セイコーエプソン株式会社 半導体装置の製造方法
JP2002075994A (ja) * 2000-08-24 2002-03-15 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
US6703307B2 (en) * 2001-11-26 2004-03-09 Advanced Micro Devices, Inc. Method of implantation after copper seed deposition
KR100805843B1 (ko) * 2001-12-28 2008-02-21 에이에스엠지니텍코리아 주식회사 구리 배선 형성방법, 그에 따라 제조된 반도체 소자 및구리 배선 형성 시스템
US20050206000A1 (en) * 2004-03-19 2005-09-22 Sanjeev Aggarwal Barrier for copper integrated circuits
US7453149B2 (en) * 2004-08-04 2008-11-18 Taiwan Semiconductor Manufacturing Co., Ltd. Composite barrier layer
US7446033B2 (en) * 2005-01-25 2008-11-04 Samung Electronics Co., Ltd. Method of forming a metal interconnection of a semiconductor device, and metal interconnection formed by such method
DE102005023122A1 (de) * 2005-05-19 2006-11-23 Infineon Technologies Ag Integrierte Schaltungsanordnung mit Schichtstapel und Verfahren
US7550385B2 (en) * 2005-09-30 2009-06-23 Intel Corporation Amine-free deposition of metal-nitride films

Also Published As

Publication number Publication date
US20100007022A1 (en) 2010-01-14
WO2009019827A1 (en) 2009-02-12

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