JP2010530660A5 - - Google Patents

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Publication number
JP2010530660A5
JP2010530660A5 JP2010510350A JP2010510350A JP2010530660A5 JP 2010530660 A5 JP2010530660 A5 JP 2010530660A5 JP 2010510350 A JP2010510350 A JP 2010510350A JP 2010510350 A JP2010510350 A JP 2010510350A JP 2010530660 A5 JP2010530660 A5 JP 2010530660A5
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JP
Japan
Prior art keywords
multiplexer
representation
multiplexers
medium
logic
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JP2010510350A
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English (en)
Japanese (ja)
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JP2010530660A (ja
JP5384483B2 (ja
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Priority claimed from US11/809,613 external-priority patent/US7730438B2/en
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Publication of JP2010530660A5 publication Critical patent/JP2010530660A5/ja
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Publication of JP5384483B2 publication Critical patent/JP5384483B2/ja
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JP2010510350A 2007-05-31 2008-05-30 マルチプレクサを設計する方法及び装置 Active JP5384483B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/809,613 2007-05-31
US11/809,613 US7730438B2 (en) 2007-05-31 2007-05-31 Methods and apparatuses for designing multiplexers
PCT/US2008/006831 WO2008150435A1 (en) 2007-05-31 2008-05-30 Methods and apparatuses for designing multiplexers

Publications (3)

Publication Number Publication Date
JP2010530660A JP2010530660A (ja) 2010-09-09
JP2010530660A5 true JP2010530660A5 (https=) 2011-07-21
JP5384483B2 JP5384483B2 (ja) 2014-01-08

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Family Applications (1)

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JP2010510350A Active JP5384483B2 (ja) 2007-05-31 2008-05-30 マルチプレクサを設計する方法及び装置

Country Status (5)

Country Link
US (1) US7730438B2 (https=)
EP (1) EP2153360A1 (https=)
JP (1) JP5384483B2 (https=)
CN (1) CN101790730B (https=)
WO (1) WO2008150435A1 (https=)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8751986B2 (en) * 2010-08-06 2014-06-10 Synopsys, Inc. Method and apparatus for automatic relative placement rule generation
JP6127807B2 (ja) * 2013-07-26 2017-05-17 富士通株式会社 送信回路、通信システム及び通信方法
US9361417B2 (en) 2014-02-07 2016-06-07 Synopsys, Inc. Placement of single-bit and multi-bit flip-flops
JP6735095B2 (ja) * 2015-12-25 2020-08-05 ザインエレクトロニクス株式会社 信号多重化装置
US10528692B1 (en) 2017-11-07 2020-01-07 Synopsis, Inc. Cell-aware defect characterization for multibit cells
US12387022B2 (en) * 2022-03-02 2025-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method of optimizing an integrated circuit design

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3060018B2 (ja) * 1988-10-05 2000-07-04 クイックターン デザイン システムズ インコーポレイテッド 複数の電気的に再構成可能なゲートアレイを用いて論理構成を構築する方法
US6505337B1 (en) * 1998-11-24 2003-01-07 Xilinx, Inc. Method for implementing large multiplexers with FPGA lookup tables
US6438735B1 (en) 1999-05-17 2002-08-20 Synplicity, Inc. Methods and apparatuses for designing integrated circuits
US6449762B1 (en) 1999-10-07 2002-09-10 Synplicity, Inc. Maintaining correspondence between text and schematic representations of circuit elements in circuit synthesis
US6711729B1 (en) * 2000-12-05 2004-03-23 Synplicity, Inc. Methods and apparatuses for designing integrated circuits using automatic reallocation techniques
US6973632B1 (en) 2002-06-11 2005-12-06 Synplicity, Inc. Method and apparatus to estimate delay for logic circuit optimization
US7506278B1 (en) * 2005-03-08 2009-03-17 Xilinx, Inc. Method and apparatus for improving multiplexer implementation on integrated circuits

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