JP2010511943A5 - - Google Patents

Download PDF

Info

Publication number
JP2010511943A5
JP2010511943A5 JP2009539576A JP2009539576A JP2010511943A5 JP 2010511943 A5 JP2010511943 A5 JP 2010511943A5 JP 2009539576 A JP2009539576 A JP 2009539576A JP 2009539576 A JP2009539576 A JP 2009539576A JP 2010511943 A5 JP2010511943 A5 JP 2010511943A5
Authority
JP
Japan
Prior art keywords
address
type
identification
semiconductor device
serial input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2009539576A
Other languages
Japanese (ja)
Other versions
JP2010511943A (en
JP5683813B2 (en
Filing date
Publication date
Priority claimed from US11/622,828 external-priority patent/US8271758B2/en
Priority claimed from US11/771,241 external-priority patent/US7925854B2/en
Application filed filed Critical
Priority claimed from PCT/CA2007/002182 external-priority patent/WO2008067658A1/en
Publication of JP2010511943A publication Critical patent/JP2010511943A/en
Publication of JP2010511943A5 publication Critical patent/JP2010511943A5/ja
Application granted granted Critical
Publication of JP5683813B2 publication Critical patent/JP5683813B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Claims (17)

混合されたタイプの複数のデバイスのシリアル相互接続構成で使用される半導体デバイスであって、
前記複数のデバイスが、シリアル相互接続され、前記シリアル相互接続構成の第1デバイスが、シリアル入力を受け取り、前記シリアル入力が、前記シリアル相互接続構成を介して伝搬され、前記シリアル入力が、デバイスタイプ識別、コマンド、およびデバイスアドレス識別を含み、前記デバイスが、前記デバイスタイプ識別および前記デバイスアドレス識別に基づいて前記コマンドを実行する、半導体デバイス。
A semiconductor device used in a serial interconnect configuration of multiple devices of mixed type,
The plurality of devices are serially interconnected, a first device of the serial interconnect configuration receives a serial input, the serial input is propagated through the serial interconnect configuration, and the serial input is a device type A semiconductor device comprising an identification, a command, and a device address identification, wherein the device executes the command based on the device type identification and the device address identification.
前記デバイスの前記タイプを示すデバイスタイプを保持するデバイスタイプホルダと、
デバイスアドレスを保持するアドレスホルダであって、割り当てられたアドレスが、前記デバイスのアドレスを示す、アドレスホルダと
をさらに含む、請求項1に記載の半導体デバイス。
A device type holder for holding a device type indicating the type of the device;
The semiconductor device according to claim 1, further comprising: an address holder that holds a device address, wherein the assigned address indicates an address of the device.
前記デバイスタイプ識別が前記デバイスタイプホルダによって保持される前記デバイスタイプと一致するかどうかを判定するタイプ一致デターミナであって、それぞれ、前記デバイスタイプ識別が前記保持されるデバイスタイプと一致する場合にデバイスタイプ一致結果を、前記デバイスタイプ識別が前記保持されるデバイスタイプと一致しない場合に非デバイスタイプ一致結果を提供することができる、タイプ一致デターミナと、
前記デバイスアドレス識別が前記アドレスホルダによって保持される前記デバイスアドレスと一致するかどうかを判定するアドレス一致デターミナであって、それぞれ、前記デバイスアドレス識別が前記保持されるデバイスアドレスと一致する場合にアドレス一致結果を、前記デバイスアドレス識別が前記保持されるデバイスアドレスと一致しない場合に非デバイスアドレス一致結果を提供することができる、アドレス一致デターミナと
をさらに含む、請求項2に記載の半導体デバイス。
A type match determiner that determines whether the device type identification matches the device type held by the device type holder, each device if the device type identification matches the held device type A type match determiner that can provide a non-device type match result if the device type identification does not match the retained device type; and
An address match determiner that determines whether the device address identification matches the device address held by the address holder, each address match if the device address identification matches the held device address 3. The semiconductor device of claim 2, further comprising: an address match determiner that can provide a non-device address match result if the device address identification does not match the retained device address.
前記受け取られたシリアル入力に応答して前記デバイスの動作を制御し、
前記デバイスタイプ一致結果および前記アドレス一致結果に応答して、前記受け取られたシリアル入力に含まれる前記コマンドを実行する
デバイスコントローラをさらに含む、請求項3に記載の半導体デバイス。
Controlling the operation of the device in response to the received serial input;
4. The semiconductor device according to claim 3, further comprising a device controller that executes the command included in the received serial input in response to the device type match result and the address match result.
前記シリアル入力が、アドレス番号を含むデータ情報をさらに含み、
前記デバイスコントローラが、
前記デバイスタイプ一致結果および前記デバイスアドレス一致結果に応答して前記アドレス番号を変更し、
前記シリアル入力に含まれる前記データ情報を前記シリアル相互接続構成の次のデバイスに転送する
ことができる
請求項4に記載の半導体デバイス。
The serial input further includes data information including an address number;
The device controller is
Changing the address number in response to the device type match result and the device address match result;
5. The semiconductor device according to claim 4, wherein the data information included in the serial input can be transferred to a next device of the serial interconnection configuration.
前記データ情報の前記受け取られたアドレス番号が、前記アドレスホルダ内で保持され、前記デバイスの前記アドレスを示す、請求項5に記載の半導体デバイス。   6. The semiconductor device of claim 5, wherein the received address number of the data information is held in the address holder and indicates the address of the device. 前記変更されたアドレス番号が、前記アドレスホルダ内で保持され、前記デバイスの前記アドレスを示す、請求項5に記載の半導体デバイス。   6. The semiconductor device of claim 5, wherein the changed address number is held in the address holder and indicates the address of the device. 前記デバイスコントローラが、前記データ情報の前記受け取られたアドレス番号および所定の番号に基づく算術計算を実行することによって前記アドレス番号を変更する、請求項5に記載の半導体デバイス。   6. The semiconductor device of claim 5, wherein the device controller changes the address number by performing an arithmetic calculation based on the received address number and a predetermined number of the data information. 前記デバイスコントローラによる前記算術計算が、前記受け取られたアドレス番号と前記所定の番号との加算を含む、請求項8に記載の半導体デバイス。   9. The semiconductor device according to claim 8, wherein the arithmetic calculation by the device controller includes addition of the received address number and the predetermined number. 前記所定の番号が、1であり、前記変更されたアドレス番号が、前記アドレス番号の1による増分を含む、請求項9に記載の半導体デバイス。   10. The semiconductor device according to claim 9, wherein the predetermined number is 1, and the changed address number includes an increment by 1 of the address number. 前記デバイスコントローラによる前記算術計算が、前記アドレス番号と前記所定の番号との減算を含む、請求項8に記載の半導体デバイス。   9. The semiconductor device according to claim 8, wherein the arithmetic calculation by the device controller includes subtraction between the address number and the predetermined number. 前記所定の番号が、1であり、前記変更されたアドレス番号が、前記アドレス番号の1による減分を含む、請求項11に記載の半導体デバイス。   12. The semiconductor device according to claim 11, wherein the predetermined number is 1, and the changed address number includes a decrement by 1 of the address number. 前記アドレスホルダが、所期のアドレス番号を保持し、
前記シリアル入力に含まれる前記デバイスアドレス識別が、前記所期のアドレス番号を含み、
前記シリアル入力に含まれる前記データ情報の前記アドレス番号が、初期アドレス番号を含み、
前記デバイスコントローラが、前記アドレス一致結果に応答して前記初期アドレス番号を変更することができ、変更されたアドレス番号が、前記アドレスホルダ内に保持される前記所期のアドレス番号を置換する
請求項5に記載の半導体デバイス。
The address holder holds an intended address number;
The device address identification included in the serial input includes the intended address number;
The address number of the data information included in the serial input includes an initial address number;
The device controller can change the initial address number in response to the address match result, and the changed address number replaces the intended address number held in the address holder. 5. The semiconductor device according to 5.
前記デバイスコントローラが、前記非デバイスタイプ一致結果および前記非デバイスアドレス一致結果のうちのいずれか1つに応答して、前記シリアル相互接続構成の次のデバイスに、前記受け取られたシリアル入力の前記デバイスタイプ識別、前記コマンド、および前記デバイスアドレス識別を転送する、請求項13に記載の半導体デバイス。   The device controller is responsive to any one of the non-device type match result and the non-device address match result to the next device in the serial interconnect configuration to receive the device of the received serial input 14. The semiconductor device of claim 13, which transfers a type identification, the command, and the device address identification. 前記デバイスが、メモリを含み、
前記シリアル入力に含まれる前記データ情報が、前記メモリに関する情報データをさらに含み、
前記デバイスコントローラが、前記デバイスタイプ一致結果および前記デバイスアドレス一致結果に応答して、前記メモリにアクセスするために、前記メモリ関連情報データに基づいて前記コマンドを実行することができる
請求項13に記載の半導体デバイス。
The device includes a memory;
The data information included in the serial input further includes information data relating to the memory;
The device controller can execute the command based on the memory-related information data to access the memory in response to the device type match result and the device address match result. Semiconductor devices.
前記デバイスコントローラが、前記非デバイスタイプ一致結果および前記非デバイスアドレス一致結果のいずれかに応答して、前記シリアル相互接続構成の次のデバイスに、前記受け取られたシリアル入力に含まれる前記デバイスタイプ識別、前記デバイスアドレス識別、前記コマンド、および前記データを転送することがさらにできる、請求項15に記載の半導体デバイス。   In response to either the non-device type match result and the non-device address match result, the device controller identifies the device type identification included in the received serial input to the next device in the serial interconnect configuration. 16. The semiconductor device of claim 15, further capable of transferring the device address identification, the command, and the data. 前記メモリが、NANDフラッシュEEPROM、NORフラッシュEEPROM、ANDフラッシュEEPROM、DiNORフラッシュEEPROM、シリアルフラッシュEEPROM、DRAM、SRAM、ROM、EPROM、FRAM、MRAM、およびPCRAMのうちのいずれか1つを含む、請求項15に記載の半導体デバイス。   The memory includes any one of NAND flash EEPROM, NOR flash EEPROM, AND flash EEPROM, DiNOR flash EEPROM, serial flash EEPROM, DRAM, SRAM, ROM, EPROM, FRAM, MRAM, and PCRAM. 15. The semiconductor device according to 15.
JP2009539576A 2006-12-06 2007-12-04 System and method for operating mixed types of memory devices Expired - Fee Related JP5683813B2 (en)

Applications Claiming Priority (9)

Application Number Priority Date Filing Date Title
US86877306P 2006-12-06 2006-12-06
US60/868,773 2006-12-06
US87089206P 2006-12-20 2006-12-20
US60/870,892 2006-12-20
US11/622,828 2007-01-12
US11/622,828 US8271758B2 (en) 2006-12-06 2007-01-12 Apparatus and method for producing IDS for interconnected devices of mixed type
US11/771,241 2007-06-29
US11/771,241 US7925854B2 (en) 2006-12-06 2007-06-29 System and method of operating memory devices of mixed type
PCT/CA2007/002182 WO2008067658A1 (en) 2006-12-06 2007-12-04 System and method of operating memory devices of mixed type

Related Child Applications (2)

Application Number Title Priority Date Filing Date
JP2010257825A Division JP5351130B2 (en) 2006-12-06 2010-11-18 System and method for operating mixed types of memory devices
JP2013257579A Division JP5695724B2 (en) 2006-12-06 2013-12-13 System and method for operating mixed types of memory devices

Publications (3)

Publication Number Publication Date
JP2010511943A JP2010511943A (en) 2010-04-15
JP2010511943A5 true JP2010511943A5 (en) 2011-01-20
JP5683813B2 JP5683813B2 (en) 2015-03-11

Family

ID=39491613

Family Applications (3)

Application Number Title Priority Date Filing Date
JP2009539576A Expired - Fee Related JP5683813B2 (en) 2006-12-06 2007-12-04 System and method for operating mixed types of memory devices
JP2010257825A Expired - Fee Related JP5351130B2 (en) 2006-12-06 2010-11-18 System and method for operating mixed types of memory devices
JP2013257579A Expired - Fee Related JP5695724B2 (en) 2006-12-06 2013-12-13 System and method for operating mixed types of memory devices

Family Applications After (2)

Application Number Title Priority Date Filing Date
JP2010257825A Expired - Fee Related JP5351130B2 (en) 2006-12-06 2010-11-18 System and method for operating mixed types of memory devices
JP2013257579A Expired - Fee Related JP5695724B2 (en) 2006-12-06 2013-12-13 System and method for operating mixed types of memory devices

Country Status (5)

Country Link
EP (1) EP2118903A4 (en)
JP (3) JP5683813B2 (en)
KR (3) KR101441154B1 (en)
TW (1) TWI470645B (en)
WO (1) WO2008067658A1 (en)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8463959B2 (en) * 2010-05-31 2013-06-11 Mosaid Technologies Incorporated High-speed interface for daisy-chained devices
TWI425362B (en) * 2010-12-07 2014-02-01 Alpha Imaging Technology Corp Memory interface chip corresponding to different memories and method of establishing memory transmission channel
US9697872B2 (en) * 2011-12-07 2017-07-04 Cypress Semiconductor Corporation High speed serial peripheral interface memory subsystem
US8614920B2 (en) 2012-04-02 2013-12-24 Winbond Electronics Corporation Method and apparatus for logic read in flash memory
JP5467134B1 (en) * 2012-09-27 2014-04-09 華邦電子股▲ふん▼有限公司 Flash memory device and method of operating memory device
US10067903B2 (en) 2015-07-30 2018-09-04 SK Hynix Inc. Semiconductor device
US11755255B2 (en) 2014-10-28 2023-09-12 SK Hynix Inc. Memory device comprising a plurality of memories sharing a resistance for impedance matching
KR102366767B1 (en) * 2015-07-30 2022-02-23 에스케이하이닉스 주식회사 Semiconductor device
KR102358177B1 (en) 2015-12-24 2022-02-07 에스케이하이닉스 주식회사 Control circuit and memory device including the control circuit
US10146608B2 (en) * 2015-04-06 2018-12-04 Rambus Inc. Memory module register access
FR3041806B1 (en) * 2015-09-25 2017-10-20 Stmicroelectronics Rousset NON-VOLATILE MEMORY DEVICE, FOR EXAMPLE OF THE EEPROM TYPE, HAVING IMPORTANT MEMORY CAPACITY, FOR EXAMPLE 16MBITS
GB2568725B (en) * 2017-11-24 2021-08-18 Ge Aviat Systems Ltd Method and apparatus for initializing a controller module
GB2568724B (en) * 2017-11-24 2021-08-18 Ge Aviat Systems Ltd Method and apparatus for initializing a controller module
CN110413197B (en) * 2018-04-28 2023-06-27 伊姆西Ip控股有限责任公司 Method, apparatus and computer program product for managing a storage system
TWI696113B (en) * 2019-01-02 2020-06-11 慧榮科技股份有限公司 Method for performing configuration management, and associated data storage device and controller thereof
US20210081318A1 (en) * 2019-09-17 2021-03-18 Micron Technology, Inc. Flexible provisioning of multi-tier memory
TWI749598B (en) * 2020-06-18 2021-12-11 華邦電子股份有限公司 Memory apparatus and method of burst read and burst write thereof
US11120851B1 (en) 2020-07-12 2021-09-14 Winbond Electronics Corp. Memory apparatus and burst read and burst write method thereof
CN113641595B (en) * 2021-07-30 2023-08-11 珠海一微半导体股份有限公司 Type identification method and system of SPI FLASH in BROM stage of independent block protection mode

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4360870A (en) * 1980-07-30 1982-11-23 International Business Machines Corporation Programmable I/O device identification
IL96808A (en) * 1990-04-18 1996-03-31 Rambus Inc Integrated circuit i/o using a high performance bus interface
JPH0484351A (en) * 1990-07-27 1992-03-17 Sony Corp Address setting method
JPH07105121A (en) * 1993-09-30 1995-04-21 Nabco Ltd Decentralized controller
JP3168552B2 (en) * 1993-12-17 2001-05-21 インターナショナル・ビジネス・マシーンズ・コーポレ−ション Memory access control system and method
US5404460A (en) * 1994-01-28 1995-04-04 Vlsi Technology, Inc. Method for configuring multiple identical serial I/O devices to unique addresses through a serial bus
US5636342A (en) * 1995-02-17 1997-06-03 Dell Usa, L.P. Systems and method for assigning unique addresses to agents on a system management bus
US5708773A (en) * 1995-07-20 1998-01-13 Unisys Corporation JTAG interface system for communicating with compliant and non-compliant JTAG devices
US5860080A (en) * 1996-03-19 1999-01-12 Apple Computer, Inc. Multicasting system for selecting a group of memory devices for operation
JP3850067B2 (en) * 1996-04-24 2006-11-29 株式会社ルネサステクノロジ Memory system and semiconductor memory device used therefor
US6175891B1 (en) * 1997-04-23 2001-01-16 Micron Technology, Inc. System and method for assigning addresses to memory devices
US6453365B1 (en) * 1998-02-11 2002-09-17 Globespanvirata, Inc. Direct memory access controller having decode circuit for compact instruction format
US6144576A (en) * 1998-08-19 2000-11-07 Intel Corporation Method and apparatus for implementing a serial memory architecture
US7356639B2 (en) * 2000-01-05 2008-04-08 Rambus Inc. Configurable width buffered module having a bypass circuit
JP2002236611A (en) * 2000-12-04 2002-08-23 Hitachi Ltd Semiconductor device and information processing system
US6996644B2 (en) * 2001-06-06 2006-02-07 Conexant Systems, Inc. Apparatus and methods for initializing integrated circuit addresses
US7073022B2 (en) * 2002-05-23 2006-07-04 International Business Machines Corporation Serial interface for a data storage array
US7032039B2 (en) * 2002-10-30 2006-04-18 Atmel Corporation Method for identification of SPI compatible serial memory devices
US7308524B2 (en) * 2003-01-13 2007-12-11 Silicon Pipe, Inc Memory chain
WO2005039113A1 (en) * 2003-10-18 2005-04-28 Samsung Electronics Co., Ltd. Method and system for discovering a mobility anchor point and managing mobility of a mobile node in a network system supporting mobile ip
US7031221B2 (en) * 2003-12-30 2006-04-18 Intel Corporation Fixed phase clock and strobe signals in daisy chained chips
US8375146B2 (en) * 2004-08-09 2013-02-12 SanDisk Technologies, Inc. Ring bus structure and its use in flash memory systems

Similar Documents

Publication Publication Date Title
JP2010511943A5 (en)
TWI629686B (en) Apparatuses and methods for concurrently accessing multiple partitions of a non-volatile memory
JP5901759B2 (en) Method, apparatus and system for determining an identifier of a volume of memory
CN105702277B (en) Accumulator system and Memory Controller
CN103366801B (en) Storage arrangement and its operating method
JP6869885B2 (en) Devices and methods for simultaneously accessing memory planes with different memories
JP2012181916A5 (en)
TWI493350B (en) High priority command queue for peripheral component
US20190050261A1 (en) Arbitration across shared memory pools of disaggregated memory devices
CN107636618B (en) Immediate restart in a non-volatile system memory computing system with embedded programmable data checking
US20160266928A1 (en) Task queues
US10581968B2 (en) Multi-node storage operation
JP2012104110A5 (en)
KR102395477B1 (en) Device controller that schedules memory accesses to a host memory, and storage device including the same
US20110096611A1 (en) Semiconductor device and semiconductor system having the same
EP2788985A1 (en) Independent write and read control in serially-connected devices
JP2004164633A5 (en)
KR20110014919A (en) Non-volatile memory system and interleave unit configuaration method thereof
JP2008158955A5 (en)
JP5533963B2 (en) Memory module with configurable input / output ports
CN108780421A (en) For the technology in memory device mirroring command/address or interpretation command/address logic
TWI634429B (en) Multi-memory collaboration structure based on spi interface
KR102219759B1 (en) Storage device, data storage system having the same, and operation method thereof
CN106293491B (en) The processing method and Memory Controller Hub of write request
TW201735032A (en) Memory system and method of controlling the same