KR101441154B1 - System and method of operating memory devices of mixed type - Google Patents

Abstract

A memory system architecture is provided in which a memory controller controls memory devices in a serial interconnect configuration. The memory controller has an output port for sending memory commands and an input port for receiving a memory response to those memory commands and requesting such a response. Each memory device includes, for example, a NAND type flash memory, a NOR type flash memory, a random access memory, and a static random access memory. Each memory command is specific to the memory type of the target memory device. The data paths for memory instructions and memory responses are provided by interconnections. The given memory command rounds the memory devices to reach the intended memory device of the serial interconnect configuration. Upon receipt of a memory command, the intended memory device executes the given memory command and sends the memory response to the next suitable memory device. The memory response is sent to the memory controller.

Description

[0001] SYSTEM AND METHOD FOR OPERATING MEMORY DEVICES OF MIXED TYPE [0002]

This application claims the benefit of U.S. Provisional Patent Application No. 60 / 868,773, filed December 6, 2006, the disclosure of which is hereby expressly incorporated by reference in its entirety, U.S. Provisional Patent Application No. 60 / 870,892 filed on December 20, 2006 , U.S. Patent Application No. 11 / 622,828, filed January 12, 2007, U.S. Patent Application No. 11 / 771,241, filed June 29, 2007, the entire contents of which are incorporated herein by reference.

The present invention relates generally to semiconductor device systems. More particularly, the present invention relates to an apparatus and method for controlling a semiconductor device, such as a memory system having memory devices of various or mixed types, for example.

Computer-based systems include, for example, semiconductor devices such as memory devices and processing devices. The memory is a place where information is stored while waiting for it to be driven by a CPU (Central Processing Unit) of the computer. The memory is controlled by the memory controller and may form part of the CPU or be detached from the CPU. The memory controller has an interface with memory to send and receive information. The well-known interface includes a parallel interface and a serial interface.

The parallel interface uses multiple pins for reading and writing data. However, as the number of input pins and wires increases, undesirable effects also increase. These undesirable effects include inter-symbol interface, signal skew and crosstalk. Therefore, in the technology, a memory module having an increased memory capacity and / or operating speed while minimizing the number of input pins and wires for accessing the memory module is required.

The serial interface uses fewer pins to read and write data. Serial flash memories are currently available, but tend to be very slow. For example, many conventional memories use a serial bus interface method that operates in the range of 1 MHz to 20 MHz with an SPI (Serial Peripheral Interface) or PC (Inter-Integrated Circuit) compatible interface. However, these serial interface standards are typically slower than their parallel interface standards.

Referring now to Figures 1A, 1B, 1C and 1D, a block diagram of four primary flash memory structures is shown. The four primary flash memory structures include a conventional XIP model as shown in FIG. 1A, a shadow model as shown in FIG. 1B, a save-download model with a NAND as shown in FIG. 1C, And a new storage-download model with a hybrid NAND flash memory as shown in FIG.

1A, a conventional XIP model includes a volatile memory 103 such as a static random access memory (SRAM) or a dynamic random access memory (DRAM) connected to the application processor 101, a volatile memory 103 such as a NOR flash memory 102, . In the XIP model, the NOR flash memory 102 executes the code while the volatile memory 103 occupies continuously changing system elements such as variables, stacks, and hits. In the XIP model, the NOR flash memory 102 may also provide data and code storage. The advantage of the XIP model is that it is simple, but its disadvantage is slower recording speeds.

1B, the shadow model has a volatile memory 107 such as a NOR flash memory 105, a NAND flash memory 106, an SRAM, or a DRAM connected to the application processor 104. The user starts the system with the NOR flash memory 105 and uses the NAND flash memory 106 for storage. Volatile memory 107 handles all executions. The shadow model is a costly model that uses relatively expensive NOR flash memory 105 to boot the system only. The structure is also a bit more complicated, which means more design time and cost. The shadow model also tends to be power consuming because volatile memory is continuously active.

For example, to overcome the space problem, which is a major factor in mobile handheld devices, a store-download structure is used as shown in FIG. 1C. The save-download architecture has a volatile memory 111 such as a NAND flash memory 110, SRAM, or DRAM connected to the application processor 108. The save-download architecture does not have NOR flash memory, but there is a one-time-programmable (OTP) storage medium 109 or ROM (Read Only Memory) core designed as an application processor 108. The application processor 108 loads information into the volatile memory 111 and accesses the NAND flash memory 110 for data storage. The structure is slightly more complex and requires more initial engineering costs, but ultimately the system cost is less expensive. The main difficulty of this model is that users have to use expensive error-correction and error-detection coding because NAND flash memory is generally less reliable. Storage and downloading designs tend to require more power because RAM is more active.

Referring to FIG. 1D, the hybrid storage and download model has a hybrid NAND flash memory 113 connected to the application processor 112, a volatile memory 114 such as SRAM or DRAM. The hybrid NAND flash memory 113 mixes SRAM, control logic, and NAND flash memory to create a memory device to look like a NOR flash device. The hybrid model reads faster than a standard NAND flash device, at the same rate as a NOR flash device. In addition, this provides better recording performance than NOR flash devices. Hybrid NAND flash memory is now available. Hybrid models require less error correction and error detection coding than storage-download models with standard NAND flash memory. The price of hybrid NAND flash memory is, for example, 30 to 40% less than that of NOR flash memory of the same density. The cost of stand-alone NAND flash memory is slightly less than that of hybrid NAND flash memory.

Memory systems that use one of the four major flash memory architectures require more time in engineering design, software development, and verification.

According to a widespread configuration, there is provided a system or apparatus comprising a modified or mixed type of memory device, wherein the memory devices are serially interconnected so that the input data is transferred serially from the device to the device.

According to another embodiment of the present invention, there is provided a semiconductor device for use in a serial interconnection configuration of a plurality of devices of a mixed type in which a plurality of devices are interconnected in series. A first device in the serial interconnection configuration receives the serial input. The serial input is passed through a serial interconnection configuration. Serial input includes device type identification, command and device address identification. The device executes the command based on the device type identification and the device address identification.

The semiconductor device may include a device controller that controls operation of the device in response to the received serial input.

For example, a semiconductor device may be a device type holder that holds a device type identification, wherein the held type identification is provided to indicate a type of device; And an address holder for holding an assigned device address in response to the provided serial input, wherein the assigned address is provided for display of an address of the device.

According to yet another broad configuration, there is provided a system comprising a plurality of devices of mixed type, wherein the devices are configured in a serial interconnection configuration in which the devices are interconnected in series. Each device has a serial input and an output connection. The system further includes a serial output / input controller having a serial output connection for providing a serial input to a serial input connection of the first device of the serial interconnection arrangement. The serial input is passed through a serial interconnection configuration. The serial output / input controller has a serial input connection that receives the serial output from the last device in the serial interconnection configuration. The serial input includes device type identification, command and device address identification.

For example, a plurality of devices are configured in a single serial interconnect configuration, and the types of devices are mixed. Each device may include a device controller that controls the operation of the device in response to the received serial input. Each of the devices further includes a device address indicator that indicates a device address assigned to the device; And a device type indicator indicating device type identification of the device.

According to yet another broad configuration, there is provided a method of operating a plurality of devices of a mixed type, wherein the devices are configured in at least one serial interconnect configuration in which the devices are interconnected in series, Providing a serial input to a first device of the interconnect configuration, wherein the serial input is communicated through a serial interconnection configuration, and the serial input comprises device type identification, command and device address identification.

The method comprises: holding a device type identification of the device; And holding the assigned device address in response to the provided serial input. The method further includes determining whether the received device type identification matches a held device type identification. Preferably, if the received device type identification matches the held device type identification, a device type match result is provided, and if the received device type identification does not match the held device type identification, then a device type mismatch result is provided do.

The method further includes determining whether the received device address identification matches a held device address. Preferably, if the received device address identification matches the held device address, a device address match result is provided, and if the received device address identification does not match the held device address, then a device address mismatch result is provided. The method may execute a received command of the serial input in response to a device type match result and a device address match result.

According to yet another broad configuration, there is provided a device for operating a plurality of devices of mixed type, wherein the devices are configured in at least one serial interconnect configuration in which the devices are interconnected in series, And a controller for providing a serial input to the first device of the interconnect configuration, wherein the serial input is communicated through a serial interconnection configuration, and the serial input includes device type identification, command and device address identification.

For example, each of the devices has a serial input and output connection, the controller has a serial output connection connected to the serial input connection of the first device and a serial input connection connected to the serial output connection of the last device of the serial interconnection configuration .

According to yet another broad configuration, allocating a device address to a plurality of devices of a mixed type comprises: allocating devices in which the devices are configured in at least one serial interconnect configuration in which devices are interconnected in series; And accessing the devices of the serial interconnection scheme based on the device type and the device address.

The method may further comprise setting an address in each of one type of devices. For example, the setting step includes providing a serial input, including a device type identification, a device address identification, and an address number, to a first device in a serial interconnection configuration. Wherein accessing comprises causing at least one device of a first type of serial interconnection configuration to be processed; And during processing of the first type of device, allowing at least one second type of device of the serial interconnection configuration to be processed, wherein the processing time of the first type of device may include processing of the second type of device It is bigger than time.

According to an embodiment of the present invention, a memory system structure is provided in which a memory controller is controlled by a memory device interconnected by a serial link. The memory controller has an output interface for sending memory commands, and an input interface for receiving a memory response for those memory commands requiring such a response. Each memory device may be any memory type, such as, for example, NAND flash or NOR flash. Each memory command is specific to the memory type of the intended memory device. Data paths for memory commands and memory responses are provided through links and interconnected devices. A given memory command rounds many memory devices to reach its intended memory device. When received, the intended memory device executes the given memory command and, if appropriate, sends a memory response to the memory controller.

In one embodiment, the memory instructions sent by the memory controller are communicated through the serially interconnected memory devices in response to the clock. Instruction execution of one memory device is not superimposed on another memory device (e.g., the next device) at the clock timing. Further, the instruction execution of the memory device may overlap each other. In the address assignment operation, the address number changed by one device is completed before another device executes the address number change.

According to an embodiment of the present invention, there is provided a memory device having a memory type of NAND flash EEPROM, NOR flash EEPROM, AND flash EEPROM, DiNOR flash EEPROM, serial flash EEPROM, DRAM, SRAM, ROM, EPROM, FRAM, A memory device is provided. In a memory system having a serial interconnect configuration of mixed type memory devices, the memory type of each device can be read based on the target address.

Other aspects and features of the present invention will become apparent to those of ordinary skill in the art upon review of the following description of specific embodiments of the invention in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS Embodiments of the present invention will now be described by way of example with reference to the accompanying drawings, in which: Fig.

Figures 1A, 1B, 1C, 1D are block diagrams of four flash memory structures.

2A is a block diagram of a memory system in accordance with an embodiment of the present invention.

2B is a block diagram of a memory system in accordance with an embodiment of the present invention.

2C is a flow diagram illustrating the operation of the memory system shown in FIG. 2B.

Figures 3A, 3B, 3C, 3D, 3E are schematic diagrams of a specific example memory system in accordance with embodiments of the present invention.

3F is a schematic diagram of a memory system of another example according to an embodiment of the present invention.

3G is a timing diagram of an example single data rate operation of a memory device.

3H is a timing diagram of an example double data rate operation of the memory device.

Figure 4A is a schematic diagram of an example memory device used as the memory device shown in Figures 3A, 3B, 3C, 3D, 3E.

Figure 4B is a schematic diagram of an example memory device used as the memory device shown in Figure 3F.

5A is a schematic diagram of an exemplary register block used to identify the memory type of a memory device.

5B is a table of an example encoding scheme for each memory device type.

6A is a flow diagram of a method of assigning a device address with type-dependent addressing.

6B is a flow chart of the details of the device address assignment step of the method shown in FIG. 6A.

Figures 7A, 7B, 7C, 7D are timing diagrams for assigning device addresses with type-dependent addressing.

8 is a timing diagram of an example input with type-dependent addressing.

9 is a timing diagram of an example of signaling through two adjacent memory devices.

10 is a table of an example predefined format for memory operations with type-dependent addressing.

Figure 11 is a table of an example encoding scheme for type-dependent addressing.

12 is a table of an example encoding scheme for a NAND flash instruction with type-dependent addressing.

13 is a table of an example encoding scheme for a NOR flash instruction with type-dependent addressing.

Figure 14 is a flow diagram of a method of handling memory operations with type-dependent addressing.

15A and 15B are timing diagrams of processing memory operations with type-dependent addressing.

Figure 16A is a schematic diagram of another example memory device block used as the memory device shown in Figures 3A, 3B, 3C, 3D, 3E.

16B is a flowchart of a device address assignment operation by the apparatus shown in FIG. 16A.

16C is a flow diagram of another device address assignment operation by the apparatus shown in FIG. 16A.

Figure 17 is a schematic diagram of another example memory device block used as the memory device shown in Figure 3F.

18 shows a two-channel memory system according to another embodiment of the present invention.

19A and 19B are schematic diagrams of a specific example memory device used in the memory system shown in Fig.

20A and 20B are schematic diagrams of another specific example memory device used in the memory system shown in Fig.

21 is a timing diagram of another example of initializing the memory system.

22 is a schematic diagram of another example memory system according to an embodiment of the present invention.

23 is a block diagram of a memory system in accordance with another embodiment of the present invention.

Fig. 24 is a schematic diagram of a specific example memory device used in the memory system shown in Fig. 23. Fig.

25 is a block diagram of a memory system in accordance with another embodiment of the present invention.

26 is a schematic diagram of a specific example memory device used in the memory system shown in Fig.

In the following detailed description of a sample embodiment of the present invention, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration specific example embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and other embodiments may be utilized and logical, mechanical, electrical, and other changes may be made without departing from the scope of the present invention. . The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.

In general, the invention provides an apparatus and method for controlling a semiconductor device, such as, for example, a memory system having a mixed type of memory device.

Embodiments of the present invention are described in the context of a memory system. The memory system includes a serial interconnect configuration of a memory controller and a memory device.

Some memory subsystems use multiple memory devices, such as flash memory devices, for example, with interfaces. Here, the instruction may be executed in only one of these devices, but the instruction string may be supplied to all devices. To select the device on which the command is to be executed, the command string may include a device identifier (ID) or device address that identifies the memory device to which the command is directed. Each device receiving the command string compares the ID contained in the command string with the ID associated with the device. If the two match, the device assumes that the command is directed to the device to execute the command.

As noted above, there are many different memory device types that have different interface specifications. Using conventional architectures, designing memory systems with varying or mixed device types takes a lot of time for engineering design, software development, and verification. In addition, the parallel interface scheme involves physical wiring or routing on a very large number of PCBs (Printed Circuit Boards) or MCPs (Multi Chip Packages) and can cause various noise problems at higher operating speeds. More signal lines mean more complex board designs and more space needs as the density and configuration of the system increases. There is a need for an improved memory system architecture.

Details of serial interconnection of memory devices are disclosed in U. S. Patent Application Serial No. 11 / 324,023, filed December 30, 2005, entitled " Serial Interconnect of Memory Devices, " filed March 28, No. 60 / 787,710, filed on May 23, 2006, entitled " Serial Interconnection of Memory Devices, " in U.S. Patent Application Serial No. 60 / 802,645, the contents of which are incorporated herein by reference in their entirety.

Figure 2A illustrates a memory system in accordance with an embodiment of the present invention. Referring to FIG. 2A, a memory system includes a plurality of devices 300-0, 300-1, ..., 300-N and a controller 100 in a serial interconnection configuration. N is an integer greater than one. In this particular embodiment, the number of serially interconnected memory devices is (N + 1). The controller 100 and the devices 300-0, 300-1, ..., 300-N are interconnected using any suitable connection, for example a link. In the illustrated example, the link is a serial link. The controller 100 and the devices 300-0, 300-1, ..., 300-N are interconnected via serial links L0, L1, L2, ..., LN and L (N + 1).

The controller 100 has a controller operation circuit 130. Each of the devices 300-0, 300-1, ..., and 300-N has a device operation circuit 230 that performs a memory operation control and a memory initialization function. The devices 300-0, 300-1, ..., 300-N have respective memory-type specific components such as respective memories 320-0, 320-1, ..., 320- Each device 300-0, 300-1, ..., 300-N has a memory type among a plurality of supported memory types. Multiple supported memory types are specified on a mounting-specification basis. The information or identification of the memory type of each device is stored in its register 250. However, the type of device is not known to the controller 100. Each of the controller operation circuit and the apparatus operation circuit includes, for example, an input circuit and an output circuit of an interface circuit.

Figure 2B illustrates an example memory system in accordance with one embodiment of the present invention. 2B, memory system 40 includes a plurality of memory devices 30-0, 30-1, ..., 30-N and a memory controller 10 in a serial interconnect configuration. N is an integer greater than one. In this particular embodiment, the number of serially interconnected memory devices is (N + 1). The memory controller 10 and the memory devices 30-0, 30-1, ..., 30-N use serial links L0, L1, L2, ..., LN, L (N + 1) Respectively.

The memory controller 10 includes an output interface 11, an input interface 12, and a controller operation circuit 13. As shown in the illustrated embodiment, in some implementations, the memory controller 10 also has another interface 14 for connecting to other electronic circuits (not shown). The memory controller 10 may have other components, but is not shown for simplicity.

Some components of the memory devices 30-0, 30-1, ..., 30-N are numbered identically. For example, each of the memory devices 30-0, 30-1, ..., 30-N includes an input interface 21, an output interface 22, and a memory device operation circuit 23). However, the memory devices 30-0, 30-1, ..., 30-N can store each memory-type specific component of each memory core 32-0, 32-1, ..., 32- . Each memory device 30-0, 30-1, ..., 30-N has one memory type among a plurality of supported memory types. Multiple supported memory types are specified on a mounting-specification basis. This may be fixed, but in some embodiments it may be modified, for example, by adding memory device types over time. Although a given configuration does not necessarily include each memory device of a plurality of supported memory device types, the memory controller 10 and interface are designed to allow this functionality. There are many possibilities for a plurality of supported memory device types.

The plurality of supported memory types may include, for example, two or more NAND flash EEPROM, NOR flash EEPROM, AND flash EEPROM, DiNOR flash EEPROM, serial flash EEPROM, DRAM, SRAM, ROM, EPROM, FRAM, Magnetoresistive Random Access Memory , PCRAM. Other combinations of supported memory types are also possible.

Each memory device 30-0, 30-1, ..., 30-N knows its memory type. This may be stored in a register, for example, as indicated at 25, but more generally, each memory device 30-0, 30-1, ..., 30-N maintains an identification of its memory device type Any suitable circuitry for doing so may be provided. It is also possible for another mechanism, whereby each memory device 30-0, 30-1, ..., 30-N can know its device type. Each memory device 30-0, 30-1, ..., 30-N may have different components, but is not shown for simplicity.

In operation, the controller operation circuit 13 of the memory controller 10 performs a memory operation control and a memory initialization function. The controller operation circuit 13 sends a memory command via the output interface 11. The data path for each memory command is a combination of the memory devices 30-0, 30-1, ..., 30-N and the serial links L0, L1, L2, ..., LN and L (N + Lt; / RTI > For example, if the memory instruction is for the second memory device 30-1, then the memory instruction will round the first memory device 30-0 via the serial link L0, L1. When the memory command requests a response from the second memory device 30-1, the response is sent to the third memory device via the serial link L2, ..., LN, L (N + 1), ... , The N-th (final) memory device 30-N is returned to the memory controller 10.

As noted above, each memory device 30-0, 30-1, ..., 30-N may be any of a plurality of supported memory types. The control operation circuit 13 of the memory controller 10 sends a memory command specific to the device type through the output interface 11 and sends a memory response to these memory commands requiring this response to the input interface 12 Lt; / RTI > For example, when the controller operating circuit 13 issues an instruction intended for the second memory device 30-1, the issued instruction is specific to the device type of the second memory device 30-1, And may be different from the device type of other memory devices. Each of the memory devices 30-0, 30-1, ..., 30-N executes these memory instructions addressed to the memory device and sends these memory instructions addressed to the other memory device through the output interface 22 . The memory system 40 may be suitably scaled to account for other device types or mixed memory device types as well as memory density extensions without degrading the overall performance of the system.

In general, the memory system 40 performs the two-step operation of an initialization step denoted by 35 and a normal operation step denoted by 36, as shown in FIG. 2C. In the initialization step 35, the device addresses are assigned to the memory devices 30-0, 30-1, ..., 30-N. The assigned device address is held in the memory device. Thereafter, in a normal operation step 36, the target or addressed memory device performs a data access operation.

The controller operation circuit 13 of the memory controller 10 transmits a memory command via the output interface 11 to control the memory devices 30-0, 30-1, ..., 30-N. There are many ways to achieve this. For example, although the first and second embodiments are described below, other embodiments are possible.

In the first embodiment, the controller operation circuit 13 transmits a memory command. Each instruction has first and second portions, which are combined to uniquely identify a memory device selected from among a plurality of memory devices. In some implementations, the first portion identifies the device type of the selected memory device, while the second portion identifies the device address of the selected memory device. Each memory instruction also has an instruction portion that identifies the selected instruction executed by the selected memory device. Each memory command may also include other suitable portions, for example, additional address information and data.

In a first embodiment, when a memory device, for example, a first memory device 30-0, receives a memory command, the memory device operating circuit 23 receives the first and second portions of the combined memory command (For example, the first memory device 30-0). For example, the memory device operation circuit 23 first interprets the first part indicating the device type. If the device type indicated by the first part differs from the device type of the first memory device 30-0 provided by the device type register 25, There is no need to look at any additional portions of < RTI ID = 0.0 > Thus, it is determined whether the received command is addressed to one of the other memory devices 30-1, ..., 30-N. Thus, the memory device operation circuit 23 sends a memory command via the output interface 22. However, if the device type indicated by the first part is the same as the device type of the first memory device 30-0), the memory device operation circuit 23 determines whether the device address indicated by the second part 30-0) of the device. When the two device addresses are matched, the memory device operation circuit 23 executes the selected instruction indicated by the instruction portion. On the other hand, the memory device operation circuit 23 sends a memory command via the output interface 22.

In the second embodiment, the controller operation circuit 13 of the memory controller 10 controls a plurality of memory devices by sending a memory command. Each memory command includes a first portion that uniquely identifies a memory device selected from a plurality of memory devices. The first part identifies the device address of the selected memory device. In a second implementation, the memory instruction need not include a device type. Each memory instruction also has an instruction portion that identifies the selected instruction executed by the selected memory device. As noted above, each memory command may also include other suitable portions. In a second embodiment, when a memory device, for example, a first memory device 30-0, receives a memory command, the memory device operation circuit 23 responds to a first portion of the memory command, (I.e., the first memory device 30-0). The memory device operation circuit 23 determines whether the device address indicated by the first part matches the device address of the first memory device 30-0). When the two device addresses are matched, the memory device operation circuit 23 executes the selected instruction indicated by the instruction portion. On the other hand, the memory device operation circuit 23 sends a memory command via the output interface 22.

In some implementations, the controller operation circuit 13 of the memory controller 10 is operable to send a memory command via the output interface 11 in response to a request received via the interface 14, 12 to respond to the request using the memory response received. The interface 14 may be any suitable interface to another device or system (not shown) using the memory system 40.

There are many possibilities for memory commands. These may include one or more of a read operation, a write operation, an erase operation, a read state operation, a read ID operation, a write configuration register operation, a write address operation, and a reset operation. There may be another memory command.

The manner in which the memory controller 10 transmits memory commands may depend on the manner in which the device address is assigned. An example of assigning a device address is provided below.

There are many ways to have device addresses assigned to memory devices 30-0, 30-1, ..., 30-N. In some implementations, the device address is predefined or wired. In another embodiment, the controller operation circuit 13 allocates a device address in an initialization step. For example, although the first and second embodiments are described below, other embodiments are possible.

In a first embodiment, the controller operating circuit 13 is operable to provide, for each device type of a plurality of supported device types, a respective one of a plurality of device types, each of which assigns a device address to each memory device of the device type via the output interface 11 And transmits an initialization message. Each of the memory devices 30-0, 30-1, ..., 30-N receives and processes the initialization message. For example, the first memory device 30-0 receives the initialization message via the first input interface 21. For each initialization message received, if the initialization message is marked for another device type rather than the device type of the first memory device 30-0, then the memory device operation circuit 23 sends an initialization message to the output interface (22). However, if the initialization message is marked for the device type of the first memory device 30-0, the memory device operation circuit 23 determines the device address from the initialization message. This involves reading the device address from the initialization message. In some implementations, the device address as read from the initialization message is the device address of the first memory device 30-0. The memory device operation circuit 23 sends an initialization message with a new device address via the output interface 22. Each of the other memory devices 30-1, ..., 30-N performs a similar initialization process. For each initialization message sent, the controller operating circuit 13 receives the respective initialization response via the input interface 12 and, if there is a memory device of the device type, The address can be determined.

For example, in some implementations, for each memory device to which a device address is assigned, the new device address sent to the next device is an increment of the device address. Therefore, if a first memory device of a given device type is assigned an address of zero, the last memory device of a given device type is assigned an address of m-1, where m is the number of memory devices of a given device type. The controller operating circuit 13 determines the device address of each memory device of a given device type by receiving an initialization response via the input interface 12, indicating the incremented device address of the last memory device of the given device type. Note that in the case of multiple device types, the memory controller 10 does not know which type of physical device it is. Rather, the memory controller 10 knows how many memory devices of each type are present. For example, there may be four NAND devices and four NOR devices. Four NAND devices have type = NAND, address = 0,1,2,3 respectively, and four NOR devices have type = NOR, address = 0,1,2,3 respectively. Then, regardless of the physical address of the NAND and NOR memory devices, the instruction containing the type and address portion always looks for the target device. By executing two different sets of device numbering (i.e., device type and device address), memory controller 10 does not need to consider which device address is assigned to which type of device in memory system 40.

In the second embodiment, the controller operation circuit 13 of the memory controller 10 outputs an initialization message for allocating the device address to the memory devices 30-0, 30-1, ..., and 30-N Via the interface 11. The memory devices 30-0, 30-1, ..., and 30-N receive and process initialization messages. For example, the first memory device 30-0 receives the initialization message via the input interface 21, and the memory device operation circuit 23 of the device reads the device address from the received initialization message. In some implementations, as read from the initialization message, the device address becomes the device address of the first memory device 30-0. The memory device operation circuit 23 sends an initialization message via the output interface 22 with a new device address. Each of the other memory devices 30-1, ..., and 30-N executes a similar initialization process. As a result, the controller operation circuit 13 of the memory controller 10 receives the initialization response via the input interface 12, from which the device address of each memory device will be determined.

For example, for each of the memory devices 30-0, 30-1, ..., and 30-N, the new device address sent to the next device is an increment of the device address. Therefore, if the first memory device 30-0 is assigned an address of zero, the last memory device 30-N will be assigned an address of N, where the number of memory devices is (N + 1). By receiving an initialization response indicating the incremented device address of the last memory device 30-N via the input interface 12, the controller operation circuit 13 can determine the device address of each memory device.

According to the second embodiment described above, once the device addresses of the respective memory devices 30-0, 30-1, ..., and 30-N are assigned, the controller operation circuit 13 reads out Determine the device type. For each device address, the controller operating circuit 13 sends an additional initialization message via the output interface 11 to determine the device type of the memory device at the device address. Each of the memory devices 30-0, 30-1, ..., and 30-N receives and processes this additional initialization message.

For example, if the first memory device 30-0 receives an additional initialization message via the input interface 21, the first memory device 30-0 may determine It is determined whether or not the additional initialization message is for the first message device 30-0. If so, the first memory device 30-0 responds to this additional initialization message via the output interface 22 with identification information of the device type of this device. If this additional initialization message is for one of the other memory devices 30-1, ..., and 30-N, the first memory device 30-0 sends this additional initialization message through the output interface 22 Each of the other memory devices 30-1, ..., and 30-N performs similar processing of the additional initialization message. The controller operation circuit 13 of the memory controller 10, via the input interface 12 And receives an initialization response indicating the device type of the memory device for each memory device.

It should be understood that the above-described first and second implementations of the controller operation circuit 13 are only very specific for illustration. Changes and modifications are possible. For example, although the first implementation is described above as involving multiple initialization messages to assign a device address to each memory device, alternatively there may be more than one initialization message for this purpose. Also, while the second embodiment is described above as involving a number of additional initialization messages to determine the device type of each memory device, alternatively there may be one or more additional initialization messages for this purpose. In the example described, the address of the received initialization message is set to the device address, and a new address is generated and sent to the next device. In another implementation, each memory device receives an address and increments it before setting it to the device address. A detailed example of this embodiment is disclosed in commonly assigned co-pending U.S. Patent Application Serial No. 11 / 529,293, filed September 29, 2006, which is incorporated herein by reference in its entirety, &Quot; Generating Packet-based IDs for Devices ".

The example provided above refers to the interface. It should be understood that there are many possibilities for such interfaces. A specific interface is provided in the example to be described later. More generally, any suitable interface may be implemented.

In some implementations, the memory controller 10 has a reset output (not shown) for connecting with each of the memory devices 30-0, 30-1, ..., and 30-N. An example of this is provided in the following example. More generally, the memory system 40 may be reset using any suitable reset implementation.

In some implementations, memory controller 10 has a serial clock output (not shown) for connecting to each of memory devices 30-0, 30-1, ..., and 30-N. An example of this is provided in the following example. More generally, the memory system 40 may be provided with a serial clock using any suitable clock implementation.

In some implementations, the memory controller 10 has chip selection (not shown) for connecting with each of the memory devices 30-0, 30-1, ..., and 30-N. An example of this is provided in the following example. More generally, the memory devices 30-0, 30-1, ..., and 30-N may be enabled using any suitable device enabling implementation.

Figure 2C shows the operation of the memory system shown in Figure 2B. 2B and 2C, the controller operation circuit 13 of the controller 10 transmits the memory command through the output interface 11 to the apparatuses 30-0, 30-1, ..., and 30- N. The controller operation circuit 13 controls the devices 30-0, 30-1, ..., and 30-N by transmitting memory commands. There are many ways in which this operation can be achieved. For purposes of illustration, some exemplary implementations will be described below, but other implementations are possible.

In general, the memory system 40 performs the initialization steps indicated by two steps 35 and the normal operation steps indicated by 36. In the initialization step 35 (or initialization mode), the device addresses are assigned to the devices 30-0, 30-1, ..., and 30-N. The assigned device addresses are held in the devices 30-0, 30-1, ..., and 30-N. Thereafter, in a normal operating phase 36 (or normal operating mode), the target or addressed memory device performs a data access operation.

In one example of the initialization step 35, the controller operation circuit 13 sends a memory command. This command has a device address assignment portion and a device address related number portion for assigning a unique address to the device. In one implementation, the device address related number of the instruction from the controller operating circuit 13 is an initial value or number, and the initial number is incremented by each device. Each of the incremented numbers is held as the address of each device in each device.

In one example of the normal operation step 36, the controller operation circuit 13 of the controller 10 transmits a memory command. The memory command includes a first portion that uniquely identifies a selected one of the plurality of memory devices by a device address. The device type is not included in the memory command. Each memory command also has a command portion that identifies the selected command to be performed by the selected memory device. Each memory instruction may also include other suitable portions. After the memory device, for example the first device 30-0, receives the memory command, the device operating circuit 23 of the device responds to the first part of the memory command, 1 device 30-0). The device operation circuit 23 determines whether the device address indicated by the first part matches the device address of the first device 30-0. If there is a match between the two device addresses, the device operation circuit 23 of the device 30-0 will perform the selected command indicated by this command part. Otherwise, the device operation circuit 23 sends a memory command to the next device (e.g., the second device 30-1) via the output interface 22.

In some embodiments, the controller operation circuit 13 of the controller 10 is operable to transmit a memory command via the output interface 11, in response to a request received via the interface 14, And to respond to the request using the memory response received via the interface 12. [ The interface 14 may be any suitable interface to another device or system (not shown) that uses the memory system 40.

There are many possibilities for memory commands. These possibilities may include at least one of a read operation, a write operation, an erase operation, a read state operation, a read DA operation, a write configuration register operation, a write address operation and a reset operation. There may be other memory commands.

The manner in which the controller 10 transmits memory commands may vary depending on the manner in which the device addresses are assigned. An exemplary implementation for assigning a device address will be provided below.

In the following detailed description and drawings, some reference numerals are used for signals and connections. For example, "SCLK" represents a clock signal and a clock input connection of a memory device, "SIP" represents a serial input port signal and a serial input port connection, "SOP" represents a serial output port signal and a serial output port connection, "IPE" indicates an input port enable signal and an input port enable connection, "OPE" indicates an output port enable signal and an output port enable connection, "CS #" indicates a chip selection signal and a chip selection input connection Port, and "RST #" indicates a reset signal and a reset input connection or port. Also, the same reference numerals are used for the same or corresponding blocks, connections, signals, and circuits.

Figures 3A, 3B, 3C, 3D, 3E and 3F illustrate a memory system of a specific example according to an embodiment of the present invention. It should be understood that these drawings are highly specific and are provided for illustrative purposes only.

3A shows a general configuration of an exemplary memory system. The memory system 41 includes a memory controller 50 and a plurality (n + 1) of memory devices, where n is an integer. In this particular example, the memory controller 50 and the memory device are connected to a serial link. This serial interconnection arrangement comprises a first device 80 ("Device-0"), a second device 81 ("Device-1"), a third device 82 ("Device- , And an (n + 1) th device 83 ("device-n").

3A, the memory controller 50 includes a reset port 51, a chip select port 52, and a serial clock port (not shown) connected to each of the memory devices 80, 81, 82, ..., (53). Thus, each of the memory devices 80, 81, 82, ..., and 83 has a reset port 61, a chip select port 62, and a serial clock port 63. The memory controller 50 has an output interface that includes a serial output 54, an input enable 55, and an output enable 56 connected to the first memory device 80. Thus, the first memory device 80 has an input interface that includes a serial input 64, an input enable 65, and an output enable 66. The first memory device 80 also has an output interface that includes a serial output 67, an input enable echo 68, and an output enable echo 69. Each of the other memory devices 81,82 and 83 has a corresponding input interface 64,65 and 66 and an output interface 67,68,69 so that the memory devices 80,81, , And 83 are interconnected via a serial link. The memory controller 50 includes a serial input 57, an input enable echo 58 and an output enable echo 59 for connection to the output interfaces 67, 68 and 69 of the final memory device 83 Lt; / RTI >

The memory controller 50 has elements (not shown) similar to the elements of the memory controller shown in Figure 2B, but these elements are not shown for simplicity.

The memory devices 80, 81, 82, ..., and 83 each have memory-type specific elements such as memories 80A, 81A, 82A, ..., and 83A. In the illustrated example, however, their device type is not specific. Each of the memory devices 80, 81, 82, ..., and 83 has an interface circuit (not shown) between its interface and its memory. Each of the memory devices 80, 81, 82, ..., and 83 also has a register 60 for maintaining the identification of the device type. In another implementation, each of the memory devices 80, 81, 82, ..., and 83 has an alternative circuit for maintaining the identification of the device type. Each of the memory devices 80, 81, 82, ..., and 83 may have other elements, but these elements are not shown for simplicity.

In operation, the memory system 41 operates in a manner similar to the memory system 40 described above with reference to FIG. 2B. However, for purposes of illustration, other illustrative details of the operation of the memory system 41 are provided below with reference to additional figures.

FIG. 3B shows a memory system 42 of a first specific example. The memory system 42 is similar to the memory system 41 shown in Fig. 3B. The memory system 42 includes (n + 1) memory devices 84, 85, 86, ..., and 87 having the same memory cores 84A, 85A, 86A, 87A as the example of Figure 3B do. 3B, the first memory device 84 has a NOR flash memory core 84A, and each of the second, third, ..., and (n + 1) th memory devices 85, 86, ..., and 87 have NAND flash memory cores 85A, 86A, ..., and 87A. The example of Figure 3C differs from the example of Figure 3B in that a type-based addressing scheme, i. E. The first addressing scheme introduced earlier, is used. NAND-1, NAND-1, NAND-1, NAND-1, NAND-1, NAND- 1) '.

As previously noted, the memory devices 84, 85, 86, ..., and 87 may be any suitable device type. To illustrate this point, another exemplary memory system with a modified or mixed device type is provided with reference to Figures 3D, 3E and 3E.

3C shows a memory system 43 of a second specific example. The memory system 43 is identical to the memory system 42 shown in Fig. 3C, except that the memory system 43 has another memory device. 3C, the memory system 43 includes a plurality (n + 1) of memory devices 88, 89, ..., 91A each having mixed memory cores 88A, 89A, 90, ..., and 91). The first memory device 88 has an SRAM memory core 88A and the second memory device 89 has a NOR flash memory core 89A. The third, ..., and (n + 1) th memory devices 91 have NAND flash memory cores 90A, ..., and 91A, respectively. The memory device is addressed using a type-of-addressing scheme. Assuming that there is one SRAM device, one NOR device, and (n-1) 'NAND devices, the type plus address is' SRAM-0', 'NOR-0', 'NAND-0',. ... " and " NAND- (n-2) ".

Figure 3D shows a memory system 44 of a third specific example including a plurality (n + 1) of memory devices. 3D, the memory system 44 is similar to the memory system 44 shown in FIG. 3C except that the memory system 44 has a different memory device 92, 93, ..., 94 and 95 42). In the particular example shown in FIG. 3E, the memory cores 92A, 93A, 94A, ..., and 95A of the memory devices 92, 93, ..., 94 and 95 are mixed. In the illustrated example, the first, second, third, ..., and nth memory devices 92, 93, ..., and 94 are NAND flash memory cores 92A, 93A, 94A. The final ((n + 1)) memory device 95 has a NOR flash memory core 95A. The memory device is addressed using a type-of-addressing scheme. The type plus address is' NAND-0 ',' NAND-1 ', ...,' NAND- (n-1) ', and' NAND- NOR-0 '. It should be noted that the memory controller 50 will not be aware of the differences in the physical layout between FIG. 3B and the example of FIG. 3D.

3E shows a memory system 45 of a fourth specific example. The memory system 45 is identical to the memory system 42 shown in Figure 3C, except that the memory system 45 has different memory devices 96, 97, 98, ..., and 99 . In the particular example shown in Figure 3E, the memory cores 96A, 97A, 98A, ..., and 99A of the memory devices 96, 97, 98, ..., and 99 are mixed. In the illustrated example, the first memory device 96 has a NAND flash memory core 96A. The second memory device 97 has a NOR flash memory core 97A. Third, ..., and final (n + 1) memory devices 98, ..., and 99 have NAND flash memory cores 98A, ..., and 99A, respectively. The memory device is addressed using a type-of-addressing scheme. NAND-1, NAND-1, NAND-1, NAND-1, NAND-1 and NAND- 1) '. It should be noted that the memory controller 50 will not be aware of the differences in physical layout between the examples of Figures 3B-3E.

Assuming that memory controller 50 is capable of interacting with at least NOR flash devices, NAND flash devices, and SRAM devices, the four examples of FIGS. 3B-3E illustrate the same circuit layout, the same memory controller 50, But may be implemented as 'lots' or 'sockets'. Any arrangement with a supported device type may then be installed as a 'lot' or 'socket', and FIGS. 3B, 3C, 3D and 3E are each an example of this.

In each of the examples illustrated in Figures 3A through 3E, a reset, a chip select, and a serial clock signal are provided in a multi-drop manner. In another implementation, as shown in Figure 3F, the serial clock is connected in a point-to-point ring type scheme by the addition of an output echo clock signal, 'SCLK_0'. SCLK is a system clock that synchronizes the memory controller 50A and the memory devices 180, 181, 182, ..., and 183. The echo clock signal output from each memory device is then supplied to the clock input (SCLK) of the memory device. The memory controller 50A and the memory devices 180, 181, 182, ..., and 183 operate as a master device and a slave device, respectively. Assuming that there are (n + 1) memory devices, the assigned address appears as 'device-0', 'device-1', ..., and 'device-n'.

In the example shown, it should be appreciated that the clocking is based on a single data rate (SDR), but other suitable clocking schemes may be contemplated. Other suitable clocking schemes may include, for example, Double Data Rate (DDR), Quad Data Rate (QDR), rising edge SDR, or falling edge SDR. There may be other suitable clocking schemes that you might think of.

Figure 3G shows a timing sequence relative to an exemplary SDR operation of a memory device. 3G shows operation at one port. 3A and 3G, the illustrated operation is such that the information transmitted to the devices 80, 81, 82, ..., and 83 is the clock signal SCLK supplied to the device's serial clock port 63, And can be captured at different times. In one example of an SDR implementation, the information provided at one of the devices at the serial input 64 of the device may be captured at the rising edge of the clock signal SCLR. In SDR operation, the chip select signal is generally connected to enable all devices at the same time, so that the input data of the first device can be transmitted through the serial interconnection scheme. Alternatively, in SDR operation, the information provided to the device at the SIP connection may be captured at the falling edge of the clock signal SCLK.

3H shows a timing sequence relative to an example DDR operation of the memory device. 3H illustrates operation at one port. In the DDR operation, both the rising and falling edges of the clock signal SCLK can be used to capture the information supplied to the serial input 64. [

Fig. 4A shows an example memory device block used as the memory device shown in Figs. 3A to 3E. 4A, memory device 140A represents any one of the memory devices and includes device controller / processor 142A, device type match determiner 143, memory 144, device type register 146, A determiner 147, a device address register 148, and an address incrementing operator 149. [ The device controller / processor 142A controls the operation of the memory device 140A. Memory 144 includes any type of memory, such as, for example, NAND flash memory, NOR flash memory, SDRAM, and DRAM. The device type register 146 includes a register 60 for maintaining the identification of the device type as shown in Figures 3A to 3E. The device address register 148 holds the device address DA assigned by the device controller / processor 142A of this memory device 140A. The details of the device type register 146 are shown in Fig. 5A. The device type match determiner 143 and the address match determiner 147 execute the relevant match determination functions under the control of the device controller / processor 142A. The address increment operator 149 executes the device address increment function (i.e., "DA + 1").

Device 140A includes a serial clock port ("SCLK ") connected to a reset port (" RST # "), a chip select port (" CS # ") and a memory controller Quot;). The device controller / processor 142A is connected to a serial input ("SIP "), an input enable (" IPE ") and an output enable ("OPE ") of a memory device connected to a previous memory device or memory controller. The device controller / processor 142A is also connected to a serial output ("SOP"), an input enable echo ("IPEQ") and an output enable echo ("OPEQ") of a memory device connected to the following memory device . The memory 144 corresponds to a flash memory core. The device type register 146 corresponds to the type register 60 for maintaining the identification of the device type.

An example of the format of a memory command issued by a memory controller is as follows:

Memory instruction (1)

TYPE
(aah) TDA
(bbh) CMD
(cCH) DATA
(ddh)

TYPE is the device type for identification of a particular memory device type. The TDA is the target device address for identification of the address of a particular memory device. CMD is an operation command to be performed by the target memory device. DATA contains information (number or value) about the process or control of the memory device. Examples of various operation commands CMD are shown in Table 1.

[Table 1]

action Command (1 byte) Page reading 00h Read random data 05h Page program 10h Chip erase 20h Sector erasing 21h Reading pages for copy 35h Recording device address 39h Block erase 60h Read status 70h Serial data input (write to buffer) 80h Random data entry 85h Target address input for copy 8Fh Reader Device Type 90h Write Configuration Register A0h Pause program / erase C0h Resume program / erase D0h reset FFh

4A, the device controller / processor 142A determines whether a memory command is addressed to this memory device 140A, in response to the device address and device type contained in the serial input (SI). For example, device type match determiner 143 may determine, under control by device controller / processor 142A, device type ('DTr') where device type ('DTs') of SI is held in device type register 146 and device type Match. If they are matched, the device type match determiner 143 provides the type match indication 143M to the device controller / processor 142A. The address match determiner 147 then determines that the device address ('DAs') contained in the SI is the device address ('DAr') held in the device address register 148 under the control of the device controller / processor 142A . ≪ / RTI > If they are matched, the address match determiner 147 provides the address match indication 147M to the device controller / processor 142A.

In operation of the initialization step 35 as shown in Figure 2C, in response to the type match indication 143M and the address match indication 147M, the device controller / processor 142A receives the device address DA contained in the SI, To the address incremental operator 149 to perform a calculation of "+1 ". Accordingly, the calculated, i.e., the incremented address DA + 1 is output to the device controller / processor 142A. The incremented device address is supplied to the next device via the SOP. If neither the type match indication 143M nor the address match indication 147M is provided, the device controller / processor 142A sends the command to the next device via the SOP.

In the normal operation of the data access step 36 as shown in Figure 2C, in response to the type match indication 143M and the address match indication 147M, the device controller / processor 142A receives the received command . If neither the type match indication 143M nor the address match indication 147M is provided, the device controller / processor 142A sends the command to the next device via the SOP.

Fig. 4B shows an example memory device used as the memory device shown in Fig. 3F. The memory device 140B shown in Fig. 4B represents any one of the memory devices shown in Fig. 3F. Memory device 140B is similar to memory device 140A shown in FIG. 4A. The device controller / processor 142B of the memory device 140B includes a clock synchronizer 191 for outputting an output clock synchronized with the input clock supplied thereto. The clock synchronizer 191 includes a phase-locked loop (PLL) or a delay-locked loop (DLL) that provides the output echo clock signal SCLK_0 of the clock signal SCLK input from the previous memory device -locked loop). The other operation of the device 140B is the same as that of the device 140A shown in Fig. 4A.

In the example raised above with reference to Figures 3A-3F, each of the memory devices has a register (e.g., device type register 146). Flash memory (e.g., NAND flash, NOR flash memory) may store useful information, such as manufacturer code, memory density, page size, block size, number of banks, I / O configuration, , A factory programmed register inside the device, which uses an extra section of the flash cell core array to identify the flash memory cell array. However, as previously noted, in some implementations, a register is used to maintain the identification of the device type. There are many ways in which registers display device types. An example is provided below with reference to FIG. 5A.

Referring to FIG. 5A, an exemplary register block 120 has a type-register that is a kind of physical hard programmable register unit. The register block 120 has an eFuse (electrically programmable fuse) array 121 and an eFuse level detection logic unit 122. In the illustrated example, the eFuse array 121 is shown having an 8-bit configuration of bits 7, 6, 5, ..., 1, and 0. In this particular example, the first 4 bits 7-4 are '0000' and the second 4 bits 3-0 are '0111'. This indicates, for example, '07h' (= 00000111). In certain implementations, this configuration indicates the PCRAM memory type. Different configurations may indicate different device types. In the illustrated example, the 'closed' and 'open' fuses indicate '0' and '1', respectively. Such '0' and '1' logic is detected by the eFuse level detection logic unit 122 and the detected bit state (bits 7-0) is provided to the device controller / processor 142A shown in FIG. 4A. Alternatively, the register block 120 may have a conventional poly or metal fuse, an OTP (One Time Programmable memory), or any non-volatile programmable device.

Figure 5B shows a table of an example encoding scheme for each device type. In this table, 'RFU' means 'Reserved for Future Usage'. Referring to Figure 5B, the table defines the encoding scheme for each of the ten memory types: NAND Flash, NOR Flash, DRAM, SRAM, PSRAM, DiNOR Flash, FeRAM, PCRAM, Serial EEPROM, and MRAM. For example, the SRAM memory type has an encoding scheme of '03h'. The NAND flash type is assigned as '00h' whereas the NOR flash type is assigned as '01h'. In this example, the bit structure is MSB (most significant bit) to LSB (least significant bit). In other implementations, this may be reversed in order so that it starts first with the LSB instead of with the MSB. Some register configurations are reserved for future use (RFU).

There are many ways to implement the initialization step 35 shown in FIG. 2C. As noted earlier, each memory device has a memory type. A method of allocating a device address by type-dependent addressing will be described below with reference to FIG. 6A.

6A shows a method of assigning a device address by type-dependent addressing. It should be appreciated that this process is very specific only for illustrative purposes. This method can be applied to any memory system in which a plurality of memory devices are connected in series (e.g., the memory system shown in FIG. 3B).

3B and 6A, when there is a power-up initialization (step 6-1), the memory controller 50 executes a write device address operation for the memory device of the device type 'm' (step 6-2 ). The write device address operation has a target device address (TDA) of '00h' because all memory devices have a device address initially set to '00h' during power up. When the recording device address operation circulates through each memory device, its target device address remains at '00h', and each memory device processes the recording device address operation. The recording device address operation circles each memory device. Each memory device of the device type 'm' is assigned the device address of the device based on the device address indicated by the recording device address operation. Each memory device to which the device address of the device is assigned increments the device address indicated by the recording device address operation before sending it to the next memory device.

Eventually, the recording device address operation returns to the memory controller 50. The recording device address operation is returned to the memory controller 50 as indicated by the signal input enable echo (IPEQ) and serial input (SIP in step 6-3) (YES in step 6-3) The memory controller 50 will determine that the number of the memory device of the device type "m" is equal to the device address ("NA" m '(step 6-5). Thereafter, the memory controller 50 determines whether there is another device type based on the value of 'm' (step 6-6). If there are other device types (YES in step 6-6), the operation will return to step 6-2. For each different device type, the memory controller 50 repeats steps 6-2 through 6-5. The memory controller 50 attempts to allocate the device address to all possible device types of memory devices corresponding to all possible values for 'm'. This is done because the memory controller 50 may not know in advance what type of device is in the memory system. When there are no more other device types (NO in step 6-6), the process ends (step 6-7).

The details of step 6-2 described above are shown in Fig. 6B. Referring to Figures 3B, 4A, 6A and 6B, the device receiving the recording device address operation determines whether the received device type 'm' matches the device type registered in the device type register 146 Step 6-8). This is performed by the device controller / processor 142A and the device type match determiner 143. [ If there is a device type match (YES in step 6-8), the device will also determine if the target device address TDA matches the device address registered in the device address register 148 (step 6-9). This is performed by the device controller / processor 142A and the address match determiner 147. [ If there is a device address match (YES in step 6-9), the received device address will be registered in the device address register 148 (step 6-10) and the received device address will be incremented (DA + 1) Steps 6-11). Such device address incrementing is performed by device controller / processor 142A and address increment operator 149. [ If there is no device type match (NO in step 6-8), both the device address assignment and the device address increment will not be executed. Also, if there is no device address match (NO in step 6-9), neither device address assignment nor address incrementation will be performed.

To further illustrate the process described above with reference to Figures 6A and 6B, a timing diagram will be described below with reference to Figures 7A, 7B, 7C and 7D.

Figures 7A, 7B, 7C, and 7D illustrate timing sequences for signals for assigning device addresses by type-dependent addressing. This timing diagram shows examples of signals that may result from a memory system in which one NOR-type flash device and the " n " NAND-type flash device are interconnected. This kind of memory system is similar to the memory system 42 of FIG. 3D.

As described above, the memory command issued by the memory controller is formatted. For example, in a memory system, only a NAND flash device is assigned a device address from "0 ", and the memory command issued by the memory controller is as follows:

Memory instruction (2)

TYPE
(00h) TDA
(00h) CMD
(39h) DATA
(00h)

In this memory command:

TYPE (00h) identifies the "NAND flash" device (see FIG. 5B).

The TDA (00h) identifies the device holding the device address "0 " when the initialization operation is performed. It is assumed that all memory devices in the serial interconnect configuration have been reset to "0 ".

CMD 39h identifies that the operation to be performed is a "recording device address " (see Table 1).

DATA (00h) identifies that the initial number of the device address is "0 ".

Referring to Figures 7A-7D, at the top of the timing diagram there is a signal for power (VDD), denoted 7-1. The timing diagram includes signals for input enable (IPE) and serial input (SIP) for device_0 as shown at 7-2 and 7-3, respectively. The timing diagram also includes signals for input enable (IPE_1) and serial input (SIP_1) for device_1 as shown at 7-4 and 7-5, respectively. The timing diagram includes signals for the input enable (IPE_2) and the serial input (SIP_2) for device_2 as shown by 7-6 and 7-7, respectively. The timing diagram includes signals for input enable (IPE_n-1) and serial input (SIP_n-1) for device_ (n-1) as shown at 7-8 and 7-9, respectively. The timing diagram includes signals for the input enable (IPE_n) and the serial input (SIP_n) for the device _n as shown at 7-10 and 7-11, respectively. Finally, the timing diagram shows the input enable echo (IPEQ) and serial output (SOP) for the device n, which is the last memory device in the serial interconnect configuration of the memory system, as indicated by 7-12 and 7-13 respectively Lt; / RTI >

For example, if this kind of memory system is applied to the memory system 42 of FIG. 3D, the devices _0, _1, ..., _ (n-1) , 94 and 95).

Referring to Figures 3D and Figures 7A-7D, the memory system is powered on and transitions to a high state, as indicated by VDD 7-1. Immediately thereafter, the first recording device address operation (7-14) is issued by the memory controller 50. The first recording device address operation 7-14 indicates the device type of the NAND flash. The first recording device address operation (7-14) circles each memory device. In each NAND flash memory device, the device address of the device is assigned based on the device address displayed by the recording device address operation. Each memory device to which the device address of the device is assigned increments the device address indicated by the first recording device address operation before sending it to the next memory device. There is a total of 'n' increments corresponding to 'n' NAND flash memory devices. There is no increment by the final memory device, since this memory device is not a NAND flash device, but rather a NOR flash device. The first recording device address operation (7-14) returns to the memory controller. The memory controller determines that the number of NAND flash devices is equal to 'n' as indicated by the first recording device address operation.

The memory controller 50 issues different write device address actions for each different device type. A second recording device address operation (7-15) indicating the device type of the NOR flash is issued. The memory instructions for device address allocation of the NOR flash device are as follows:

Memory instruction (3)

TYPE
(01h) TDA
(00h) CMD
(39h) DATA
(00h)

A second recording device address operation (7-15) centers each memory device. None of the NAND flash devices increment the device address indicated by the second recording device address operation. The final memory device, which is a NOR device, is assigned its device address (TDA) '00h'. The final memory device also increments the device address indicated by the second recording device address operation before sending it to the memory controller. Upon receipt of the second recording device address operation (7-15), the memory controller determines whether there is one NOR device based on the device address indicated by the second recording device address operation.

Additional recording device operations may be issued by the memory controller, but are not shown for simplicity. For example, if SRAMs are allocated to device devices, the type of memory command issued by the memory controller would be " 03h " (see FIG. 5B).

Devices in the serial interconnect configuration perform operations in response to commands issued by the memory controller.

Referring to Figures 3D, 4A and 7A-7D, the memory controller 50 issues a second recording device address operation for the device type of the NAND flash. TYPE (NAND flash), TDA (0Oh), CMD 39h and DATA (0Oh) included in the SIP are supplied to the first device 92 (i.e., device_0) during IPE high-in. CMD 39h causes device controller / processor 142A of device 92 to perform a " write device address " operation. Both the TYPE and the device type DTr of the SIPs (DTs) held in the device type register 146 are NAND flashes and thus the device type match determiner 143 determines the device type match result (i.e., the type match indication 143M ). Also, the TDA is '00h' (DAs) matching the device address DAr held in the device address register 148, and the address match determiner 147 sets the device address match result (that is, the address match mark 147M) Lt; / RTI > In response to the device type match result, the address increment operator 149 performs an addition of DATA and 1 to obtain an address increment (" DA + 1 "). In response to the device address match result, the device controller / processor 142A causes the device address register 148 to replace the previously held address with the received address (the number or value of DATA in the SIP) 92 is set to " NAND-0 ". The number of DATAs in SIP is replaced by the number of incremented addresses. All commands (in SIP) except DATA are bypassed. Thus, a modified SIP (SIP_1) containing the incremented DATA (01h), CMD 39h, TDA (00h) and TYPE (NAND Flash) is sent to the next device 93 .

These operations are performed during a period between transition of IPE to high and transition of IPE_1 to high. The device 93 executes the same operations and is set to " NAND-1 ". All commands (of SIP_1) except DATA are bypassed. These operations are executed during a period TP1-1 between transition of IPE_1 to high and transition of IPE_2 to high. The received DATA is incremented by one and the incremented DATA (02h) is included in the SIP_2 of the next device 94 (i.e., device_2) These operations are executed during the period TP1-2. Similarly, the device 94 executes the same operations and is set to " NAND- (n-1) ". All commands except for DATA (of SIP_ (n-1)) are bypassed. These operations are performed during a period TP1- (n-1) between transition of IPE_ (n-1) to high and transition of IPE_n to high. However, the device 95 does not perform the same operations. In response to an input command of DATA (nh), CMD 39h, TDA 00h and TYPE (NAND Flash) included in SIP_n, the device 95 is called a device type mismatch (i.e., mismatch) Determine and ignore the command. Therefore, DATA (nh) remains unchanged with no DATA increment for the next device. The command output from the device 95 (final device) is sent to the memory controller 50 as a feedback during the period TP1-SO. Memory controller 50 recognizes the total number of NAND-type devices that are " n " in number or value of DATA.

The memory controller 50 then issues a second recording device address operation for the device type of the NOR flash. During the IPE high again, DATA (00h), CMD (39h), TDA (00h) and TYPE (NOR flash) included in the SIP are supplied to the first device 92 (i.e., device_0). The CMD 39h causes the device controller / processor 142A of the device 92 to execute a device type match determination. The TYPE of SIP (DTs) is NOR flash, and the device type (DTr) held in device type register 146 is NAND Flash. Accordingly, the device type match determiner 143 provides a device type mismatch (or mismatch), and the device 92 ignores the received (or input) write device address command. DATA remains unchanged as incremental. The device 92 (device controller / processor 142A) sends TYPE (NOR flash), TDA (00h), CMD 39h and DATA (0Oh) to the next device 93. An unmodified SIP (SIP_l) containing the incremental DATA (00h), CMD 39h, TDA 00h and TYPE (NOR Flash) is sent to the next device 93 (i.e., device_1) . These operations are performed during a period TP2-SI between transition of IPE to high and transition of IPE_1 to high.

In response to the received SIP_1, the device 93 performs the same operations. Due to the mismatch of the device type, the device 93 (device controller / processor 142A) ignores the received command (write device address) and the DATA byte remains unchanged to no increment. The device 93 sends DATA (00h), CMD 39h, TDA 00h and TYPE (NOR flash) included in the SIP_2 to the next device 94 (i.e., device_2). These operations are executed during a period TP2-1 between transition of IPE to high and transition of IPE_2 to high. Similarly, in response to SIP_2, which includes DATA (00h), CMD (39h), TDA (00h), and TYPE (NOR Flash), device 94 performs the same functions. Due to the mismatch of the device type, the device 94 ignores the recording device address and the DATA byte remains unchanged to no increment. These operations are executed during the period TP2- (n-1).

In response to SIP_n, which includes DATA (00h), CMD 39h, TDA 00h, and TYPE (NOR Flash), device 95 executes device type match verdicts. Both the device type DTr held in the device type register 146 and the TYPE of the SIPs DTs are NOR flash so that the device type match determiner 143 determines the device type match result (i.e., the type match indication 143M ). Also, the TDA is '00h' (DAs) matching the device address DAr held in the device address register 148, so that the address match determiner 147 generates a device address match result (i.e., an address match indication 147M ).

In response to the device type match result, the address increment operator 149 performs an addition of DATA and 1 to obtain an address increment (" DA + 1 "). In response to the device address match result, the device controller / processor 142A of the device 95 causes the device address register 148 to replace the previously held address with the received address (the number or value of DATA in the SIP) , So that the device 95 is set to " NOR-0 ". The number of DATAs in SIP is replaced by the number of incremented addresses. All commands (in SIP) except DATA are bypassed. Thus, the incremented DATA (01h), CMD (39h), TDA (00h), and TYPE (NAND flash) included in the SOP are output. Since the device 95 is the last device, the output SOP is sent to the memory controller 50. These operations are performed during a period TP2-n between transition of IPE_n to high and transition of IPEQ to high. The command output from the device 95 is sent to the memory controller 50 as feedback during the period TP2-SO. The memory controller 50 recognizes the total number of NO-type devices that are " 1 " in the value or number of DATA.

Thereafter, at time TAME, the memory controller 50 issues another write device address operation for the other device type. If there are no more device types to be initialized, the system 44 is ready for normal operation (e.g., step 2 as shown in FIG. 2C).

Exemplary details will now be provided in connection with the previously introduced examples with reference to Figures 3A-3F. These details relate to implementations with type-dependent addressing. In these implementations, each memory device has a device type and a device address, both of which are used for addressing purposes. Alternative implementations use type-dependent addressing, the details of which are provided under a different section header. It is understood that the details provided in this section are highly specific for illustrative purposes only.

Figure 8 shows a timing sequence for signals of an exemplary input with type-dependent addressing. This timing diagram can be applied to all memory devices of the exemplary memory systems described above with reference to Figures 3A to 3F. At the top of the timing diagram, signals are plotted for a chip selection (CS #) as indicated by 8-1 and a serial clock (SCLK) as indicated by 8-2. The timing diagram also shows the signals for the input interface, namely the input enable (IPE) as indicated by 8-3, the serial input (SIP) as indicated by 8-4, and 8-5 And an output enable (OPE) as shown. The timing diagram also includes a signal from the output interface, i. E., A serial output (SOP) as indicated by 8-6.

Chip select CS # 8-1 is active 'low' and therefore must be 'on' to enable all of the memory devices connected to the memory system. SCLK 8-2 is a free running serial clock signal. IPE 8-3 has a transition from logic 'low' to logic 'high' indicating the start of the input stream of byte mode serialized. A memory device receiving IPE 8-3 in a logic high state must be prepared to handle data streaming through the SIP port of the byte mode definition. The first byte of SIP 8-4 carries information of 'device type'. The first byte includes 8 cycles of SCLK 8-2 with rising edges where the MSB (highest) is the first and the LSB (lowest bit) is the last. After the first byte, the second byte of the SIP 8-4 continues to carry the 'device address' information (e.g., the target device address TDA). The third byte carries the 'command' information followed by the second byte and the 'fourth', 'fifth', and / or sixth or more bytes followed by 'row / column addresses'. If applicable (e.g., write-related operations), one or more data input bytes follow.

As shown in the timing diagram, the arrangement of the 'serial byte' of SIP 8-4 with IPE 8-3 is defined as a series of 8 clock cycles using the rising edge of SCLK 8-2. In other implementations, falling edges of SCLK 8-2 may also be used. If both the rising and falling edges of SCLK 8-2 are used, only four clock cycles will be needed to form a 'serial byte' due to the 'double-edge' of clocking. One byte contains 8 bits, and one bit indicates a state of logic 'high' or logic 'low'.

In the illustrated example, since the memory device is not capable of outputting data to the next memory device, SOP 8-6 is shown as a logical 'do not care'. However, if the memory device was capable of outputting data to the next memory device, the memory device would have an output enable (OPE) driven logic ' high '

Alternatively, the bytes of SIP 8-4 carry information that the LSB goes first and the MSB goes to the last location.

An example in which a memory device receives data and transfers the data to the next memory device is provided below with reference to FIG.

Figure 9 shows a timing sequence of exemplary signaling through two adjacent memory devices. This timing diagram can be applied to each phase of the neighboring memory devices of the exemplary memory systems described above with reference to Figures 3C, 3D, 3E and 3E. In this example, the first device named Device 0 and the second device named Device 1 have been selected for illustrative purposes. The suffixes '_D0' and '_D1' of all signal names represent two devices, device 0 and device 1, respectively, for purposes of illustration. At the top of the timing diagram, the signal is floated for the serial clock SCLK as indicated by 9-1. The timing diagram then shows the input enable (IPE_D0), serial input (SIP_D0), and output enable () signals as indicated by signals for the input interface of device 0, 9-2, 9-3 and 9-4, respectively OPE_D0). The timing diagram then shows the serial output (SOP_D0), input enable echo (IPEQ_D0), and the serial output (SOP_D0) as indicated by the signals for the output interface of the device 1, namely 9-5, 9-6 and 9-7, And an output enable echo OPEQ_D0. The timing diagram then shows the input enable (IPE_D1), serial input (SIP_D1), and output enable (as indicated by signals 9-8, 9-9 and 9-10 respectively for the input interface of the device 1 OPE_D1. Signals input to the input interface of the second memory device, Device 1, correspond to signals output from the output interface of the first memory device, Device 0. Next, the timing diagram shows the serial output (SOP_D1), input enable echo (IPEQ_D1), and output enable signal (SOP_D1) as indicated by signals output from the output interface of device 1, Able echo OPEQ_D1.

The timing diagrams are provided for illustrative purposes only, so that the entire waveforms do not represent actual operation. At time T2, the transition of IPE_D0 9-2 from the rising edge of SCLK 9-1 to the logic high state implies the start of a serial data stream-in via SIP_D0 9-3. Next, the device 0 starts receiving SIP_D0 9-3 and processes the appropriate operation according to the serial stream-in information. Also, device 0 echoes the logic high state of IPE_D0 9-4 to IPEQ_D0 9-6 connected to the IPE port of device 1. In addition, the stream-in data of the SIP_D0 9-3 is echoed to SOP_D0 9-5 connected to the SOP port of the device 1. This procedure continues until time T10, at which the logic 'to' state of IPE_D0 9-2 is detected at the rising edge of SCLK 9-1. At the device 1 level, IPEQ_D0 9-6 is directly connected to IPE_D1 9-8 via wiring or other interconnection method, so IPE_D1 9-8 has a signal waveform that is logically identical to the IPEQ_D0 9-7 signal at device 0 level . Since SOP_D0 9-5 is directly connected to SIP_D1 9-9 through wiring or other interconnection method, SIP_D1 9-9 indicates a signal waveform that is logically identical to the SOP_D0 9-5 signal at device 0 level. For device 1, a procedure similar to that in device 0 occurs, resulting in the echo to SOP_D1 9-11 of SIP_D1 9-9 and the echo to IPEQ_D1 9-12 of IPE_D1 9-8.

In the illustrated example, there is one clock cycle latency for the echo procedure. However, more generally, an appropriate clock cycle latency can be realized. For example, a clock cycle latency of half a clock cycle, two clock cycles, or more than two clock cycles may be implemented. The clock cycle latency across each memory device determines the total clock latency of the memory system. Assuming one clock cycle latency of the system and four devices, the last device's SOP_D3, IPEQ_D3 will have four clock cycle latency from SIP_D0 9-3, IPE_D0 9-2 signals. From T13 to T17 at the device 0 level, the OPE_D0 9-4 signal is active and causes a serial output operation from device 0 via signal SOP_D0 9-5. At time T10, a 9-4 logic high state of OPE_D0 is detected at the rising edge of SCLK 9-1, and then device 0 outputs a serial data stream via SOP_D0 9-5 according to the previous condition of the device Begin. In this example, device 0 is selected to output serial data, and device 1 is not selected, so device 1 sends the SIP_D1 9-9 signal (same to SOP_D0 9-5) to the SOP_D1 9-11 port, Only. The serial output operation with the OPE ports has the same clock latency as the serial input procedure.

In the examples described with reference to Figures 3A-3F, an output enable echo (OPEQ) 69 from the end device 83, 87, 91, 95 or 99 is connected to each memory controller 50. In this way, the memory controller 50 need not count the number of clock latencies, as determined by the interconnected devices. The memory controller can detect the rising point of the OPEQ signal from the final device and determine the starting point of the streaming data output stream from the interconnecting devices. In alternative embodiments where the output enable echo (OPEQ) 69 from the end device 83, 87, 91, 95 or 99 is not connected to the memory controller 10, Based on the previous recognition of latency, it can be predicted for the time that serial data will be received via serial input (SIP) 59.

In the timing diagrams described above with reference to Figures 8 and 9, the signals floated for SIP and SOP (if applicable) include memory operations that conform to a predetermined format. A table of exemplary predefined formats for memory operations is described below with reference to FIG.

Figure 10 shows a table of exemplary predefined formats for memory operations with type dependent addressing. It is understood that this table is very detailed for illustrative purposes only. In the table,

TYPE: Target device type

TDA: target device address

CMD: Command code

CA: column address

RA: row address

Note 1: The TDA (Target Device Address) is '00h' when the first write device address command is issued after a power-up or hard reset.

Referring to FIG. 10, the table shows various formats for different memory operations. In the table, there are eight memory operations listed as read, write, erase, read state, read ID, write configuration register, write device address, and reset. There may be other memory operations, but they are not shown for the sake of simplicity. The first byte defines the device type (TYPE). This information can be compared to on-chip preprogrammed device type register values to determine whether a serial input stream of data over the SIP port should or should not be processed. Along with the device type, the second column specifies the target device address (TDA), which is used to distinguish between memory devices of the same device type. The third byte defines the command definition (CMD). If appropriate (e.g., read operations), fourth, fifth, and / or more bytes define row address (RA) and / or column address (CA) information, if appropriate. If appropriate (eg, write operations), define the data (DATA) by which additional bytes are sent by the operation.

The device type, device address, and command are encoded in such a way that they are specific to the device type. Exemplary encoding schemes are described below with reference to FIGS. 10-13. It is understood that these schemes are highly detailed for illustrative purposes only. The encoding schemes may be changed by the producers in different ways for their own use.

Figure 11 shows a table of an example encoding scheme for type-dependent addressing. In the table,

DA [7: 0]: device address (in this example, the maximum number of devices = 2 ⁸ = 256)

DA [11: 0]: column address (in this example, the maximum number of columns = 2 ¹² = 4,096)

DA [17: 0]: The row address (in this example, the maximum number of rows = 2 ¹⁸ = 262,144)

Referring to FIG. 11, the table defines an encoding scheme for a device address (TDA), a row address (RA), and a column address (CA). In this example, since the device address has a total of 8 bits, the total number of devices that can be configured in this system is 2 ⁸ = 256. However, the device address definition may be appropriately extended using other serial byte (s). The row address and column address bytes are also shown in a manner similar to the device address format. As noted above for the table of FIG. 5B, the table definition may alternatively be in the reverse order, with the LSB first.

Figure 12 shows a table of an example encoding scheme for NAND Flash instructions with type-dependent addressing.

In the table,

* 1: Target DA must be 00h when a 'write device address' command is issued after power-up or hard reset.

* 2: The row and column address bytes may not be provided if the co-located page read command was issued before.

Referring to Figure 12, the table includes a page read, a random read, a page read for copy, a target address input for copy, a serial data input, a random data input, a page program, a block erase, A write configuration register, a write device address, and a reset scheme. Each instruction includes a device type (device TYPE) which is '00h' for the NAND flash memory according to the table of FIG. 5B. Next, each command includes a device address (target DA), which is indicated as " valid ". The device address may identify any device address to select a particular device of the serial interconnection. The device address column may be extended to more bytes if appropriate. Next, each command contains a command definition. The illustrated command definition is similar to a general NAND flash memory command definition. The fourth column and the fifth column in the table represent the row address and the column address, respectively, for selection of the specific row and column positions of the memory cell array block of the NAND flash device. As shown in the table, some instructions do not include row and / or column addresses.

The number of bytes for each row and column address range may vary depending on the memory array size for a particular density. The row address and the column address can be switched in either manner. Thus, the column address bytes may alternatively be the first and the row address bytes may follow the column address. It depends on the specific memory chip design preference. The final column shows an input data column definition for the 'write' operation commands, for example, 'serial data input 80h', 'random data input 85h' and 'write configuration register A0h' . This input data byte may be as many as N bytes or as small as one byte, depending on the device details. The 'read status 70h' command is needed to check the status of each device using the same serial link port SOP, otherwise each device needs a separate extra hard pin for status indication purposes . It may be changed to a different hex-number definition. If the interconnected devices use the number of soft generating devices instead of the hard pin configuration, the 'recording device address 39h' command is used. The 'Reset (FFh)' command can perform a soft reset function on each selected device. This soft reset distinguishes it from a 'hard reset' using the 'RST #' port connected to all devices in the interconnect.

Figure 13 shows a table of an example encoding scheme for a NOR flash command with type-dependent addressing. In this table,

Note 1: The target DA shall be 00h when the 'write device address' command is issued after power-up or hard reset.

Note 2: The row and column address bytes may not be provided if the co-located page read command was issued before.

The table of FIG. 13 follows a format similar to the table of FIG. However, the table of Fig. 13 is a table in which the table is read out, the buffer is written, the buffer is programmed (confirmed), the chip is erased, the sector erase, the program / erase pause, the program / erase resume, A write address, and a different set of reset. Each instruction includes a device type (device TYPE) which is '01h' for the NOR flash memory according to the table of FIG. 5B. Next, each command includes a device address (target DA), which is indicated as " valid ". If interconnected devices use a soft-generated device number instead of a hard-pin configuration, the 'record DN entry (39h)' command is used. As in the table of FIG. 12, the 'reset (FFh)' command can perform a soft reset function on each selected device. This soft reset distinguishes it from a 'hard reset' using the 'RST #' port connected to all devices in the interconnect.

Figure 14 illustrates a method for handling memory operations with type-dependent addressing. This process shows a general concept. Certain commands or operational flow charts may be different from this example. For example, an operation that does not include read or write data does not involve data transfer. Also, if the instruction does not include a row or column address, the memory device does not transmit row / column address bytes. When the serial signal stream bytes are bypassed through the IPE, SIP, OPE or SOP of each device in the interconnect, if the bypass circuit is designated as one clock latency, there is one clock cycle latency.

14, when a memory device receives a memory command, the memory device compares the device type indicated by the memory command with its own device type indicated by its own type register (step 14 -One). The memory command is specific to the type of device displayed in the memory command. The memory device determines whether the device type of the memory instruction matches its device type (step 14-2). If there is a type match between the two device types (YES in step 14-2), the memory device stores the device address indicated by the memory command with its own device address indicated by its own address register (Step 14-3). The memory device determines whether the device address of the memory command matches the device address of its own register (step 14-4). If there is an address match (YES in step 14-4), the memory device executes the command (step 14-5). In accordance with the instructions, this may include a memory device that processes the row and column addresses represented by the memory command, and may also include processing the received data as part of the memory command. However, if there is no match in the device type (NO in step 14-2), or if there is no match in the device address (NO in step 14-4), the memory device will issue a memory command The internal processing is not executed (step 14-6). In order to provide a further description of the process of handling the memory operations described above with reference to Fig. 14, a timing diagram will be described below with reference to Figs. 15A and 15B.

15A and 15B show timing sequences for signals for handling memory operations with type-dependent addressing. The timing diagram illustrates exemplary signals that may result from the memory system of FIG. 3B, having three NAND-type flash devices 85, 86, 87 and one NOR-type flash device 84 interconnected Respectively.

Memory instructions for page reading of the NAND flash devices issued by the memory controller include:

Memory instructions (4)

TYPE
(00h) TDA
(01h) CMD
(00h) low /column
Address

to be.

For a memory instruction,

TYPE (00h) identifies " NAND flash " devices (see FIG. 5B).

The TDA 01h identifies the devices holding device address " 1 ".

CMD (00h) identifies the action for which " page read " is to be performed.

The row / column address identifies the row and column addresses of the memory, instead of the DATA.

Similarly, memory instructions for page reading of a NOR flash device include:

Memory instructions (4)

TYPE
(01h) TDA
(01h) CMD
(00h) low /column
Address

to be.

Referring to Figures 3B, 15A, and 15B, the NOR-type flash device 84 is the first device of the interconnect (i. E., Closest to the memory controller 50). It has a unique type plus device number (or type plus device identification, or type plus device address) as 'NOR-0'. The NAND-type flash devices 85, 86, ..., and 87 connected in series next to the NOR-0 device 84 have unique device numbers' NAND-0 ',' NAND- And 'NAND- (n-1)'. At the top of the timing diagram there is a signal for the serial clock SCLK, denoted by 15-1. Next, the timing diagram is shown for serial input (SIP) to each memory device 84,85, 86, ..., and 87, respectively, represented as 15-2, 15-3, 15-4, Lt; / RTI > Next, the timing diagram shows the output enable (OPE) for each of the memory devices 84, 85, 86, ..., and 87, indicated by 15-6, 15-7, 15-8, Lt; / RTI > Next, the timing diagram includes a signal for the output enable echo (OPEQ) for the final memory device 87, denoted by 15-10. Finally, the timing diagram shows the serial output (SOP) for each memory device 84, 85, 86, ..., and 87, represented as 15-11, 15-12, 15-13, Lt; / RTI > For the sake of brevity, other signals such as IPE, CS #, RST # are not shown in the timing diagrams. In this timing diagram, the 'page read command set for NAND-1', as shown at 15-15, includes a device type (TYPE = NAND), a target device address (DA = 1) It is issued first with a row / column address. The serial stream of these input signals sequentially passes through the devices and processes a " page read " command within the device, given only the selected device (in this case, NAND-1). In general, a NAND-type flash memory takes a longer time (typically 20 μs) for an internal 'page read operation' that transfers data from the NAND flash cells to the data register block. Therefore, the memory controller has to wait for 20 [mu] s of time. However, the memory controller can access the NOR-type flash device, NOR-0, while waiting for the long page read time of the NAND-1. Thus, as indicated by 15-16, the 'page read command set for NOR-0' is issued immediately after the 'page read command set for NAND-1'. The NOR-type flash memory has a very fast read access time, such as, for example, 100 ns, and therefore the memory controller can perform many fast operations such as 'demand paging' from NOR-0. 'Request paging' is a simple way to implement virtual memory.

In a system using demand paging, the operating system copies the page into physical memory only if an attempt is made to access it (i.e., a page fault occurs). This results in a large number of page faults occurring until the process starts executing without its own pages in physical memory and the working set of pages of most processes are placed in physical memory. As indicated by 15-17, the last read data output from NOR-0 is the sum of the number of connected memory devices is 4, so that after four clock cycle latency, the SOP port of NAND-2, which is directly connected to the SOP port of the controller appear. After a long wait, the memory controller can access the NAND-1. At this time, as indicated by 15-18, the memory controller generates the page read instruction set for NAND-1 without the row / column address bytes, and sets the OPE 15-6 signal to logic ' To a logic ' high ' state which enables the output circuitry of the NAND-1 device from the NAND-1 device, and then the read data output from the NAND-1 is routed through the SIP / SOP ports connected in series, It starts to be streamed out. There is 4 clock cycle latency on the final data output of the SOP port of the memory controller.

Figure 16A shows another example memory device block used as the memory devices shown in Figures 3A-3E. The memory device 140A shown in Figure 16A is similar to the memory device 140A shown in Figure 4A. Referring to FIG. 16A, the address increment operator 149 performs an operation in response to an initial-stage request from the device controller / processor 142A. In such a specific example, the device address to be assigned is the device address incremented by that device. Each device executes the device address assignment method shown in Fig. 6A. However, steps 6-10 and 6-11 shown in FIG. 6B are opposite to those shown in FIG. 16B.

Referring to Figures 3B, 4A, 16A, and 16B, the device receiving the recording device address operation determines whether the received device type ('DTs') matches its device type registered in the device type register 146 (Step 16-8). If there is a device type match (YES in step 16-8) or a device type match result, the address match determiner 147 determines that the target device address TDA (i.e., 'DAs') is registered in the device address register 148 It is judged whether or not the device address DAr matches the device address DAr (step 16-9). If there is a device address match (YES in step 16-9) or a device address match result, the device address match determiner 147 outputs an address match indication 147M. The received device address ('DA') is then incremented by the address increment operator 149 (step 16-10). The incremented address ('DA + 1') is registered in the device address register 148 (step 16-11) and the incremented device address is transferred to the next device. If there is no device type match (NO in step 16-8), or if there is no device type match result, neither device address arrangement nor device address increment will be performed. Also, if there is no device address match (NO in step 16-9) or there is no device address match result, no device address alignment or address increment will be performed.

16C illustrates another device address arrangement operation performed by the apparatus of FIG. 6A. Steps 16-8 and 16-9 of Figure 16C are consistent with those of Figure 16B. If there is a device type match (YES in step 16-8) and a device address match (YES in step 16-9), the received device address ('DA') is incremented by an address increment operator 149 16-12). The incremented address (DA + 1 ') is registered in the device address register 148 (step 16-13) and the incremented device address is transferred to the next device (step 16-14).

Figure 17 shows another example memory device block used as the memory devices shown in Figure 3F. The memory device 140B shown in Fig. 17 is similar to the memory device 140A shown in Fig. 4A. Referring to FIG. 17, the address increment operator 149 performs an operation in response to an initial stage request from the device controller / processor 142B. Device 140B performs operations similar to those of FIG. 16B. The incremented device address provided by the address increment operator 149 is registered in the device address register 148 and sent to the next device.

18 shows a two-channel memory system according to another embodiment of the present invention. Referring to FIG. 18, the first channel of memory controller 150 is connected to a first serial interconnect configuration 151 of memory devices connected via a serial link. Similarly, the second channel of the memory controller 150 is connected to a second serial interconnect configuration 152 of memory devices connected via a serial link. The serial output (SOP), input enable echo (IPEQ) and output enable echo (OPEQ) from each final device of the serial interconnect configuration 131 are fed back to the memory controller 150.

The details of the first serial interconnect configuration 151 of memory devices are shown in Figure 19A. The details of the second serial interconnect configuration 152 of memory devices are shown in Figure 19B.

19A, a first serial interconnect configuration 151 of memory devices includes (n + 1) NOR flash memory devices 160, 161, 162, ..., and 163 interconnected in series, . The devices 160, 161, 162, ..., and 163 have NOR flash memory cores 160A, 161A, 162A, ..., and 163A, respectively. Each of the devices 160, 161, 162, ..., and 163 has a register 60 for holding its own memory type (NOR flash). NOR-1 ", " NOR-2 ", ..., and "Quot; NOR-n ". The assigned device addresses are held in registers (not shown) of the devices.

Referring to Figure 19B, a second serial interconnect configuration 152 of memory devices includes (n + 1) NAND flash memory devices 170, 171, 172, ..., and 173, . The devices 170, 171, 172, ..., and 173 have NAND flash memory cores 170A, 171A, 172A, ..., and 173A, respectively. Each of the devices 170, 171, 172, ..., and 173 has a register 60 for holding its own memory type (NAND flash). NAND-1 ", " NAND-2 ", ..., and "Quot; NAND-n ". The assigned device addresses are held in registers (not shown) of the devices.

Alternatively, the first serial interconnect configuration 151 of memory devices may include mixed type devices. Also, the second serial interconnect configuration 152 of memory devices may include mixed type devices.

20A and 20B show a schematic diagram of memory devices of another specific example used in the memory system shown in Fig. 20A, a first serial interconnect configuration 151 of memory devices includes (n + 1) memory devices 210, 210A, 210A, and 213A having the same memory cores 210A, 211, 212, ..., and 213, respectively. 3B, the first memory device 210 has a NOR flash memory core 210A and the second, third, ..., and (n + 1) memory devices 211 212, ..., and 213 have NAND flash memory cores 211A, 212A, ..., and 213A, respectively. Fig. 3C differs from the Fig. 3B example in that a type-wise addressing scheme is employed, i.e., a previously addressed first addressing scheme. 1 ", and " NAND- (n-1) ", the type plus address is assumed to be NOR-O, NAND-O, NAND- ) '.

20B, the second serial interconnect configuration 152 of memory devices includes a plurality of (n + 1) memory devices 220A, 221A, 222A, ..., and 223A having mixed memory cores 220A, 220, ..., and 223, respectively. The first memory device 220 has an SRAM memory core 220A and the second memory device 221 has a NOR flash memory core 221A. Third, ..., and (n + 1) th memory devices 223 have NAND flash memory cores 222A, ..., and 223A, respectively. Memory devices are addressed using a type-wise addressing scheme. Assuming that there are one SRAM device, one NOR device, and (n-1) 'NAND devices, the type plus address is' SRAM-0', 'NOR-O', 'NAND-O', ... , And 'NAND- (n-2)'.

In the previously described embodiments, one memory command (e.g., a " recording device address " command of the SIP) does not overlap with another memory command (e.g., the " recording device address " In other implementations, the memory instructions of the serial input to the devices may not overlap those shown in FIG. However, if required, the device address (DATA) increment by one device must be completed before the other device can perform the address (DATA) increment.

It will be apparent to those skilled in the art that the transmission of data, information or signals is performed by a single bit or a plurality of bits. For example, data transmission on a serial input SIP and serial output SOP is performed by a single bit or a plurality of bits (M bits), as shown in FIG. 22, where M is an integer greater than one. The interface may include a single I / O pin or a plurality of I / O pins.

23 shows a memory system according to another embodiment of the present invention. The memory system shown in Fig. 23 includes a memory controller 350 that controls the serial interconnection configuration of a plurality of memory devices 351 and the operation of the devices. In the illustrated example, the configuration includes (n + 1) memory devices: Device-0, Device-1, Device-2, ... And a device-n. Each memory device has a plurality of ports. In the specific example of Fig. 24, each device is a two-port device. The memory controller 350 provides a reset signal " RST # ", a chip select signal CS #, and a serial clock signal SCLK to each port of each memory device.

23 and 24, the first memory device (device-0) includes a plurality of data input ports SIP1 and SIP2, a plurality of data output ports SOP1 and SOP2, a plurality of control input ports IPE1 and IPE2, And a plurality of control output ports OPE1 and OPE2. Data and control signals are transferred from the memory controller 350 to the first memory device. The second memory device (device-1) has the same type of port as device-0 to which device-1 is connected. For example, Device-1 receives data and control signals from Device-0. The final memory device (device-n) in the configuration returns to the memory controller 350 after a predetermined latency to provide data and control signals. Each memory device outputs the echoes (IPEQ1, IPEQ2, OPEQ1, OPEQ2) of IPE1, IPE2, OPE1 and OPE2 (i.e., control output port) to the subsequent device.

Figure 25 illustrates a memory system in accordance with another embodiment of the present invention. The memory system shown in Fig. 25 includes a serial interconnect configuration of a memory controller 450 and a plurality of memory devices 451. The configuration of the devices is shown in Fig. Each memory device has a plurality of ports. In the specific example of Fig. 26, each device is a two-port device. The memory controller 450 provides the memory devices with a plurality of groups of signals corresponding to the plurality of ports. In the illustrated example, reset signal "RST # 1 ", chip select signal" CS # 1 "and serial clock signal" SCLK1 "are provided to each port 1 of each memory device. Similarly, for port 2, a reset signal "RST # 2", a chip select signal "CS # 2", and a serial clock signal "SCLK2" are provided to each port of each memory device.

In the memory system and apparatus shown in Figs. 23-26, the devices shown in Figs. 4A and 16A can be used in a serial interconnect configuration of memory devices. In addition, the devices shown in Figures 4B and 17 may be used in a serial interconnect configuration of memory devices. In such a case, the clock signal SCLK needs to be transmitted as shown in FIG. 3F, and each device has a clock synchronization circuit for providing an output echo clock signal 'SCLK_O' for the next device.

In the embodiments described above, the device elements and circuits are connected to each other as shown in the figures for the sake of simplicity. In an actual application of the present invention, elements, circuits, and the like may be directly connected to each other. Of course, elements, circuits, and the like may be indirectly connected to each other through devices or other elements, circuits, and the like necessary for operation of the device. Thus, in the actual configuration of devices and devices, the devices and circuits are directly or indirectly coupled or interconnected.

It will be apparent to those skilled in the art that semiconductor devices can be realized as devices.

The embodiments of the present invention described above are intended to be examples only. Modifications, alterations, and modifications may be made by those skilled in the art to the particular embodiments, without departing from the scope of the invention as set forth solely by the claims appended hereto.

Claims (59)

A semiconductor device for use in a serial interconnection configuration of a plurality of devices of mixed type, the plurality of devices being interconnected in series, the semiconductor device comprising: An input for receiving a serial input comprising device type identification, command and device address identification; A device type holder for holding a device type indicating a type of device; An address holder holding an assigned device address; an assigned address indicating an address of the device; A first comparator for comparing the device type identification of the serial input with the device type held by the device type holder and for providing a device type comparison result to determine if the device type identification is associated with a held device type; A second comparator for comparing the device address identification with a device address held by the address holder to determine if the device address identification is associated with a held device address and for providing an address comparison result; And And an instruction executing section for executing the instruction in accordance with a judgment in response to the first and second comparison results. The method according to claim 1, And the second comparator is configured to compare the device address identification with the held device address in response to the device type comparison result. The method of claim 2, Wherein the first comparator comprises a tangible match determiner for determining whether the device type identification matches the held device type and for providing a device type match result or a device type mismatch result as a result of the device type comparison, Wherein the second comparator comprises an address match determiner for determining whether the device address identification matches the held device address and for providing a device address match result or a device address match match result as the address comparison result. The method of claim 3, Wherein the instruction execution unit includes a device controller, The device controller comprises: Control operation of the device in response to the received serial input; In response to the device type match result and the device address match result, executes the instructions contained in the received serial input. The method of claim 4, The device controller In response to any one of a device type mismatch result and a device address mismatch result, sending the device type identification of the received serial input, the command, and the device address identification to the next device in the serial interconnection configuration, A semiconductor device. The method of claim 4, The apparatus comprising a memory; The serial input including data information including information data about the memory; Wherein the device controller is capable of executing the instruction based on information data about the memory to access the memory in response to the device type match result and the device address match result. The method of claim 6, The device controller is further configured to cause the device type identification, the device address identification, the command, and the data included in the received serial input to be stored in the memory in response to any of the device type mismatch result and the device address mismatch result To a next device in a serial interconnection configuration. 7. The semiconductor device of claim 6, wherein the memory comprises one of a NAND Flash EEPROM, a NOR Flash EEPROM, an AND Flash EEPROM, a DiNOR Flash EEPROM, a Serial Flash EEPROM, a DRAM, a SRAM, a ROM, an EPROM, a FRAM, . delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete

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