JP2010283130A - Interposer, semiconductor device and electronic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an interposer with a thermoelectric conversion element that can cool a semiconductor chip without hindering a high-frequency operation of a semiconductor device. <P>SOLUTION: The interposer 200 includes a substrate 210 and a plurality of vias 220 penetrating the substrate. The plurality of vias 220 include a first via 220V and a second via 220G; when the semiconductor chip is mounted on the interposer 220, a first current path including the first via 220V constitutes a power supply path and a second current path including the second via 220G constitutes a ground path. The power supply path includes at least one N-type thermoelectric conversion layer 217N and the ground path includes at least one P-type thermoelectric conversion layer 217P. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an interposer having a thermoelectric conversion element, and a semiconductor device and an electronic device including such an interposer.

  As electronic devices such as servers, personal computers, and network devices become more multifunctional and sophisticated, higher integration and higher performance of semiconductor devices such as integrated circuits (ICs) and large-scale integrated circuits (LSIs) Is underway.

  In a high-performance LSI such as a central processing unit (CPU), it is important to keep the impedance of a power supply system low until reaching a high frequency region in order to prevent malfunction due to switching noise or the like. In the high-frequency region, the inductance of the power supply system is dominant. Therefore, a high-performance LSI typically has a configuration in which a large number of power supply terminals and ground terminals are arranged at a narrow pitch, and a large number of decoupling capacitors are arranged around such an LSI. Due to the high frequency operation of the LSI, the decoupling capacitor is connected to the power supply terminal and the ground terminal of the LSI with the shortest possible wiring length. As one technique for this purpose, a technique is known in which a decoupling capacitor is provided in an interposer between an LSI and a circuit board on which the LSI is mounted.

  In addition, a high-performance LSI such as a CPU consumes a large amount of power and generates a large amount of heat. In order to prevent thermal runaway of the LSI and to ensure stable operation, it is important to efficiently dissipate heat from the LSI. However, since a semiconductor chip such as a high-performance LSI has a large number of terminals (pads) arranged at a narrow pitch as described above, it is generally flip-chip mounted using a large number of bumps. For this reason, it is difficult to provide a heat dissipation mechanism on the surface side of the semiconductor chip, and heat dissipation from the surface side is limited to those that are less effective, such as reducing the thermal resistance of a circuit board on which the semiconductor chip is mounted. It was. That is, the heat radiation from the semiconductor chip is substantially performed only from the back side.

  In recent years, a method for promoting heat dissipation from the surface side of a semiconductor chip such as an integrated circuit chip, that is, from the bump side has been proposed. For example, a method of forming a Peltier element inside the semiconductor chip itself is known. However, such a method for forming a Peltier element in a semiconductor chip has various problems such as complicating the semiconductor chip manufacturing method and consuming precious area resources of the semiconductor chip.

  In addition, a second interposer is disposed between the semiconductor chip and the first interposer on which the semiconductor chip is mounted. Peltier elements and electrical wiring are dissipated from the surface of the second interposer. A method for forming a structure to be formed is known. Furthermore, in this method, a method is proposed in which a current output from a semiconductor chip is configured to flow through a Peltier element, and the semiconductor chip is cooled using a power supply for the semiconductor chip.

JP 2008-049333 A JP 2008-153393 A JP 2008-244370 A

  In the conventional method of forming a Peltier element on the surface of the second interposer, the wiring formed on the surface of the second interposer and the wire bonding for connecting the second interposer and the first interposer are used. Thus, the semiconductor chip is connected to the circuit board. Therefore, the wiring is long and its inductance is large. Therefore, this method cannot be applied to a high-performance LSI because it hinders the high-frequency operation of the semiconductor chip. Further, when the Peltier element formed on the surface of the second interposer is configured so that the output current from the semiconductor chip flows, the inductance of the power supply wiring further increases.

  Therefore, it is desired to realize a heat dissipation mechanism that can cool a semiconductor chip using a power source for the semiconductor chip without hindering high-frequency operation of the semiconductor device.

  According to one aspect, an interposer having a substrate and a plurality of vias passing through the substrate is provided. The plurality of vias include a first via and a second via. When a semiconductor chip is mounted on the interposer, the first current path including the first via constitutes a power supply path, and the second via A second current path including the above constitutes a ground path. The first current path or power path has at least one N-type thermoelectric conversion layer, and the second current path or ground path has at least one P-type thermoelectric conversion layer.

  According to another aspect, a semiconductor device having a semiconductor chip and an interposer on which the semiconductor chip is mounted is provided. The interposer has a substrate and a plurality of vias penetrating the substrate. The semiconductor chip has a power pad and a ground pad, and the plurality of vias of the interposer includes a power supply via electrically connected to the power pad of the semiconductor chip and a ground electrically connected to the ground pad of the semiconductor chip. Including vias. The power path of the interposer including the power via has at least one N-type thermoelectric conversion layer, and the ground path of the interposer including the ground via has at least one P-type thermoelectric conversion layer.

  According to another aspect, an electronic device is provided that includes a semiconductor chip, a circuit board, and an interposer disposed between the semiconductor chip and the circuit board. The semiconductor chip has a power supply pad and a ground pad, and the circuit board has a power supply wiring and a ground wiring. The interposer has a substrate and a plurality of vias penetrating the substrate, the plurality of vias being electrically connected to the power supply pad of the semiconductor chip and the power supply wiring of the circuit board, and the semiconductor chip A ground via and a ground via electrically connected to the ground wiring of the circuit board are included. The power path of the interposer including the power via has at least one N-type thermoelectric conversion layer, and the ground path of the interposer including the ground via has at least one P-type thermoelectric conversion layer.

  Wiring to the semiconductor chip includes signal wiring in addition to power supply wiring and ground wiring. The interposer also requires through vias that serve as signal paths. A thermoelectric conversion layer is formed in this path. Then, since the signal quality is deteriorated, it is preferable not to form a thermoelectric conversion layer in the signal path.

  An interposer having a thermoelectric conversion element that can be used for a semiconductor device that operates at a high frequency and can dissipate heat generated in a semiconductor chip without using a new power supply, and includes such an interposer. Semiconductor devices and electronic devices are provided.

1 is a cross-sectional view illustrating an electronic device according to an embodiment. It is sectional drawing which shows the interposer according to 1st Embodiment. It is sectional drawing which shows the manufacturing method of the interposer according to 1st Embodiment. It is sectional drawing which shows the manufacturing method of the interposer according to 1st Embodiment. It is sectional drawing which shows the 1st modification of the interposer according to 1st Embodiment. It is sectional drawing which shows the 2nd modification of the interposer according to 1st Embodiment. It is sectional drawing which shows the interposer according to 2nd Embodiment. It is a graph which shows the impedance of the power supply system seen from the semiconductor chip. It is sectional drawing which shows the manufacturing method of the interposer according to 2nd Embodiment. It is sectional drawing which shows the manufacturing method of the interposer according to 2nd Embodiment. It is sectional drawing which shows the manufacturing method of the interposer according to 2nd Embodiment. It is sectional drawing which shows the 1st modification of the interposer according to 2nd Embodiment. It is sectional drawing which shows the 2nd modification of the interposer according to 2nd Embodiment. It is sectional drawing which illustrates the mounting form of an electronic device.

  Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. In the drawings, various components are not necessarily drawn to the same scale. Throughout the drawings, the same or corresponding components are denoted by the same or similar reference numerals.

(First embodiment)
With reference to FIGS. 1 and 2, an interposer according to a first embodiment, and a semiconductor device and an electronic device including the interposer will be described. FIG. 1 is a cross-sectional view schematically showing an electronic device 100 according to an embodiment, and FIG. 2 is an enlarged cross-sectional view showing an interposer 200 according to the first embodiment included in the electronic device 100.

  Referring to FIG. 1, an electronic device 100 according to the present embodiment includes a circuit board 110, a semiconductor device 120 mounted on the circuit board 110, and a heat dissipation plate 130 disposed on the semiconductor device 120.

  The circuit board 110 is not particularly limited, and is, for example, an insulating board made of resin, glass, ceramic, or the like, and includes a patterned conductive layer 114 on the surface 111 thereof. The circuit board 110 may include a conductive layer also on the back surface 112 and / or inside thereof. The conductive layer 114 preferably includes a plurality of power pads 114V, a ground pad 114G, and a signal pad 114S. Each pad is connected to the front surface 111, the back surface 112, and / or the power wiring, the ground wiring, or the signal wiring formed inside the circuit board 110.

  In addition to the semiconductor device 120, various electronic components such as a capacitor 116 can be mounted on the circuit board 110. Capacitor 116 may preferably be a multilayer ceramic capacitor (MCC). However, other types of capacitors such as electrolytic capacitors can also be implemented. In the illustrated example, the MCC 116 is connected between the power supply pad 114V and the ground pad 114G, and functions as a decoupling capacitor connected to the power supply system of the semiconductor device 120, as will be described in more detail later.

  The semiconductor device 120 includes a semiconductor chip 140 and an interposer 200 including a plurality of through vias 220. The semiconductor chip 140 is not particularly limited. For example, the semiconductor chip 140 is a semiconductor chip such as a CPU that needs to dissipate heat generated during operation. The semiconductor chip 140 has a front surface 141 and a back surface 142, and has a conductive layer 144 on at least the front surface 141. The conductive layer 144 preferably includes a plurality of power supply pads 144V, ground pads 144G, and signal pads 144S.

  The interposer 200 includes a substrate 210 having a thickness of 30 to 50 μm and having a semiconductor or an insulator. For example, the interposer 200 is a Si interposer including a silicon (Si) substrate 210. The substrate 210 has a first surface 211 and a second surface 212, and has conductive layers 214 and 215 on the surfaces 211 and 212, respectively. The conductive layer 214 includes a power pad 214V, a ground pad 214G, and a signal pad 214S. The conductive layer 215 includes a power pad 215V, a ground pad 215G, and a signal pad 215S. Each pad 214 on the first surface 211 of the interposer substrate 210 and each pad 215 on the second surface 212 are electrically connected by a through via 220.

  The power, ground, and signal pads 214 on the first surface side of the interposer substrate 210 are formed at corresponding positions with respect to the power, ground, and signal pads 144 on the front surface side of the semiconductor chip 140 and are connected bumps. 150 is connected. The connection bump 150 is a metal bump such as gold (Au) or a solder bump formed on each pad 144 on the surface 141 of the semiconductor chip 140 or each pad 214 on the first surface 211 of the interposer substrate 210. obtain. Similarly, the power, ground, and signal pads 215 on the second surface 212 of the interposer substrate 210 are formed at positions corresponding to the power, ground, and signal pads 114 on the surface 111 of the circuit board 110. Further, they are connected by connection bumps 160. The connection bump 160 may be a metal bump or a solder bump formed on each pad on the surface 111 of the circuit board 110 or each pad 215 on the second surface 212 of the interposer substrate 210.

  The heat sink 130 is not particularly limited, and includes a metal or an alloy having a low thermal resistance. The heat radiating plate 130 is joined to the back surface 142 of the semiconductor chip 140 via a heat conductive material 170 such as solder or thermal grease.

  The heat generated from the semiconductor chip 140 is also generated by the heat flow 190 from the chip back surface 142 through the heat dissipation plate 130 and the heat flow 190 from the chip surface 141 through the interposer 200 as described with reference to FIG. Dissipated. That is, the semiconductor chip 140 can be cooled substantially from both sides.

  Next, the interposer 200 will be described in more detail with reference to FIG. Here, description will be made assuming that the substrate 210 is a Si substrate. FIG. 2 shows a power supply via 220V, a ground via 220G, and a signal via 220S that are through vias 220 formed in the Si substrate 210. The power supply via 220 </ b> V connects the power supply pad 214 </ b> V on the first surface 211 of the Si substrate 210 and the power supply pad 215 </ b> V on the second surface 212. Similarly, the ground via 220G connects the ground pads 214G and 215G, and the signal via 220S connects the signal pad 214S and the signal pad 215S. As a result, current paths for the power supply, the ground, and the signal penetrating the substrate 210 are formed. An insulating film 230 is formed between each current path (through via 220, pads 214, 215) and the silicon substrate 210, and the current paths are electrically isolated from each other by this insulating film. Note that in the case where the substrate 210 is an insulating substrate, the insulating film 230 may not be formed.

  The power supply pad 214V on the first surface 211 of the Si substrate 210 includes an N-type thermoelectric conversion layer 217N sandwiched between a lower conductive layer 216 and an upper conductive layer 219. The ground pad 214 </ b> G includes a P-type thermoelectric conversion layer 217 </ b> P sandwiched between the conductive layers 216 and 219. The thicknesses of the N-type and P-type thermoelectric conversion layers 217N and P can be set to, for example, 2-3 μm. The signal pad 214 </ b> S does not include a thermoelectric conversion layer between the conductive layers 216 and 219, and instead includes an additional conductive layer 218.

As the thermoelectric conversion material of the N-type thermoelectric conversion layer 217N and the P-type thermoelectric conversion layer 217P, for example, a heavy metal system such as a BiTe system or a PbTe system can be used. In addition, this thermoelectric semiconductor material is a semiconductor system such as Si, SiGe, or SiC, an oxide system such as a CaCo system, CaMn system, ZnO system, or SrTiO ₃ system, and further, a silicide system, a crater system, or a skutterudite system. It is good also as various materials, such as. Generally, as a characteristic index of a thermoelectric conversion material, a figure of merit Z = S ² / (κρ) is used to increase a temperature difference between the heat absorption side and the heat dissipation side. Where S is the Seebeck coefficient, κ is the thermal conductivity, and ρ is the electrical resistivity. In the present embodiment, power factor P = S ² / ρ can be used in place of Z in order to increase the heat flow from the heat absorption side, that is, the semiconductor chip 140 side, to the heat dissipation side, that is, the circuit board 110 side. Therefore, the thermoelectric conversion material of the thermoelectric conversion layers 217N and P may be a material having a relatively low Z and a high thermal conductivity. Table 1 shows the power factor P of main thermoelectric conversion materials. Suitable thermoelectric conversion materials include, for example, BiTe and FeSi ₂ materials that have a higher power factor P than other materials of about 5 × 10 ⁻³ W / mK ² .

  Referring to FIG. 1 again, the thermoelectric conversion layers 217N and P of FIG. 2 are arranged on the power pad 214V and the ground pad 214G on the first surface 211 side of the interposer substrate 210, respectively. Therefore, when a power supply current is supplied from the circuit board 110 to the semiconductor chip 140 via the interposer 200 and then returned to the circuit board 110 from the semiconductor chip 140 via the interposer 200 again, the N-type and P-type thermoelectric conversion layers 217N. , P also flows the current. Then, a current flows from the circuit board 110 side to the semiconductor chip 140 side in the N-type thermoelectric conversion layer 217N, and conversely, a current flows from the semiconductor chip 140 side to the circuit board 110 side in the P-type thermoelectric conversion layer 217P. Therefore, due to the thermoelectric effects of the N-type and P-type thermoelectric conversion layers 217N and P, a heat flow 190 from the semiconductor chip 140 side to the circuit board 110 side is generated in each current path. Accordingly, the heat generated in the semiconductor chip 140 is transferred to the circuit board 150 and dissipated.

  In FIG. 1, the heat flow 190 is shown on the assumption that all the power supply pads 214V and the ground pads 214G have the thermoelectric conversion layers 217N and P of FIG. However, some power supply pads 214V and ground pads 214G may be configured to have thermoelectric conversion layers 217N and P. For example, the thermoelectric conversion layers 217P and N may be arranged only at a position close to such a high temperature point when a local position that can be a high temperature point is known in the semiconductor chip 140 such as a CPU.

  According to the present embodiment, Peltier elements having thermoelectric conversion layers 217N and 217P are arranged in series in the power supply-ground current path of the semiconductor chip 140. Therefore, a new power source and wiring for operating the Peltier element are unnecessary. Therefore, a thermoelectric element can also be incorporated into an interposer having high-density wiring (via) used for a semiconductor chip such as an LSI having bumps formed at high density.

  In addition, a wiring length corresponding to the thickness of the interposer 200 is added to each current path between the circuit board 110 and the semiconductor chip 140 as compared with a case where the semiconductor chip is directly bump-bonded to the circuit board. . However, the length is as short as several tens of μm, and the increase in the equivalent series inductance (ESL) of the power supply system due to this wiring length is a negligible level. Therefore, the influence on the high frequency characteristics of the semiconductor chip 140 is limited. Further, the equivalent series resistance (ESR) of the power supply system also increases due to the insertion of the interposer 200. However, normally, the ESR of a power supply system such as a high-performance LSI is dominated by the ESR component of a decoupling capacitor (for example, MCC 116). Can be ignored.

  The arrangement of the power supply V, ground G, signal S pads (114, 144, 214, 215) and vias 220 is not limited to that shown in FIG. However, it is preferable to form a large number of adjacent power supply path-ground path pairs from the viewpoint of uniform cooling of the semiconductor chip 140 and ESL and ESR.

  Next, a method for manufacturing the interposer 200 according to the first embodiment shown in FIG. 2 will be described with reference to FIGS.

First, as shown in FIG. 3A, a through via opening 220 ′ is formed in the substrate 210. For example, in the case of the Si substrate 210, the through via opening 220 ′ can be formed by etching using an ICP (Induction Coupling Plasma) etching apparatus. An insulating film 230 that is, for example, a thermal oxide film (SiO ₂ film) may be formed in advance on the first surface 211 and the second surface 212 of the Si substrate 210.

Next, as shown in FIG. 3B, an insulating film 230 is formed on the side wall of the through via opening 220 ′. For example, a SiO ₂ film is formed by thermal oxidation on the portion of the Si substrate 210 exposed through the through via opening 220 ′. Note that the insulating film 230 on the surfaces 211 and 212 of the Si substrate 210 may also be formed here.

  Next, as shown in FIG. 3C, the first surface 211 side of the substrate 210 is attached to the pedestal 260, and via filling with a conductor and pad formation on the second surface 212 side are performed. This can be done, for example, by Cu plating. Specifically, first, after Ti and Ni serving as seeds are formed by sputtering, a resist mask having an opening in the pad portion is formed. Then, after Cu plating is performed and excess Cu is removed by polishing, the resist is stripped and the exposed Ti and Ni are removed. As a result, the through vias 220V, G, S for the power supply, the ground, and the signal, and the pads 215 on the second surface are formed.

Next, as shown in FIG. 4A, the substrate 210 is peeled off from the pedestal 260 and inverted, the second surface 212 side is attached to the pedestal 270, and the thermoelectric conversion layer 217 and the first surface 211 side are disposed on the first surface 211 side. A conductive layer 216 serving as a base is formed. For example, first, a Cu / Ni / Ti laminated film is formed as the conductive layer 216 by sputtering and patterned by wet etching. Then, after forming a resist mask having an opening in the pad portion, an N-type thermoelectric conversion layer 217N is formed. For example, (Bi ₂ Te ₃ ) _0.975 (Bi ₂ Se ₃ ) _0.025 is deposited to a thickness of 2 μm to 3 μm by vapor deposition or sputtering. Thereafter, the N-type thermoelectric conversion layer 217N is left only on the conductive layer 216 on the power supply via 220V by lift-off. Similarly, a P-type thermoelectric conversion layer 217P is formed on the conductive layer 216 on the ground via 220G by using a lift-off method. For example, (Bi _0.25 Sb _0.75 ) (Te _0.93 Se _0.07 ) ₃ can be used. As another example, a FeSi ₂ material may be formed by sputtering or the like instead of the BiTe material described above. If necessary, a conductive layer 218 such as a Cu layer is formed on the conductive layer 216 on the signal via 220S. In the formation of the conductive layer 218, a lift-off method can be used as in the thermoelectric conversion layers 217N and P.

  Finally, as shown in FIG. 4B, the conductive layer 219 on the upper layer of each of the power supply, ground, and signal pads 214 is formed by, for example, the lift-off method as in FIG. 4A. The conductive layer 219 can be, for example, a Cu layer.

  Thus, the interposer 200 shown in FIG. 2 is obtained. In addition, the manufacturing method of the interposer 200 is not limited to the above-mentioned method. For example, instead of the lift-off method, other methods such as a pattern formation method by photolithography and etching may be used. When the substrate 210 is a semiconductor substrate other than Si or an insulating substrate, a method for forming the through via opening 220 ′ and the insulating film 230 can be selected from various known methods depending on the substrate material.

  The thus produced Si interposer was placed between the surface of the CPU with power consumption of 100 W and the circuit board, and heat sink fins and fans were placed on the back surface of the CPU to measure the junction temperature on the CPU surface during operation. As a result, it was shown that the junction temperature was reduced by 5 ° C. compared to the case without the interposer.

  Next, a modification of the interposer 200 according to the first embodiment shown in FIG. 2 will be described with reference to FIGS.

  FIG. 5 shows an interposer 300 according to a first modification. The interposer 300 includes a thermoelectric conversion layer on the pad 315 on the second surface 212 side in addition to the pad 214 on the first surface 211 side of the substrate 210. That is, on the second surface 212 side of the substrate 210, the power supply pad 315V has two conductive layers 316 and 319 and an N-type thermoelectric conversion layer 317N therebetween, and the ground pad 315G has two conductive layers 316 and 316 319 and a P-type thermoelectric conversion layer 317P between them. This configuration makes it possible to further enhance the heat dissipation effect 190 from the semiconductor chip disposed on the first surface 211 side of the substrate 210.

  As a further modification, the configuration in which the thermoelectric conversion layers 217N and P are excluded from the pads 214V and G on the first surface 211 side of the substrate 210 in FIG. 5, that is, only on the second surface 212 side of the substrate 210 is shown. A configuration having a thermoelectric conversion layer is also contemplated. This configuration can increase the temperature gradient between both surfaces of the interposer and promote heat dissipation from the semiconductor chip as compared to a configuration having no thermoelectric conversion layer.

  FIG. 6 shows an interposer 400 according to a second modification. The interposer 400 does not have a thermoelectric conversion layer in the power pads 414V and 215V and the ground pads 414G and 215G of the first surface 211 and the second surface 212 of the substrate 210, respectively. Instead, the power supply via 420V and the ground via 420G in the Si substrate 210 are filled with a thermoelectric conversion material. That is, the power supply pad 414V and the ground pad 414G have only a conductive layer, and the power supply via 420V and the ground via 420G function as an N-type thermoelectric conversion layer and a P-type thermoelectric conversion layer, respectively. This configuration makes it possible to form a thicker thermoelectric conversion material (for example, 30 μm to 50 μm) while reducing the total thickness of the interposer and increase the temperature difference between the semiconductor chip and the circuit board. Useful. Note that the power supply via 420V and the ground via 420G may have a laminated structure of a thermoelectric conversion layer and a conductive layer, in which only a part thereof is filled with a thermoelectric conversion material.

  The interposer 400 can be manufactured as follows. After the formation of the insulating film 230 shown in FIG. 3B, for example, by screen printing, an N-type thermoelectric conversion material and a P-type thermoelectric conversion material in the form of a paste of BiTe alloy powder, and a Cu paste are used. The via opening 220 ′ is filled and fired. Preferably, the signal via 420S containing Cu, which has a higher firing temperature than others, is filled and fired first, and then the power supply via 420V and the ground via 420G each having a thermoelectric conversion material are filled and fired. The thermoelectric conversion material in the power supply via 420V and the ground via 420G may be fired simultaneously. Thereafter, pads 414 and 215 having a Cu / Ni / Ti laminated film are formed on each of the first surface 211 and the second surface 212 of the substrate 210 by sputtering, for example.

  The power supply via 420V and the ground via 420G having the thermoelectric conversion layer included in the interposer 400 are also applicable to the interposers 200 and 300 illustrated in FIGS.

(Second Embodiment)
With reference to FIG. 7, the interposer 500 according to the second embodiment will be described. FIG. 7 is a cross-sectional view showing a part of the interposer in an enlarged manner similarly to FIG. 2, and has the same components as the interposer 200 of FIG. Here, a description will be mainly given of portions where the interposer 500 is different from the interposer 200.

  The interposer 500 includes a substrate 210 that is, for example, a Si substrate, and a plurality of vias 220 that penetrate the substrate 210. The interposer 500 also has a pad 214 formed on the first surface 211 side of the substrate 210 and in contact with the via 220, and a pad 215 formed on the second surface 212 side of the substrate 210 and in contact with the via 220. Is included. The power pad 214V includes an N-type thermoelectric conversion layer 217N, and the ground pad 214G includes a P-type thermoelectric conversion layer 217P.

  The interposer 500 further includes a plurality of thin film capacitors 510 in an insulating layer 520 formed on the first surface 211 side of the substrate 210. Each thin film capacitor 510 includes a dielectric layer 512, a lower electrode 511 sandwiching the dielectric layer, and an upper electrode 513. In FIG. 7, the upper electrode 513 is electrically connected to the adjacent power supply pad 214V via the contact 530V, and the lower electrode 511 is electrically connected to the adjacent ground pad 214G via the contact 530G. . Note that the upper electrode 513 of the thin film capacitor 510 (GS) shown between the ground via 220G and the signal via 220S has a cross section (not shown) between another thin film capacitor 510 (for example, the power via 220V and the ground via 220G). The thin film capacitor 510 (VG) in between is connected to the upper electrode 513. In other examples, the thin film capacitor 510 (GS) may be separated from other thin film capacitors and may or may not be formed. When the thin film capacitor 510 (GS) is not used, the contact 530G to the ground pad 214G of the lower electrode 511 can be eliminated.

The dielectric layer 512 of the thin film capacitor 510 has a metal oxide material having a perovskite crystal structure, which is preferably a high dielectric constant dielectric, but other insulating materials such as SiO ₂ , Si ₃ N ₄ , Ta ₂ O _5, etc. You may have a body. Suitable metal oxide materials having a perovskite crystal structure include, for example, (Ba, Sr) TiO ₃ (BST), SrTiO ₃ (ST), BaTiO ₃ , Ba (Zr, Ti) O ₃ , Ba (Ti, Sn ) O ₃ , Pb (Zr, Ti) O ₃ (PZT), (Pb, La) (Zr, Ti) O ₃ (PLZT), Pb (Mn, Nb) O ₃ —PbTiO ₃ (PMN-PT), Pb (Ni, Nb) O ₃ —PbTiO _{3 and the} like.

When a metal oxide material having a perovskite crystal structure is used for the dielectric layer 512, a noble metal such as Ir or Pt or a conductive perovskite oxide such as SrRuO ₃ (SRO) may be used as the material of the lower electrode layer 511. preferable. By using such a material, a high-quality dielectric film with high crystallinity can be grown, and as a result, the value and uniformity of the dielectric constant of the dielectric layer 512 are improved.

As a material of the upper electrode 513, for example, Au, Al, Pt, Ag, Pd, Cu, and alloys thereof can be used. Further, the above metal or alloy may be laminated on a conductive perovskite oxide such as IrO _x or SRO.

  As described above, the interposer 500 includes the power supply, the ground, and the signal vias 220 penetrating the substrate 210, and the thermoelectric conversion layers 217N and P in the power supply pad 214V and the ground pad 214G on the first surface 211 of the substrate. It has the structure which arranged. This configuration makes it possible to form the thin film capacitor 510 together with the thermoelectric conversion element in the interposer.

  The interposer 500 can be used in place of the interposer 200 in the electronic device 100 of FIG. Then, when a power supply current is supplied from the circuit board 110 to the semiconductor chip 140 via the interposer 500 and is returned again from the semiconductor chip 140 to the circuit board 110 via the interposer 500, from the semiconductor chip 140 side to the circuit board 110 side. The heat flow 190 is generated. Therefore, the heat generated in the semiconductor chip 140 is transferred to the circuit board 110 and dissipated. Further, the increase in ESL and ESR of the power supply system due to the insertion of the interposer 500 is at a negligible level.

  Further, the thin film capacitor 510 is connected to the semiconductor chip 140 and functions as a decoupling capacitor. The thin film capacitor 510 is located directly below the semiconductor chip 140 and is connected to the pad 214 bump-connected to the pad 144 of the semiconductor chip 140 without passing through the surface wiring. Therefore, the wiring distance from the semiconductor chip 140 to the thin film capacitor 510 is several orders of magnitude smaller than that of the capacitor 116 that is, for example, an MCC disposed on the circuit board 110. For example, when considering a 10 mm square semiconductor chip 140, the wiring distance from the central portion thereof to the MCC 116 is at least about 7 mm, whereas the wiring distance between the semiconductor chip 140 and the thin film capacitor 510 should be about 10 μm. Can do.

  The interposer 500 may include a thin film capacitor on the second surface 212 side of the substrate 210, that is, on the circuit board 110 side. However, in order to reduce ESR and ESL as much as possible, the interposer 500 preferably includes a thin film capacitor 510 on the first surface 211 side of the substrate 210, that is, on the semiconductor chip 140 side. The interposer 500 may include a thin film capacitor on the second surface 212 side of the substrate 210 in addition to the thin film capacitor 510 on the first surface 211 side of the substrate 210. Forming thin film capacitors on both sides of the substrate 210 requires additional manufacturing steps, but increases the achievable capacitance and the choice of dielectric materials that can be used to obtain the desired capacitance An increase in width or the like may be caused.

  FIG. 8 shows the impedance of the power supply system viewed from the semiconductor chip 140 when the interposer 500 according to an example is used (solid line) and when it is not used (broken line). In this example, the power supply system includes an MCC 116 mounted on the circuit board 110 and a larger capacity electrolytic capacitor in addition to the thin film capacitor 510 built in the interposer 500. By using the interposer 500 incorporating the thin film capacitor 510, the impedance of the power supply system in a high frequency region of several tens of MHz or more is greatly reduced. By combining the thin film decoupling capacitor 510 with the decoupling capacitor on the circuit board 110 or inside the power supply itself, it is possible to suppress the impedance of the power supply system to about 1 mΩ in the entire frequency range up to at least 1 GHz. is there. Moreover, the deterioration of ESR due to the insertion of the interposer is not observed, and it can be seen that the application of the interposer 500 is effective in reducing the power supply impedance.

  Next, with reference to FIGS. 9-11, the manufacturing method of the interposer 500 which concerns on 2nd Embodiment shown in FIG. 7 is demonstrated.

First, as shown in FIG. 9A, after forming an insulating film 230 on at least the first surface 211 of the substrate 210, a thin film capacitor 510 is formed on the insulating film 230 on the first surface 211 side. When the substrate 210 is a Si substrate, the insulating film 230 is a SiO ₂ film formed by thermal oxidation, for example. The thin film capacitor 510 can be formed as follows, for example. First, an Ir / TiO ₂ laminated film, a Ba _0.7 Sr _0.3 TiO ₃ film, and an Au / IrO ₂ laminated film are sequentially formed by sputtering. Then, by ion milling, these films are sequentially removed from a region where a through via is formed later, and an upper electrode 513, a dielectric layer 512, and a lower electrode 511 having a predetermined pattern are formed from each film.

  Next, as shown in FIG. 9B, after the formation of the protective film 520, a through via opening 220 'is formed in the same manner as in the step shown in FIG. For example, as the protective film 520, an alumina insulating film is formed by sputtering.

  Next, after forming an insulating film 230 on the side wall of the through via opening 220 ′ as shown in FIG. 9C, via filling with a conductor and pads on the second surface 212 side as shown in FIG. Form. These steps can be performed in the same manner as described with reference to FIGS. 3B and 3C, respectively. Thereby, the through via 220 and the pad 215 on the second surface 212 side are formed.

  Next, as shown in FIG. 10B, contact holes 530 </ b> G ′ and 530 </ b> V ′ for forming electrical connection with the lower electrode 511 and the upper electrode 513 are formed in the protective film 520. For example, an ion rimming method can be used.

  Thereafter, as shown in FIG. 10C to FIG. 11B, a pad 214 on the first surface 211 side of the substrate 210 is formed. That is, as described with reference to FIGS. 4A and 4B, the conductive layer 216 under the pad 214, the thermoelectric conversion layers 217N and P, and the additional conductive layer of the signal pad 214S as necessary. 218 and an upper conductive layer 219 are formed. When the lower conductive layer 216 is formed, the contact hole 530 ′ formed in the protective film 520 is filled, and a contact 530V to the upper electrode 513 and a contact 530G to the lower electrode 511 of the thin film capacitor 510 are formed. . These contacts may be reversed. That is, the upper electrode 513 of the thin film capacitor 510 and the ground pad may be connected, and the lower electrode 511 and the power supply pad may be connected.

  The thus produced Si interposer was placed between the surface of the CPU with power consumption of 100 W and the circuit board, and heat sink fins and fans were placed on the back surface of the CPU to measure the junction temperature on the CPU surface during operation. As a result, it was shown that the junction temperature was reduced by 5 ° C. compared to the case without the interposer.

  Next, a modification of the interposer 500 according to the second embodiment shown in FIG. 7 will be described with reference to FIGS.

  FIG. 12 shows an interposer 600 according to a first modification. The interposer 600 includes a thermoelectric conversion layer on the pad 615 on the second surface 212 side in addition to the pad 214 on the first surface 211 side of the substrate 210. That is, on the second surface 212 side of the substrate 210, the power supply pad 615V has two conductive layers 616 and 619 and an N-type thermoelectric conversion layer 617N therebetween, and the ground pad 615G has two conductive layers 616 and 616G. 619 and a P-type thermoelectric conversion layer 617P between them. This configuration makes it possible to further enhance the heat dissipation effect 190 from the semiconductor chip disposed on the first surface 211 side of the substrate 210.

  As a further modification, a configuration in which the thermoelectric conversion layers 217N and P are excluded from the pads 214V and G on the first surface 211 side of the substrate 210 in FIG. This configuration increases the temperature gradient between both surfaces of the interposer and promotes heat dissipation from the semiconductor chip as compared to a configuration in which the thermoelectric conversion layer is completely eliminated.

  FIG. 13 shows an interposer 700 according to a second modification. The interposer 700 does not have a thermoelectric conversion layer in the power pads 714V and 215V and the ground pads 714G and 215G on the first surface 211 and the second surface 212 of the substrate 210, respectively. Instead, the power supply via 720V and the ground via 720G in the substrate 210 are filled with a thermoelectric conversion material. That is, the power supply pad 714V and the ground pad 714G have only a conductive layer, and the power supply via 720V and the ground via 720G function as an N-type thermoelectric conversion layer and a P-type thermoelectric conversion layer, respectively. This configuration makes it possible to form a thicker thermoelectric conversion material while reducing the total thickness of the interposer, and is useful for increasing the temperature difference between the semiconductor chip and the circuit board. The power supply via 720 </ b> V and the ground via 720 </ b> G may have a laminated structure of a thermoelectric conversion layer and a conductive layer, in which only a part thereof is filled with a thermoelectric conversion material. The interposer 700 can be manufactured by forming a through via having a thermoelectric conversion material in the same manner as the interposer 400 shown in FIG.

  The power supply via 720V and the ground via 720G having the thermoelectric conversion layer included in the interposer 700 can also be applied to the interposers 500 and 600 shown in FIGS.

  Next, an exemplary implementation of an electronic device having an interposer 800 that is, for example, the interposer 200, 300, 400, 500, 600, or 700 will be described with reference to FIG.

  The electronic device 100 ′ illustrated in FIG. 14A includes a semiconductor chip 140 mounted on the circuit board 110 via the interposer 800. The circuit board 110 may have a decoupling capacitor 116 such as MCC. A heat sink 810 is thermally bonded to the back surface side of the semiconductor chip 140, that is, the surface opposite to the surface to which the interposer 800 is bonded. Further, a heat-radiating plate 820 having a high thermal conductivity such as a metal core substrate is bonded to the back surface of the circuit board 110, that is, the surface opposite to the surface to which the interposer 800 is bonded. The interposer 800 has a thermoelectric conversion element as described above, and moves the heat generated in the semiconductor chip 140 to the circuit board 110. The heat transferred to the circuit board 110 is efficiently diffused and radiated by the metal core board 820.

  The electronic device 100 ″ shown in FIG. 14B is an example of an ultra-high-density mounting with a multi-chip configuration applied to a supercomputer, a high-end server, etc. For example, on an ultra-multilayer ceramic circuit board 110 ″ having several tens of layers. In addition, a plurality of LSI chips 140 are mounted via respective interposers 800. The ceramic circuit board 110 ″ may have a decoupling capacitor 116 such as MCC. A heat sink 810 is thermally bonded to the back side of each LSI chip 140. Further, on the back side of the circuit board 110, Preferably, a plurality of heat sinks 830 are joined. Each interposer 800 has a thermoelectric conversion element as described above, and moves the heat generated in each LSI chip 140 to the ceramic circuit board 110 ″. The heat transferred to the ceramic circuit board 110 ″ is efficiently diffused due to the high thermal conductivity of the board and further dissipated by the heat sink 830.

  Further, when the interposer 800 is an interposer such as an interposer 500, 600, 700 or the like that incorporates a thin film decoupling capacitor 510, the electronic devices 100 ′, 100 ″ have a sufficiently low power supply that does not hinder their operation even in a high frequency region. The semiconductor chip 140 having an impedance can be stably operated even during a large current operation.

  Although the embodiment has been described in detail above, the present invention is not limited to the specific embodiment, and various modifications and changes can be made within the scope of the gist described in the claims. For example, the interposer substrate may have an intermediate conductive layer therein, and the pads on the first surface and the pads on the second surface may be formed at different pitches using the intermediate conductive layer. .

Regarding the above description, the following additional notes are disclosed.
(Appendix 1)
A substrate having a first surface on which a semiconductor chip is mounted, and a second surface opposite to the first surface;
A plurality of vias including a first via and a second via penetrating the substrate;
Have
A first current path including the first via that becomes a power path when the semiconductor chip is mounted has at least one N-type thermoelectric conversion layer, and a ground path when the semiconductor chip is mounted. The interposer, wherein the second current path including the second via has at least one P-type thermoelectric conversion layer.
(Appendix 2)
The first current path includes a first pad formed on the first surface of the substrate, and the second current path is a first pad formed on the first surface of the substrate. The interposer according to appendix 1, wherein the interposer includes two pads, the N-type thermoelectric conversion layer is formed in the first pad, and the P-type thermoelectric conversion layer is formed in the second pad.
(Appendix 3)
The interposer according to appendix 1 or 2, wherein the N-type thermoelectric conversion layer is formed in the first via and the P-type thermoelectric conversion layer is formed in the second via.
(Appendix 4)
The first current path includes a third pad formed on the second surface of the substrate, and the second current path is formed on the second surface of the substrate. Any one of appendixes 1 to 3, wherein the N-type thermoelectric conversion layer is formed in the third pad, and the P-type thermoelectric conversion layer is formed in the fourth pad. The interposer described in.
(Appendix 5)
The N-type thermoelectric conversion layer and the P-type thermoelectric conversion layer are selected from the group consisting of heavy metal-based, semiconductor-based, CaCo-based, CaMn-based, ZnO-based, oxide-based, silicide-based, clastrate-based, and skutterudite-based. The interposer according to any one of appendices 1 to 4, comprising the selected thermoelectric conversion material.
(Appendix 6)
The N-type thermoelectric conversion layer and the P-type thermoelectric conversion layer has a thermoelectric conversion material of BiTe-based or FeSi ₂ based, interposer according to Appendix 5.
(Appendix 7)
A thin film capacitor in which a first electrode electrically connected to the first current path, a dielectric layer, and a second electrode electrically connected to the second current path are stacked on the substrate; The interposer according to any one of appendices 1 to 6, further comprising:
(Appendix 8)
The interposer according to any one of appendices 1 to 7, wherein the plurality of vias include a plurality of pairs of the first via and the second via.
(Appendix 9)
The plurality of vias further include a third via, and the third current path including the third via that becomes a signal path when the semiconductor chip is mounted does not include a thermoelectric conversion layer. The interposer according to any one of 8.
(Appendix 10)
A semiconductor chip;
An interposer having a substrate on which the semiconductor chip is mounted and a plurality of vias penetrating the substrate;
Have
The semiconductor chip has a power pad and a ground pad,
The plurality of vias of the interposer includes a power supply via electrically connected to the power supply pad of the semiconductor chip and a ground via electrically connected to the ground pad of the semiconductor chip,
The power path of the interposer including the power via has at least one N-type thermoelectric conversion layer, and the ground path of the interposer including the ground via has at least one P-type thermoelectric conversion layer.
Semiconductor device.
(Appendix 11)
A semiconductor chip;
A circuit board;
An interposer that is disposed between the semiconductor chip and the circuit board and has a substrate and a plurality of vias penetrating the substrate;
Have
The semiconductor chip has a power pad and a ground pad,
The circuit board has power supply wiring and ground wiring,
The plurality of vias of the interposer includes a power supply via electrically connected to the power supply pad and the power supply wiring, and a ground via electrically connected to the ground pad and the ground wiring,
The power path of the interposer including the power via has at least one N-type thermoelectric conversion layer, and the ground path of the interposer including the ground via has at least one P-type thermoelectric conversion layer.
Electronic equipment.
(Appendix 12)
The electronic device according to appendix 11, wherein a heat radiating plate or a heat sink is bonded to a surface of the circuit board opposite to a surface on which the interposer is disposed.

100, 100 ', 100 "electronic device 110, 110" circuit board 111 surface of circuit board 116 decoupling capacitor 120 semiconductor device 130, 820 heat sink 140 semiconductor chip 141 surface of semiconductor chip 150, 160 connection bump 114, 144 pad ( Conductive layer)
180, 190 Heat flow 200, 300, 400, 500, 600, 700 Interposer 210 Interposer substrate 211 First surface of interposer substrate 212 Second surface of interposer substrate 214V, 414V, 714V Power supply pad 214G, 414G on first surface , 714G First surface ground pad 214S, 414S, 714S First surface signal pad 215V, 315V, 615V Second surface power pad 215G, 315G, 615G Second surface ground pad 215S, 315S, 615S Second surface signal pad 216, 218, 219, 316, 318, 319, 616, 618, 619 Conductive layer 217N, 317N N-type thermoelectric conversion layer 217P, 317P P-type thermoelectric conversion layer 220V, 420V, 720V Power supply via 22 G, 420G, 720G ground vias 220S, 420S, 720S signal via 230 insulating film 510 thin film capacitor 511 lower electrode 512 dielectric layer 513 upper electrode 520 insulating layer 530V, 530G Contacts

Claims (7)

A substrate having a first surface on which a semiconductor chip is mounted, and a second surface opposite to the first surface;
A plurality of vias including a first via and a second via penetrating the substrate;
Have
A first current path including the first via that becomes a power path when the semiconductor chip is mounted has at least one N-type thermoelectric conversion layer, and a ground path when the semiconductor chip is mounted. The interposer, wherein the second current path including the second via has at least one P-type thermoelectric conversion layer.   The first current path includes a first pad formed on the first surface of the substrate, and the second current path is a first pad formed on the first surface of the substrate. 2. The interposer according to claim 1, comprising two pads, wherein the N-type thermoelectric conversion layer is formed in the first pad, and the P-type thermoelectric conversion layer is formed in the second pad.   The interposer according to claim 1 or 2, wherein the N-type thermoelectric conversion layer is formed in the first via and the P-type thermoelectric conversion layer is formed in the second via. The N-type thermoelectric conversion layer and the P-type thermoelectric conversion layer has a thermoelectric conversion material of BiTe-based or FeSi ₂ based, interposer according to any one of claims 1 to 3.   A thin film capacitor in which a first electrode electrically connected to the first current path, a dielectric layer, and a second electrode electrically connected to the second current path are stacked on the substrate; The interposer according to any one of claims 1 to 4, further comprising: A semiconductor chip;
An interposer having a substrate on which the semiconductor chip is mounted and a plurality of vias penetrating the substrate;
Have
The semiconductor chip has a power pad and a ground pad,
The plurality of vias of the interposer includes a power supply via electrically connected to the power supply pad of the semiconductor chip and a ground via electrically connected to the ground pad of the semiconductor chip,
The power path of the interposer including the power via has at least one N-type thermoelectric conversion layer, and the ground path of the interposer including the ground via has at least one P-type thermoelectric conversion layer.
Semiconductor device. A semiconductor chip;
A circuit board;
An interposer that is disposed between the semiconductor chip and the circuit board and has a substrate and a plurality of vias penetrating the substrate;
Have
The semiconductor chip has a power pad and a ground pad,
The circuit board has power supply wiring and ground wiring,
The plurality of vias of the interposer includes a power supply via electrically connected to the power supply pad and the power supply wiring, and a ground via electrically connected to the ground pad and the ground wiring,
The power path of the interposer including the power via has at least one N-type thermoelectric conversion layer, and the ground path of the interposer including the ground via has at least one P-type thermoelectric conversion layer.
Electronic equipment.

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