TW201919162A - Package structure - Google Patents

Package structure Download PDF

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Publication number
TW201919162A
TW201919162A TW107137456A TW107137456A TW201919162A TW 201919162 A TW201919162 A TW 201919162A TW 107137456 A TW107137456 A TW 107137456A TW 107137456 A TW107137456 A TW 107137456A TW 201919162 A TW201919162 A TW 201919162A
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Taiwan
Prior art keywords
insulating layer
layer
packaging structure
insulating
item
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TW107137456A
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Chinese (zh)
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TWI791648B (en
Inventor
吳銘洪
吳基福
曾安平
吳晧宇
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台灣東電化股份有限公司
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Publication of TW201919162A publication Critical patent/TW201919162A/en
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Publication of TWI791648B publication Critical patent/TWI791648B/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Abstract

A package structure is provided, including a first insulating layer, a second insulating layer, a third insulating layer, and a chip. The second insulating layer is disposed on the first insulating layer, the chip is disposed in the second insulating layer, and the third insulating layer is disposed on the second insulating layer. The heat transfer coefficient of the second insulating layer is less than the heat transfer coefficient of the first insulating layer, and the hardness of the second insulating layer is less than the hardness of the first insulating layer.

Description

封裝結構Package structure

本發明係關於一種封裝結構,且特別關於一種增強導熱功能的封裝結構。The present invention relates to a packaging structure, and particularly to a packaging structure that enhances heat conduction function.

積體電路(integrated circuit,IC)工業已經歷了指數增長。積體電路材料及設計的技術改進已產生了數個世代的積體電路,每一世代的積體電路都具有比上一世代更小及更複雜的電路,並且已應用於日常生活中的各種裝置中(例如手機、變壓器、電池、汽車等)。為了進一步增加積體電路裝置的效能,業界致力於尋求各種可提高生產效率和降低相關成本的微縮化方法。舉例來說,在行動電話中,由於基板佔據了一定的空間,從而造成其他元件(如電池)的空間受限。若可降低基板所佔據的空間,則這些額外的空間可被靈活地運用,以滿足使用者的需求。The integrated circuit (IC) industry has experienced exponential growth. The improvement of integrated circuit materials and design technology has produced several generations of integrated circuits. Each generation of integrated circuits has smaller and more complex circuits than the previous generation, and has been used in various kinds of daily life. In the device (such as mobile phones, transformers, batteries, cars, etc.). In order to further increase the efficiency of integrated circuit devices, the industry is committed to seeking various miniaturization methods that can increase production efficiency and reduce related costs. For example, in a mobile phone, since the substrate occupies a certain space, the space of other components (such as a battery) is limited. If the space occupied by the substrate can be reduced, these additional spaces can be flexibly used to meet the needs of users.

在降低基板的大小時使用了各種封裝結構,而對需要較大電流的裝置中的封裝結構來說,較大的電流會產生較多的熱量,若熱量累積在上述裝置中,則可能會造成效率下降或損壞裝置。因此,如何讓上述封裝結構達成進一步散熱始成為一重要之課題。Various package structures are used to reduce the size of the substrate. For a package structure in a device that requires a large current, a large current will generate more heat. If the heat is accumulated in the above device, it may cause Reduced efficiency or damage to the device. Therefore, how to achieve the further heat dissipation of the package structure has become an important issue.

本發明提供一種封裝結構,包括:第一絕緣層、第二絕緣層、第三絕緣層、及晶片。上述第二絕緣層設置在第一絕緣層上,上述晶片設置在第二絕緣層中,上述第三絕緣層設置在第二絕緣層上。其中第二絕緣層之導熱係數小於第一絕緣層之導熱係數,且第二絕緣層之硬度小於第一絕緣層之硬度。The invention provides a packaging structure, including: a first insulating layer, a second insulating layer, a third insulating layer, and a chip. The second insulating layer is provided on the first insulating layer, the wafer is provided in the second insulating layer, and the third insulating layer is provided on the second insulating layer. The thermal conductivity of the second insulating layer is less than the thermal conductivity of the first insulating layer, and the hardness of the second insulating layer is less than the hardness of the first insulating layer.

如本發明一些實施例所述之封裝結構,其中第一絕緣層之材料包括陶瓷材料,且第二絕緣層之材料包括樹脂材料。第二絕緣層之材料不包括玻璃纖維。第二絕緣層之導熱係數小於第三絕緣層之導熱係數,且第二絕緣層之硬度小於第三絕緣層之硬度。第三絕緣層之材料包括陶瓷材料。The packaging structure as described in some embodiments of the present invention, wherein the material of the first insulating layer includes a ceramic material, and the material of the second insulating layer includes a resin material. The material of the second insulating layer does not include glass fiber. The thermal conductivity of the second insulating layer is less than the thermal conductivity of the third insulating layer, and the hardness of the second insulating layer is less than the hardness of the third insulating layer. The material of the third insulating layer includes ceramic material.

如本發明一些實施例所述之封裝結構,其中第三絕緣層包括金屬層及絕緣薄膜,上述絕緣薄膜係設置在金屬層上。上述封裝結構更包括彈性層、電子元件,設置在第一絕緣層上。第一絕緣層之導熱係數小於第三絕緣層之導熱係數,且第一絕緣層之硬度小於第三絕緣層之硬度。第一絕緣層中之陶瓷材料之厚度大於第一絕緣層之厚度的50%。其中第二絕緣層之厚度大於該第一絕緣層之厚度及大於第三絕緣層之厚度,第三絕緣層之厚度大於第一絕緣層之厚度。According to the packaging structure described in some embodiments of the present invention, the third insulating layer includes a metal layer and an insulating film, and the insulating film is disposed on the metal layer. The above packaging structure further includes an elastic layer and electronic components, which are disposed on the first insulating layer. The thermal conductivity of the first insulating layer is less than the thermal conductivity of the third insulating layer, and the hardness of the first insulating layer is less than the hardness of the third insulating layer. The thickness of the ceramic material in the first insulating layer is greater than 50% of the thickness of the first insulating layer. The thickness of the second insulating layer is greater than the thickness of the first insulating layer and the thickness of the third insulating layer, and the thickness of the third insulating layer is greater than the thickness of the first insulating layer.

如本發明一些實施例所述之封裝結構,其中第一絕緣層之材料包括金屬層及第一絕緣薄膜,第二絕緣層之材料包括樹脂材料,且第一絕緣薄膜係設置在金屬層上,第三絕緣層之材料包括陶瓷材料。其中第三絕緣層包括金屬層及第二絕緣薄膜,上述金屬層包括導電部及絕緣部,且導電部與絕緣部電性隔離。從平行第一絕緣層及第二絕緣層間界面的方向觀察,第一絕緣層與第二絕緣層不重疊,且第二絕緣層與第三絕緣層不重疊。封裝結構更包括第一導線層、第二導線層、及導孔,其中第一導線層係設置在第一絕緣層及第二絕緣層間,第二導線層係設置在第二絕緣層及第三絕緣層間,且導孔電性連接晶片、第一導線層、及第二導線層。According to the packaging structure of some embodiments of the present invention, the material of the first insulating layer includes a metal layer and a first insulating film, the material of the second insulating layer includes a resin material, and the first insulating film is disposed on the metal layer, The material of the third insulating layer includes ceramic material. The third insulating layer includes a metal layer and a second insulating film. The metal layer includes a conductive portion and an insulating portion, and the conductive portion is electrically isolated from the insulating portion. Viewed from the direction parallel to the interface between the first insulating layer and the second insulating layer, the first insulating layer and the second insulating layer do not overlap, and the second insulating layer and the third insulating layer do not overlap. The packaging structure further includes a first wire layer, a second wire layer, and a via hole, wherein the first wire layer is disposed between the first insulating layer and the second insulating layer, and the second wire layer is disposed between the second insulating layer and the third Between the insulating layers, the via holes are electrically connected to the chip, the first wire layer, and the second wire layer.

以下公開許多不同的實施方法或是範例來實行所提供之標的之不同特徵,以下描述具體的元件及其排列的實施例以闡述本發明。當然這些實施例僅用以例示,且不該以此限定本發明的範圍。Many different implementation methods or examples are disclosed below to implement the different features of the provided subject matter. The following describes specific elements and their arrangement of embodiments to illustrate the present invention. Of course, these embodiments are for illustration only, and should not be used to limit the scope of the present invention.

此外,在不同實施例中可能使用重複的標號或標示,這些重複僅為了簡單清楚地敘述本發明,不代表所討論的不同實施例及/或結構之間有特定的關係。此外,在本發明中的在另一特徵部件之上形成、連接到及/或耦接到另一特徵部件可包括其中特徵部件形成為直接接觸的實施例,並且還可包括其中可形成插入上述特徵部件的附加特徵部件的實施例,使得上述特徵部件可能不直接接觸。此外,其中可能用到與空間相關用詞,例如“在…下方”、“下方”、“水平的”、“垂直的”、“上方”、“較高的”、"下方"、"較低的"、"上"、"下"、"頂"、"底"及類似的用詞(如"水平地"、"向下地"、"向上地"等),這些空間相關用詞係為了便於描述圖示中一個(些)元件或特徵與另一個(些)元件或特徵之間的關係,這些空間相關用詞旨在涵蓋包括特徵的裝置的不同方向。In addition, repeated reference numerals or marks may be used in different embodiments. These repetitions are merely a simple and clear description of the present invention and do not represent a specific relationship between the different embodiments and / or structures discussed. In addition, forming, connecting to, and / or coupling to another feature in the present invention may include an embodiment in which the feature is formed in direct contact, and may also include in which the above-described insert may be formed Embodiments of additional feature parts of the feature parts such that the above feature parts may not be in direct contact. In addition, space-related terms may be used, such as "below", "below", "horizontal", "vertical", "above", "higher", "below", "lower" "," Up "," down "," top "," bottom "and similar terms (such as" horizontally "," downwardly "," upwardly ", etc.), these spatially related terms are for convenience Describe the relationship between one element (s) or feature and another element (s) in the illustration. These spatially related terms are intended to cover different directions of the device that includes the feature.

請參閱第1A圖,其繪示一實施例的封裝結構1a。上述封裝結構1a主要包括第一絕緣層10r、第二絕緣層20、第三絕緣層30r、晶片40、以及用以將晶片40與外部其他元件電性連接的內連線結構。上述第一絕緣層10r係設置在第二絕緣層20上,第二絕緣層20係設置在第三絕緣層30r上,且晶片40係設置在第二絕緣層20中。Please refer to FIG. 1A, which illustrates a package structure 1a according to an embodiment. The package structure 1a mainly includes a first insulating layer 10r, a second insulating layer 20, a third insulating layer 30r, a chip 40, and an interconnect structure for electrically connecting the chip 40 with other external components. The first insulating layer 10r is provided on the second insulating layer 20, the second insulating layer 20 is provided on the third insulating layer 30r, and the wafer 40 is provided in the second insulating layer 20.

上述內連線結構包括設置在第一絕緣層10r上的導線層50、設置在第一絕緣層10r及第二絕緣層20間的導線層51、設置在第二絕緣層20及第三絕緣層30r間的導線層52、設置在第三絕緣層30r上的導線層53、設置在第一絕緣層10r中的導孔60、設置在第二絕緣層20中的導孔61、62、及設置在第三絕緣層30r中的導孔63。在晶片40及導孔61之間還設置有導電墊70。鈍化層80及鈍化層81分別設置在第一絕緣層10r及第三絕緣層30r朝向封裝結構1a外部的表面上,並且分別覆蓋部分導線層50及導線層53。The above interconnect structure includes a wire layer 50 disposed on the first insulating layer 10r, a wire layer 51 disposed between the first insulating layer 10r and the second insulating layer 20, a second insulating layer 20 and a third insulating layer The lead layer 52 between 30r, the lead layer 53 provided on the third insulating layer 30r, the via hole 60 provided in the first insulating layer 10r, the via holes 61, 62 provided in the second insulating layer 20, and the arrangement The via hole 63 in the third insulating layer 30r. A conductive pad 70 is also provided between the wafer 40 and the via 61. The passivation layer 80 and the passivation layer 81 are respectively disposed on the surfaces of the first insulating layer 10r and the third insulating layer 30r facing the outside of the packaging structure 1a, and cover part of the wire layer 50 and the wire layer 53 respectively.

此外,可在形成第二絕緣層20後,使用合適的壓合製程(例如熱壓製程),使第一絕緣層10r及第三絕緣層30r與第二絕緣層20結合,進而形成上述封裝結構1a。In addition, after the second insulating layer 20 is formed, a suitable pressing process (such as a hot pressing process) may be used to combine the first insulating layer 10r and the third insulating layer 30r with the second insulating layer 20 to form the above-mentioned package structure 1a.

在上述內連線結構中,導孔60電性連接導線層50、51,導孔61電性連接導線層52,且通過導電墊70電性連接晶片40,導孔62電性連接導線層51、52,導孔63電性連接導線層52、53。應理解的是,上述繪示的導線層50、51、52、53及導孔60、61、62、63的位置僅是示例性的,其實際配置可以根據設計及製造需求而變化。雖然上述導孔60、61、62、63係繪示成梯形,但本發明並不以此為限。舉例來說,亦可使用合適的製程(例如鑽孔製程),使得導孔具有筆直的側壁。此外,雖然在第1A圖中,在導線層及導孔之間繪示一界面,但其僅為示例,亦可藉由合適的製程使導線層及導孔間不具有明顯的界面。導線層50、51、52、53可藉由例如雷射打線的方式所形成。In the above interconnect structure, the via hole 60 is electrically connected to the lead layers 50 and 51, the via hole 61 is electrically connected to the lead layer 52, and the chip 40 is electrically connected to the via pad 70, and the via hole 62 is electrically connected to the lead layer 51 , 52, the via 63 is electrically connected to the lead layers 52, 53. It should be understood that the positions of the wire layers 50, 51, 52, and 53 and the guide holes 60, 61, 62, and 63 shown above are only exemplary, and their actual configurations may vary according to design and manufacturing requirements. Although the guide holes 60, 61, 62, and 63 are depicted as trapezoids, the present invention is not limited thereto. For example, a suitable process (such as a drilling process) can also be used so that the via hole has straight side walls. In addition, although an interface is shown between the wire layer and the via hole in FIG. 1A, it is only an example, and there can be no obvious interface between the wire layer and the via hole by a suitable process. The wire layers 50, 51, 52, and 53 can be formed by, for example, laser bonding.

上述導線層50、51、52、53及導孔60、61、62、63可包括合適的導電材料,例如鎢、鋁、鈷或銅等合適的導電材料。本領域通常技術人士將理解用於導線層50、51、52、53及導孔60、61、62、63的其它導電材料係在本實施例的範圍及精神內。The wire layers 50, 51, 52, and 53 and the via holes 60, 61, 62, and 63 may include suitable conductive materials, such as tungsten, aluminum, cobalt, or copper. Those of ordinary skill in the art will understand that other conductive materials for the wire layers 50, 51, 52, 53 and the vias 60, 61, 62, 63 are within the scope and spirit of this embodiment.

鈍化層80、81用以保護封裝結構1a中的各種元件,且在鈍化層80、81上具有多個開口,以分別露出部分的導線層50、53,藉以與外部電路連接。於一些實施例中,鈍化層80、81係由氧化矽、氮化矽、氮氧化矽或其組合所形成。於一些實施例中,鈍化層80、81係由高分子所形成。於一些實施例中,鈍化層80、81係由化學氣相沉積製程、旋轉塗佈製程、濺鍍製程或其組合所形成。The passivation layers 80 and 81 are used to protect various components in the packaging structure 1a, and the passivation layers 80 and 81 have a plurality of openings to expose portions of the wire layers 50 and 53 to connect with external circuits. In some embodiments, the passivation layers 80 and 81 are formed of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In some embodiments, the passivation layers 80 and 81 are formed of polymers. In some embodiments, the passivation layers 80 and 81 are formed by a chemical vapor deposition process, a spin coating process, a sputtering process, or a combination thereof.

上述第一絕緣層10r及第三絕緣層30r的材料可為相同或相似的樹脂材料,例如FR-4或BT(Bismaleimide Triazine,雙馬來醯亞胺-三氮雜苯)等樹脂材料。第二絕緣層20的材料可與第一絕緣層10r及第三絕緣層30r不同,例如為其他導熱係數較第一絕緣層10r及第三絕緣層30r高之樹脂材料。此外,第二絕緣層20不需使用玻璃纖維,進而可降低製造成本並簡化製程。然而,在第一絕緣層10r及第三絕緣層30r皆使用導熱係數較低的樹脂材料(例如<2W/mK)所形成的條件下,封裝結構1a中的元件(如晶片40或其他周邊元件)在運作時所產生的熱較難被有效地導出封裝結構1a,因此會造成整體結構溫度升高,連帶使得效能受到限制。The materials of the first insulating layer 10r and the third insulating layer 30r may be the same or similar resin materials, such as FR-4 or BT (Bismaleimide Triazine, bismaleimide-triazine) and other resin materials. The material of the second insulating layer 20 may be different from the first insulating layer 10r and the third insulating layer 30r, for example, other resin materials having higher thermal conductivity than the first insulating layer 10r and the third insulating layer 30r. In addition, the second insulating layer 20 does not need to use glass fiber, which can reduce the manufacturing cost and simplify the manufacturing process. However, under the condition that both the first insulating layer 10r and the third insulating layer 30r are formed of a resin material with a low thermal conductivity (for example, <2W / mK), the components (such as the chip 40 or other peripheral components) in the package structure 1a ) The heat generated during operation is more difficult to be effectively led out of the package structure 1a, so it will cause the overall structure temperature to increase, which in turn will limit the performance.

請參閱第1B圖,其繪示本發明一實施例的封裝結構1b。封裝結構1b與上述封裝結構1a類似,差異在封裝結構1b的第一絕緣層10c與封裝結構1a的第一絕緣層10r不同,其餘相同或相似的部件細節於此不再贅述。Please refer to FIG. 1B, which illustrates a package structure 1b according to an embodiment of the present invention. The packaging structure 1b is similar to the packaging structure 1a described above. The difference is that the first insulating layer 10c of the packaging structure 1b is different from the first insulating layer 10r of the packaging structure 1a. The details of the same or similar components are not repeated here.

在本實施例中,第一絕緣層10c係使用導熱係數比第一絕緣層10r高的陶瓷材料所形成,例如氧化鋁或氮化鋁等合適的陶瓷材料。第一絕緣層10c的導熱係數例如大於20W/mK。藉由這種配置方式,可使封裝結構1b中的晶片40所產生的熱以較快的速率傳導到外部,進而提升整體的效能。此外,還可藉此控制散熱方向。再者,相較於樹脂製的第一絕緣層10r,由於陶瓷製的第一絕緣層10c較不易變形且硬度較高,因此可使得封裝結構1b較不易發生翹曲的問題,進而增加連接的可靠度。此外,在第一絕緣層10c與樹脂材料製成的第二絕緣層20接合後,由於第一絕緣層10c的表面較粗糙,可提升與第二絕緣層20的接合強度。In this embodiment, the first insulating layer 10c is formed using a ceramic material having a higher thermal conductivity than the first insulating layer 10r, such as a suitable ceramic material such as alumina or aluminum nitride. The thermal conductivity of the first insulating layer 10c is greater than 20 W / mK, for example. With this arrangement, the heat generated by the chip 40 in the packaging structure 1b can be conducted to the outside at a faster rate, thereby improving the overall performance. In addition, the direction of heat dissipation can also be controlled. Furthermore, compared to the first insulating layer 10r made of resin, the first insulating layer 10c made of ceramic is less likely to deform and has a higher hardness, so that the package structure 1b is less likely to warp, thereby increasing the connection Reliability. In addition, after the first insulating layer 10c is bonded to the second insulating layer 20 made of resin material, since the surface of the first insulating layer 10c is rough, the bonding strength with the second insulating layer 20 can be improved.

應注意的是,上述第一絕緣層10c中之陶瓷材料之厚度係大於第一絕緣層10c總厚度的50%。藉此可確保第一絕緣層中具有足夠的陶瓷材料,以達成前述優點。此外,沿著第1B圖中的X方向觀察(平行第一絕緣層10c及第二絕緣層20間界面的方向)觀察,封裝結構1b的第一絕緣層10c與第二絕緣層20不重疊,且第二絕緣層20與第三絕緣層30r不重疊。藉由這種配置方式,可簡化封裝結構1b的生產製程並且降低成本。再者,沿著第1B圖中的Z方向觀察(垂直第一絕緣層10c及第二絕緣層20間界面的方向),第一絕緣層10c、第三絕緣層30r會與晶片40至少部分重疊,因此可進一步提升在Z方向上的導熱效果。It should be noted that the thickness of the ceramic material in the first insulating layer 10c is greater than 50% of the total thickness of the first insulating layer 10c. In this way, sufficient ceramic material can be ensured in the first insulating layer to achieve the aforementioned advantages. In addition, when viewed in the X direction in FIG. 1B (parallel to the interface between the first insulating layer 10c and the second insulating layer 20), the first insulating layer 10c and the second insulating layer 20 of the package structure 1b do not overlap, Moreover, the second insulating layer 20 and the third insulating layer 30r do not overlap. With this configuration, the manufacturing process of the packaging structure 1b can be simplified and the cost can be reduced. Furthermore, when viewed in the Z direction in FIG. 1B (the direction perpendicular to the interface between the first insulating layer 10c and the second insulating layer 20), the first insulating layer 10c and the third insulating layer 30r at least partially overlap the wafer 40 Therefore, the heat conduction effect in the Z direction can be further improved.

此外,上述第一絕緣層10c與第二絕緣層20係在不同的步驟中分別形成,之後再用合適的製程結合(例如熱壓製程),以防止在形成第一絕緣層10c的製程中損壞第二絕緣層20及第二絕緣層20中的晶片40。In addition, the first insulating layer 10c and the second insulating layer 20 are separately formed in different steps, and then combined with a suitable process (such as a hot pressing process) to prevent damage in the process of forming the first insulating layer 10c The second insulating layer 20 and the wafer 40 in the second insulating layer 20.

請參閱第1C圖,其繪示本發明另一實施例的封裝結構1c。封裝結構1c與上述封裝結構1a類似,差異在封裝結構1c的第一絕緣層10c及第三絕緣層30c與封裝結構1a的第一絕緣層10r、第三絕緣層30r不同,其餘相同或相似的部件細節於此不再贅述。在本實施例中,第一絕緣層10c及第三絕緣層30c係使用導熱係數比第一絕緣層10r及第三絕緣層30r高的陶瓷材料所形成,例如氧化鋁或氮化鋁等合適的陶瓷材料。因此,可進一步地將晶片40所散發之熱量向外導出,避免過熱的問題,使整體效能提升。此外,還可藉此控制散熱方向。再者,相較於樹脂製的第一絕緣層10r及第三絕緣層30r,由於陶瓷製的第一絕緣層10c及第三絕緣層30c較不易變形且硬度較高,因此可使得封裝結構1c較不易發生翹曲的問題,進而增加連接的可靠度。此外,在第一絕緣層10c及第三絕緣層30c與樹脂材料製成的第二絕緣層20接合後,由於第一絕緣層10c及第三絕緣層30c的表面較粗糙,可提升與第二絕緣層20的接合強度。Please refer to FIG. 1C, which illustrates a package structure 1c according to another embodiment of the present invention. The packaging structure 1c is similar to the packaging structure 1a described above, except that the first insulating layer 10c and the third insulating layer 30c of the packaging structure 1c are different from the first insulating layer 10r and the third insulating layer 30r of the packaging structure 1a, and the rest are the same or similar The details of the components are not repeated here. In this embodiment, the first insulating layer 10c and the third insulating layer 30c are formed using a ceramic material having a higher thermal conductivity than the first insulating layer 10r and the third insulating layer 30r, such as aluminum oxide or aluminum nitride. Ceramic material. Therefore, the heat dissipated by the wafer 40 can be further led out to avoid the problem of overheating and improve the overall performance. In addition, the direction of heat dissipation can also be controlled. Furthermore, compared to the first insulating layer 10r and the third insulating layer 30r made of resin, the first insulating layer 10c and the third insulating layer 30c made of ceramic are less likely to deform and have a higher hardness, so the package structure 1c can be made The problem of warpage is less likely to occur, thereby increasing the reliability of the connection. In addition, after the first insulating layer 10c and the third insulating layer 30c are joined to the second insulating layer 20 made of resin material, since the surfaces of the first insulating layer 10c and the third insulating layer 30c are rough, the The bonding strength of the insulating layer 20.

請參閱第1D圖,其繪示本發明另一實施例的封裝結構1d。封裝結構1d與前述封裝結構1b之結構類似,差別是在第一絕緣層10c及第三絕緣層30r上進一步設置了彈性層E ,而其餘相同或相似的部件細節於此不再贅述。彈性層E的材料例如為樹脂等彈性材料,此外不含玻璃纖維,並且彈性層E可與第一絕緣層10c黏合。藉此,即使第一絕緣層10c遭受外力衝擊而碎裂,彈性層E可緊黏碎裂的第一絕緣層10c,以防止碎片散落而造成裝置損壞。Please refer to FIG. 1D, which illustrates a package structure 1d according to another embodiment of the present invention. The packaging structure 1d is similar to the foregoing packaging structure 1b, the difference is that an elastic layer E is further provided on the first insulating layer 10c and the third insulating layer 30r, and the details of the same or similar components will not be repeated here. The material of the elastic layer E is, for example, an elastic material such as resin. In addition, it does not contain glass fibers, and the elastic layer E can be bonded to the first insulating layer 10c. In this way, even if the first insulating layer 10c is cracked by an external force, the elastic layer E can tightly adhere the cracked first insulating layer 10c to prevent the debris from scattering and causing damage to the device.

請參閱第1E圖,其繪示本發明另一實施例的封裝結構1e。封裝結構1e與前述封裝結構1a之結構類似,差別在於封裝結構1e的第一絕緣層係從第一絕緣層10r替換為上下兩面具有絕緣薄膜F,並由金屬材料所形成(例如鋁或銅)的第一絕緣層10m,其餘相同或相似的部件細節於此不再贅述。絕緣薄膜F係例如可藉由陽極處理或其他方法所形成,以防止第一絕緣層10m中的金屬材料與其他導電結構(例如前述內連線結構)接觸處發生短路。Please refer to FIG. 1E, which illustrates a package structure 1e according to another embodiment of the present invention. The packaging structure 1e is similar to the foregoing packaging structure 1a, except that the first insulating layer of the packaging structure 1e is replaced from the first insulating layer 10r with an insulating film F on the upper and lower sides, and is formed of a metal material (such as aluminum or copper) The first insulating layer of 10m, the details of the remaining same or similar components will not be repeated here. The insulating film F can be formed by, for example, anodizing or other methods to prevent short circuit between the metallic material in the first insulating layer 10m and other conductive structures (such as the aforementioned interconnect structure).

由於第一絕緣層10m是使用導熱係數比前述第一絕緣層10c高的材料所形成,從而可進一步地將封裝結構1e中各元件運作時所產生的熱量導出,以達成防止過熱、控制散熱方向以及提升效率的優點。此外,由於金屬材料製成的第一絕緣層10m相較於樹脂具有良好之延展性,並且第一絕緣層10m的硬度比第二絕緣層20高,因此設置第一絕緣層10m亦可提升對應接觸的其他部分遭受撞擊時的耐衝擊力。再者,上述第一絕緣層10m的厚度可設置為小於0.1μm,因此可使封裝結構1e進一步小型化。Since the first insulating layer 10m is formed of a material with a higher thermal conductivity than the first insulating layer 10c, the heat generated during the operation of the components in the package structure 1e can be further extracted to prevent overheating and control the direction of heat dissipation And the advantages of improving efficiency. In addition, since the first insulating layer 10m made of a metal material has better ductility than resin, and the hardness of the first insulating layer 10m is higher than that of the second insulating layer 20, the provision of the first insulating layer 10m can also improve the correspondence The impact resistance of other parts in contact with the impact. Furthermore, the thickness of the first insulating layer 10m can be set to be less than 0.1 μm, so the package structure 1e can be further miniaturized.

由於第一絕緣層10m係以具有絕緣薄膜F的金屬所製成,因此需要特殊的結構來允許電性上下導通。請參閱第1F圖,其係第1E圖中區域R的放大圖。金屬製的第一絕緣層10m具有導電部11及絕緣部12,且導電部11及絕緣部12間以隔絕部H分隔。在本實施例中,在兩個隔絕部H間並未設置絕緣薄膜F,導電部11直接且電性連接排列在導電部11上方的導線層51及排列在導電部31下方的導線層50,而絕緣部12未直接連接導電部11正上方導線層51及排列在導電部31正下方的導線層50。在隔絕部H中,可不設置任何元件(即以空氣填充),或者是設置合適的絕緣材料,以防止導電部11及絕緣部12間發生干擾或短路。亦即,導電部11於局部電性獨立。此外,可使用不同的材料形成導電部11及導線層51,以利於加工並且提升導電性。Since the first insulating layer 10m is made of metal with an insulating film F, a special structure is required to allow electrical conduction up and down. Please refer to Figure 1F, which is an enlarged view of area R in Figure 1E. The first insulating layer 10m made of metal has a conductive portion 11 and an insulating portion 12, and the conductive portion 11 and the insulating portion 12 are separated by an insulating portion H. In this embodiment, the insulating film F is not provided between the two isolation portions H, and the conductive portion 11 is directly and electrically connected to the wire layer 51 arranged above the conductive portion 11 and the wire layer 50 arranged under the conductive portion 31 The insulating portion 12 does not directly connect the wire layer 51 directly above the conductive portion 11 and the wire layer 50 arranged directly below the conductive portion 31. In the insulating portion H, no element (ie, filled with air) may be provided, or a suitable insulating material may be provided to prevent interference or short circuit between the conductive portion 11 and the insulating portion 12. That is, the conductive portion 11 is electrically independent locally. In addition, different materials may be used to form the conductive portion 11 and the wire layer 51 to facilitate processing and improve conductivity.

請參閱第1G圖,其繪示本發明另一實施例的封裝結構1f。封裝結構1f與前述封裝結構1a之結構類似,差別在於封裝結構1f的第一絕緣層10m及第三絕緣層30m係由金屬材料所形成(例如鋁或銅)。Please refer to FIG. 1G, which illustrates a package structure 1f according to another embodiment of the present invention. The packaging structure 1f is similar to the foregoing packaging structure 1a, except that the first insulating layer 10m and the third insulating layer 30m of the packaging structure 1f are formed of metal materials (such as aluminum or copper).

在第一絕緣層10m及第三絕緣層30m上皆具有絕緣薄膜(未繪示),以防止其中的金屬材料與其他導電結構(例如前述內連線結構)接觸處發生短路。可分別在第一絕緣層10m及第三絕緣層30m的上表面及下表面上設置絕緣薄膜,以確保各方向上的絕緣效果。藉由設置導熱係數高的金屬材料,可進一步增強封裝結構1f的散熱能力,以防止過熱並提升效率。此外,由於在封裝結構1f的上側及下側分別設置了金屬製的第一絕緣層10m及第三絕緣層30m,可防止來自封裝結構1f外部的電磁波干擾,使運作更加精確,並且不須在封裝結構1f外為了降低電磁干擾而再額外鍍製一金屬。An insulating film (not shown) is provided on both the first insulating layer 10m and the third insulating layer 30m to prevent short circuit between the metal material and other conductive structures (such as the aforementioned interconnect structure). Insulating films can be provided on the upper and lower surfaces of the first insulating layer 10m and the third insulating layer 30m, respectively, to ensure the insulating effect in all directions. By providing a metal material with a high thermal conductivity, the heat dissipation capacity of the package structure 1f can be further enhanced to prevent overheating and improve efficiency. In addition, since the first insulating layer 10m and the third insulating layer 30m made of metal are provided on the upper side and the lower side of the package structure 1f, respectively, electromagnetic interference from the outside of the package structure 1f can be prevented, making the operation more accurate and eliminating the need for In order to reduce electromagnetic interference, a metal is additionally plated outside the package structure 1f.

請參閱第1H圖,其繪示本發明另一實施例的封裝結構1g。與前述實施例不同的是,在本實施例中係使用金屬材料製的第一絕緣層10m與陶瓷材料製的第三絕緣層30c的組合。由於金屬材料製的第一絕緣層10m與陶瓷材料製的第三絕緣層30c的導熱係數皆比樹脂材料高,從而可進一步將封裝結構1g運作時所產生的熱量導出,以防止過熱並增加效能。此外,由於陶瓷材料製的第三絕緣層30c所需的空間較小,因此可在對尺寸要求較高的地方使用這種結構,以同時兼具小型化及增加散熱功效的目的。Please refer to FIG. 1H, which illustrates a package structure 1g according to another embodiment of the present invention. Different from the foregoing embodiment, in this embodiment, a combination of a first insulating layer 10m made of a metal material and a third insulating layer 30c made of a ceramic material is used. Since the thermal conductivity of the first insulating layer 10m made of metal material and the third insulating layer 30c made of ceramic material are higher than that of resin material, the heat generated during the operation of the package structure 1g can be further exported to prevent overheating and increase performance . In addition, since the space required for the third insulating layer 30c made of ceramic material is small, this structure can be used in places where the size is required to be both miniaturized and increase the heat dissipation effect.

請參閱第1I圖,其繪示本發明另一實施例的封裝結構1h。在本實施例中,第一絕緣層10r’及第三絕緣層30r’係以摻雜導電材料的樹脂材料形成。舉例來說,可摻雜氧化鋁、氮化鋁、金粉、銀粉、石墨等導電材料,以在第一絕緣層10r’及第三絕緣層30r’仍保持電性絕緣的條件下增加導熱係數,進而增加封裝結構1h的散熱速率,並達到較高的效能。Please refer to FIG. 1I, which illustrates a package structure 1h according to another embodiment of the present invention. In this embodiment, the first insulating layer 10r 'and the third insulating layer 30r' are formed of a resin material doped with a conductive material. For example, conductive materials such as aluminum oxide, aluminum nitride, gold powder, silver powder, and graphite can be doped to increase the thermal conductivity while the first insulating layer 10r 'and the third insulating layer 30r' still maintain electrical insulation. In turn, the heat dissipation rate of the package structure is increased for 1h, and a higher performance is achieved.

請參閱第1J圖,其繪示本發明另一實施例的封裝結構1i。與前述實施例不同的是,封裝結構1i之各絕緣層的厚度不同。如第1J圖所示,第三絕緣層30加上鈍化層81(上部絕緣層)具有厚度A,第二絕緣層20具有厚度B,且第一絕緣層10加上鈍化層80(下部絕緣層)具有厚度C,其中厚度B>厚度C>厚度A。由於上部絕緣層僅需與被動元件或外界絕緣,從而可降低其厚度,達到小型化的功效。下部絕緣層需與電路基板進行連接及承受衝擊,因此若將其厚度C設置為大於上部絕緣層的厚度A,可達到較佳的保護效果。由於在第二絕緣層20中設置了樹脂及各種元件(例如晶片40或其他積體電路元件),從而厚度B係設置為大於厚度A及厚度C。Please refer to FIG. 1J, which illustrates a package structure 1i according to another embodiment of the invention. Different from the foregoing embodiments, the thickness of each insulating layer of the packaging structure 1i is different. As shown in FIG. 1J, the third insulating layer 30 plus the passivation layer 81 (upper insulating layer) has a thickness A, the second insulating layer 20 has a thickness B, and the first insulating layer 10 plus the passivation layer 80 (lower insulating layer ) Has a thickness C, where thickness B> thickness C> thickness A. Since the upper insulating layer only needs to be insulated from the passive component or the outside world, it can reduce its thickness and achieve the effect of miniaturization. The lower insulating layer needs to be connected to the circuit board and bear the impact, so if the thickness C is set to be greater than the thickness A of the upper insulating layer, a better protection effect can be achieved. Since the second insulating layer 20 is provided with resin and various elements (for example, the wafer 40 or other integrated circuit elements), the thickness B is set to be greater than the thickness A and the thickness C.

在一些實施例中,亦可選擇合適的材料,使得第一絕緣層之導熱係數小於第三絕緣層之導熱係數,且使得第一絕緣層之硬度小於第三絕緣層之硬度,增加設計的靈活性,以符合各種需求。In some embodiments, a suitable material may also be selected so that the thermal conductivity of the first insulating layer is less than the thermal conductivity of the third insulating layer, and the hardness of the first insulating layer is less than the hardness of the third insulating layer, which increases the flexibility of design To meet various needs.

請參閱第2A圖,其繪示本發明另一實施例的封裝結構2a。封裝結構2a與前述封裝結構1c類似,差異在第一絕緣層10c上進一步設置了絕緣層90m。絕緣層90m可使用與前述實施例的第一絕緣層10m、第三絕緣層30m相同或相似的金屬材料所形成,並且在絕緣層90m上具有絕緣薄膜(未繪示)以防止絕緣層90m中的金屬材料與其他元件發生短路。在絕緣層90m兩側分別設置用以與外部電路連接的導線層54及導線層55,以及分別設置在導線層54及導線層55上的鈍化層82及鈍化層83。鈍化層82及鈍化層83與前述鈍化層80及81的材料、製程及用途類似,於此不再贅述。在絕緣層90m中還設置有導孔64,用以電性連接導線層54及導線層55。Please refer to FIG. 2A, which illustrates a package structure 2a according to another embodiment of the present invention. The packaging structure 2a is similar to the foregoing packaging structure 1c, except that an insulating layer 90m is further provided on the first insulating layer 10c. The insulating layer 90m can be formed using the same or similar metal material as the first insulating layer 10m and the third insulating layer 30m of the foregoing embodiments, and has an insulating film (not shown) on the insulating layer 90m to prevent the insulating layer 90m The metal material is short-circuited with other components. On both sides of the insulating layer 90m, a wire layer 54 and a wire layer 55 for connecting to an external circuit, and a passivation layer 82 and a passivation layer 83 respectively provided on the wire layer 54 and the wire layer 55 are provided. The materials, processes, and uses of the passivation layer 82 and the passivation layer 83 are similar to those of the aforementioned passivation layers 80 and 81, and will not be repeated here. A guide hole 64 is also provided in the insulating layer 90m for electrically connecting the wire layer 54 and the wire layer 55.

在第2A圖中,絕緣層90m的寬度比前述第一絕緣層10c及第三絕緣層30c寬,從而可在絕緣層90m上設置額外的元件(例如其他被動元件等),以達到更有效率的空間利用。此外,由於金屬材料形成的絕緣層90m的平面度較易控制,從而在封裝結構2a中設置絕緣層90m可使得封裝結構2a具有更佳的平面度。再者,由於額外設置了一層導熱係數高的絕緣層90m,可進一步增強散熱效率。In FIG. 2A, the width of the insulating layer 90m is wider than that of the first insulating layer 10c and the third insulating layer 30c, so that additional components (such as other passive components) can be placed on the insulating layer 90m to achieve more efficiency Space utilization. In addition, since the flatness of the insulating layer 90m formed of a metal material is easier to control, providing the insulating layer 90m in the packaging structure 2a can make the packaging structure 2a have better flatness. Furthermore, since an insulating layer 90m with a high thermal conductivity is additionally provided, the heat dissipation efficiency can be further enhanced.

請參閱第2B圖,其繪示本發明另一實施例的封裝結構2b。封裝結構2b與前述封裝結構2a的差別在於封裝結構2b係使用金屬製的第一絕緣層10m、第三絕緣層30m以及陶瓷製的絕緣層90c所製成,而其他相同或相似的元件描述於此不再贅述。藉由在封裝結構2b設置比第一絕緣層10m、第三絕緣層30m寬度大的絕緣層90c,以提升整體結構的散熱效果。此外,可進一步在絕緣層90c上設置其他的元件(例如被動元件),以更有效地利用空間。Please refer to FIG. 2B, which illustrates a package structure 2b according to another embodiment of the invention. The difference between the package structure 2b and the aforementioned package structure 2a is that the package structure 2b is made of a first insulating layer 10m made of metal, a third insulating layer 30m, and an insulating layer 90c made of ceramic, while other identical or similar components are described in This will not be repeated here. By providing an insulating layer 90c with a larger width than the first insulating layer 10m and the third insulating layer 30m in the packaging structure 2b, the heat dissipation effect of the overall structure is improved. In addition, other elements (for example, passive elements) may be further provided on the insulating layer 90c to use space more efficiently.

請參閱第3A圖,其繪示本發明另一實施例的封裝結構3a。在本實施例中,與前述封裝結構1c不同的是,在第一絕緣層10c上還可設置另一個封裝結構,其包括絕緣層100(與第二絕緣層20相似)以及金屬製的絕緣層110m。絕緣層110m上設置有與前述第一絕緣層10m、第三絕緣層30m相似的絕緣薄膜(未繪示),以防止絕緣層110m中的金屬材料與其他元件接觸而短路。Please refer to FIG. 3A, which illustrates a package structure 3a according to another embodiment of the present invention. In this embodiment, unlike the aforementioned packaging structure 1c, another packaging structure may be provided on the first insulating layer 10c, which includes an insulating layer 100 (similar to the second insulating layer 20) and a metal insulating layer 110m. An insulating film (not shown) similar to the first insulating layer 10m and the third insulating layer 30m described above is provided on the insulating layer 110m to prevent the metal material in the insulating layer 110m from contacting with other elements to short-circuit.

在第3A圖中,絕緣層100上下兩側分別設置了導線層56及導線層57,其中導線層56係設置在絕緣層100及第一絕緣層10c之間,並且與導孔60電性連接,而導線層57係設置在絕緣層100及絕緣層110m之間。在絕緣層110m背對絕緣層100的面上設置導線層58,且在導線層58上設置鈍化層84。此外,在絕緣層100中設置晶片41,且晶片41通過導電墊71及導孔67與導線層56電性連接。導線層56藉由設置在絕緣層100中的導孔65與導線層57電性連接,導線層57藉由設置在絕緣層110m中的導孔66與導線層58電性連接,而導線層58與外部的電路電性連接。In FIG. 3A, a conductive layer 56 and a conductive layer 57 are respectively provided on the upper and lower sides of the insulating layer 100, wherein the conductive layer 56 is disposed between the insulating layer 100 and the first insulating layer 10c, and is electrically connected to the via hole 60 And the wire layer 57 is disposed between the insulating layer 100 and the insulating layer 110m. A wire layer 58 is provided on the face of the insulating layer 110m facing away from the insulating layer 100, and a passivation layer 84 is provided on the wire layer 58. In addition, a wafer 41 is provided in the insulating layer 100, and the wafer 41 is electrically connected to the wire layer 56 through the conductive pad 71 and the via hole 67. The lead layer 56 is electrically connected to the lead layer 57 via the via 65 provided in the insulating layer 100, the lead layer 57 is electrically connected to the lead layer 58 via the via 66 provided in the insulating layer 110m, and the lead layer 58 Electrically connected to external circuits.

封裝結構3a允許在同個封裝結構中設置多層元件,從而可增加空間利用的效率,達到機構微型化的功效以及增加IC封裝的設計自由度。此外,由於封裝結構3a使用了導熱係數比傳統樹脂材料高的陶瓷製的第一絕緣層10c、第三絕緣層30c及金屬製的絕緣層110m,因此可使得封裝結構3a中元件運作時所產生的熱量更快地導出,以防止過熱並且增加效能。The packaging structure 3a allows multiple layers of components to be arranged in the same packaging structure, thereby increasing the efficiency of space utilization, achieving the effect of miniaturization of the mechanism, and increasing the design freedom of the IC package. In addition, since the package structure 3a uses the ceramic first insulating layer 10c, the third insulating layer 30c and the metal insulating layer 110m which have a higher thermal conductivity than the conventional resin material, the components in the package structure 3a can be generated during operation The heat is dissipated more quickly to prevent overheating and increase efficiency.

雖然在第3A圖的實施例中的封裝結構3a係使用陶瓷製的第一絕緣層10c、第三絕緣層30c及金屬製的絕緣層110m,但本發明並不限於此。可視設置需求置換上述元件的材料。舉例來說,請參閱第3B圖,其繪示本發明另一實施例的封裝結構3b。在本實施例中係採用金屬製的第一絕緣層10m、第三絕緣層30m及陶瓷製的絕緣層110c。這種結構同樣可增加導熱效率、達到機構微型化的功效以及增加IC封裝的設計自由度。Although the package structure 3a in the embodiment of FIG. 3A uses the ceramic first insulating layer 10c, the third insulating layer 30c, and the metal insulating layer 110m, the present invention is not limited to this. The materials of the above components can be replaced according to the setting requirements. For example, please refer to FIG. 3B, which illustrates a package structure 3b according to another embodiment of the present invention. In this embodiment, the first insulating layer 10m made of metal, the third insulating layer 30m and the insulating layer 110c made of ceramic are used. This structure can also increase the heat conduction efficiency, achieve the effect of miniaturization of the mechanism, and increase the design freedom of the IC package.

請參閱第4A圖,其繪示本發明另一實施例的封裝結構5a。在封裝結構5a中,第一絕緣層10及第三絕緣層30的配置方式及材料可與前述實施例的第一絕緣層10c、10m及第三絕緣層30c、30m相同或相似。在本實施例中,可在水平方向同時設置多個晶片40,並且可在封裝結構5a上方設置電子元件120(如各種被動元件等),並且可在封裝結構5a另一面設置焊球130,以與外部的其他元件焊接。由於使用了機械強度及平整性較佳的第一絕緣層10及第三絕緣層30,即使在第二絕緣層20中內埋多個晶片,仍然不會影響製程的精準度。此外,亦可提升各層之間的連接效果,加強整體的完整性。Please refer to FIG. 4A, which illustrates a package structure 5a according to another embodiment of the present invention. In the packaging structure 5a, the arrangement and materials of the first insulating layer 10 and the third insulating layer 30 may be the same as or similar to the first insulating layers 10c, 10m and the third insulating layers 30c, 30m of the foregoing embodiments. In this embodiment, a plurality of wafers 40 can be simultaneously arranged in the horizontal direction, and electronic components 120 (such as various passive components, etc.) can be disposed above the packaging structure 5a, and solder balls 130 can be disposed on the other side of the packaging structure 5a, to Welding with other external components. Since the first insulating layer 10 and the third insulating layer 30 with better mechanical strength and flatness are used, even if a plurality of chips are buried in the second insulating layer 20, the accuracy of the manufacturing process will not be affected. In addition, it can also improve the connection effect between the layers and enhance the overall integrity.

然而,本發明並不限於此。舉例來說,可視設計需求在不同方向及位置上設置被動元件以及更改結構。舉例來說,請參閱第4B圖,其繪示本發明另一實施例的封裝結構5b。在第4B圖中,與前述第4A圖不同的是,電子元件120改為設置在封裝結構5b的下方,而焊球130設置在另一面上,以增加設計的彈性。However, the present invention is not limited to this. For example, depending on design requirements, passive components can be placed in different directions and positions and the structure can be changed. For example, please refer to FIG. 4B, which illustrates a package structure 5b according to another embodiment of the present invention. In FIG. 4B, unlike the aforementioned FIG. 4A, the electronic component 120 is instead disposed under the package structure 5b, and the solder ball 130 is disposed on the other side, so as to increase the flexibility of the design.

於上述實施例中,雖然將晶片40繪示為設置在相同的水平高度上,但本發明並不限於此。根據設計需求,亦可將第4A圖或第4B圖左方與右方的晶片40分別設置在不同的水平高度上,以增加設計的自由度。In the above embodiment, although the wafer 40 is illustrated as being arranged at the same level, the present invention is not limited to this. According to the design requirements, the left and right wafers 40 in FIG. 4A or FIG. 4B can also be set at different levels to increase the degree of freedom in design.

綜上所述,本發明提供了一種封裝結構,具有第一絕緣層、第三絕緣層及設置在第一絕緣層及第三絕緣層間的第二絕緣層。第二絕緣層之導熱係數小於第一絕緣層及/或第三絕緣層之導熱係數,且第二絕緣層之硬度小於第一絕緣層及/或第三絕緣層之硬度。藉由這種配置方式,可使得封裝結構的元件於運作時所產生的熱量更有效率地導出,以防止封裝結構過熱。此外,亦可增加整體的結構強度,增加耐用性。In summary, the present invention provides a packaging structure having a first insulating layer, a third insulating layer, and a second insulating layer disposed between the first insulating layer and the third insulating layer. The thermal conductivity of the second insulating layer is less than the thermal conductivity of the first insulating layer and / or the third insulating layer, and the hardness of the second insulating layer is less than the hardness of the first insulating layer and / or the third insulating layer. With this arrangement, the heat generated by the components of the package structure during operation can be more efficiently conducted to prevent the package structure from overheating. In addition, it can also increase the overall structural strength and increase durability.

上述內容概述許多實施例的特徵,因此任何所屬技術領域中具有通常知識者,可更加理解本發明之各面向。任何所屬技術領域中具有通常知識者,可能無困難地以本發明為基礎,設計或修改其他製程及結構,以達到與本發明實施例相同的目的及/或得到相同的優點。任何所屬技術領域中具有通常知識者也應了解,在不脫離本發明之精神和範圍內做不同改變、代替及修改,如此等效的創造並沒有超出本發明的精神及範圍。The foregoing outlines the features of many embodiments, so anyone with ordinary knowledge in the art can more fully understand the aspects of the present invention. Any person with ordinary knowledge in the technical field may design or modify other processes and structures based on the present invention without difficulty, so as to achieve the same purposes and / or obtain the same advantages as the embodiments of the present invention. Any person with ordinary knowledge in the technical field should also understand that different changes, substitutions, and modifications can be made without departing from the spirit and scope of the present invention. Such an equivalent creation does not exceed the spirit and scope of the present invention.

1a、1b、1c、1d、1e、1f、1g、1h、1i、2a、2b、3a、3b、4、5a、5b‧‧‧封裝結構1a, 1b, 1c, 1d, 1e, 1f, 1g, 1h, 1i, 2a, 2b, 3a, 3b, 4, 5a, 5b

10、10c、10m、10r、10r’‧‧‧第一絕緣層10, 10c, 10m, 10r, 10r’‧‧‧‧ first insulation layer

11‧‧‧導電部11‧‧‧Conducting Department

22‧‧‧絕緣部22‧‧‧Insulation Department

20‧‧‧第二絕緣層20‧‧‧Second insulation layer

30、30c、30m、30r 、30r’‧‧‧第三絕緣層30, 30c, 30m, 30r, 30r’‧‧‧‧ third insulation layer

40、41‧‧‧晶片40、41‧‧‧chip

50、51、52、53、53’、54、55、56、57、58‧‧‧導線層50, 51, 52, 53, 53 ’, 54, 55, 56, 57, 58‧‧‧ wire layer

60、61、61’、62、63、64、65、66、67‧‧‧導孔60, 61, 61 ’, 62, 63, 64, 65, 66, 67

70、71‧‧‧導電墊70, 71‧‧‧ conductive pad

80、81、82、83、84‧‧‧鈍化層80, 81, 82, 83, 84 ‧‧‧ passivation layer

90m、90c、100、110m、110c‧‧‧絕緣層90m, 90c, 100, 110m, 110c ‧‧‧ insulation layer

120‧‧‧電子元件120‧‧‧Electronic components

130‧‧‧焊球130‧‧‧solder ball

A、B、C‧‧‧厚度A, B, C ‧‧‧ thickness

E‧‧‧彈性層E‧‧‧Elastic layer

H‧‧‧隔絕部H‧‧‧Isolation Department

R‧‧‧區域R‧‧‧Region

以下將配合所附圖式詳述本發明之實施例。應注意的是,依據在業界的標準做法,多種特徵並未按照比例繪示且僅用以說明例示。事實上,可能任意地放大或縮小元件的尺寸,以清楚地表現出本發明的特徵。 第1A圖為根據一實施例繪示的封裝結構的剖面圖。 第1B圖為根據本發明一實施例繪示的封裝結構的剖面圖。 第1C圖為根據本發明另一實施例繪示的封裝結構的剖面圖。 第1D圖為根據本發明另一實施例繪示的封裝結構的剖面圖。 第1E圖為根據本發明另一實施例繪示的封裝結構的剖面圖。 第1F圖為第1E圖中區域R的放大圖。 第1G圖為根據本發明另一實施例繪示的封裝結構的剖面圖。 第1H圖為根據本發明另一實施例繪示的封裝結構的剖面圖。 第1I圖為根據本發明另一實施例繪示的封裝結構的剖面圖。 第1J圖為根據本發明另一實施例繪示的封裝結構的剖面圖。 第2A圖為根據本發明另一實施例繪示的封裝結構的剖面圖。 第2B圖為根據本發明另一實施例繪示的封裝結構的剖面圖。 第3A圖為根據本發明另一實施例繪示的封裝結構的剖面圖。 第3B圖為根據本發明另一實施例繪示的封裝結構的剖面圖。 第4A圖為根據本發明另一實施例繪示的封裝結構的剖面圖。 第4B圖為根據本發明另一實施例繪示的封裝結構的剖面圖。The embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. It should be noted that, according to standard practices in the industry, various features are not drawn to scale and are for illustrative purposes only. In fact, it is possible to arbitrarily enlarge or reduce the size of the elements to clearly show the features of the present invention. FIG. 1A is a cross-sectional view of a package structure according to an embodiment. FIG. 1B is a cross-sectional view of a package structure according to an embodiment of the invention. FIG. 1C is a cross-sectional view of a package structure according to another embodiment of the invention. FIG. 1D is a cross-sectional view of a package structure according to another embodiment of the invention. FIG. 1E is a cross-sectional view of a package structure according to another embodiment of the invention. Figure 1F is an enlarged view of area R in Figure 1E. FIG. 1G is a cross-sectional view of a package structure according to another embodiment of the invention. FIG. 1H is a cross-sectional view of a package structure according to another embodiment of the invention. FIG. 1I is a cross-sectional view of a package structure according to another embodiment of the invention. FIG. 1J is a cross-sectional view of a package structure according to another embodiment of the invention. FIG. 2A is a cross-sectional view of a package structure according to another embodiment of the invention. FIG. 2B is a cross-sectional view of a package structure according to another embodiment of the invention. FIG. 3A is a cross-sectional view of a package structure according to another embodiment of the invention. FIG. 3B is a cross-sectional view of a package structure according to another embodiment of the invention. FIG. 4A is a cross-sectional view of a package structure according to another embodiment of the invention. FIG. 4B is a cross-sectional view of a package structure according to another embodiment of the invention.

Claims (18)

一種封裝結構,包括: 一第一絕緣層; 一第二絕緣層,設置在該第一絕緣層上; 一晶片,設置在該第二絕緣層中; 一第三絕緣層,設置在該第二絕緣層上; 其中該第二絕緣層之導熱係數小於該第一絕緣層之導熱係數,且該第二絕緣層之硬度小於該第一絕緣層之硬度。A packaging structure includes: a first insulating layer; a second insulating layer, disposed on the first insulating layer; a chip, disposed in the second insulating layer; a third insulating layer, disposed on the second On the insulating layer; wherein the thermal conductivity of the second insulating layer is less than the thermal conductivity of the first insulating layer, and the hardness of the second insulating layer is less than the hardness of the first insulating layer. 如申請專利範圍第1項所述之封裝結構,其中該第一絕緣層之材料包括陶瓷材料,且該第二絕緣層之材料包括樹脂材料。The packaging structure as described in item 1 of the patent application scope, wherein the material of the first insulating layer includes a ceramic material, and the material of the second insulating layer includes a resin material. 如申請專利範圍第2項所述之封裝結構,其中該第二絕緣層之材料不包括玻璃纖維。The packaging structure as described in item 2 of the patent application scope, wherein the material of the second insulating layer does not include glass fiber. 如申請專利範圍第2項所述之封裝結構,其中該第二絕緣層之導熱係數小於該第三絕緣層之導熱係數,且該第二絕緣層之硬度小於該第三絕緣層之硬度。The packaging structure as described in item 2 of the patent application range, wherein the thermal conductivity of the second insulating layer is less than the thermal conductivity of the third insulating layer, and the hardness of the second insulating layer is less than the hardness of the third insulating layer. 如申請專利範圍第4項所述之封裝結構,其中該第三絕緣層之材料包括陶瓷材料。The packaging structure as described in item 4 of the patent application scope, wherein the material of the third insulating layer includes a ceramic material. 如申請專利範圍第4項所述之封裝結構,其中該第三絕緣層包括一金屬層及一絕緣薄膜,且該絕緣薄膜係設置在該金屬層上。The packaging structure as described in item 4 of the patent application scope, wherein the third insulating layer includes a metal layer and an insulating film, and the insulating film is disposed on the metal layer. 如申請專利範圍第2項所述之封裝結構,更包括一彈性層,設置在該第一絕緣層上。The packaging structure described in item 2 of the scope of the patent application further includes an elastic layer disposed on the first insulating layer. 如申請專利範圍第7項所述之封裝結構,更包括一電子元件,設置在該第一絕緣層上。The packaging structure as described in item 7 of the patent application scope further includes an electronic component disposed on the first insulating layer. 如申請專利範圍第2項所述之封裝結構,其中該第一絕緣層之導熱係數小於該第三絕緣層之導熱係數,且該第一絕緣層之硬度小於該第三絕緣層之硬度。The packaging structure as described in item 2 of the patent application scope, wherein the thermal conductivity of the first insulating layer is less than the thermal conductivity of the third insulating layer, and the hardness of the first insulating layer is less than the hardness of the third insulating layer. 如申請專利範圍第2項所述之封裝結構,其中該第一絕緣層中之陶瓷材料之厚度大於該第一絕緣層之厚度的50%。The packaging structure as described in item 2 of the patent application scope, wherein the thickness of the ceramic material in the first insulating layer is greater than 50% of the thickness of the first insulating layer. 如申請專利範圍第1項所述之封裝結構,其中該第二絕緣層之厚度大於該第一絕緣層之厚度及大於該第三絕緣層之厚度。The packaging structure as described in item 1 of the patent application scope, wherein the thickness of the second insulating layer is greater than the thickness of the first insulating layer and greater than the thickness of the third insulating layer. 如申請專利範圍第11項所述之封裝結構,其中該第三絕緣層之厚度大於該第一絕緣層之厚度。The packaging structure as recited in item 11 of the patent application range, wherein the thickness of the third insulating layer is greater than the thickness of the first insulating layer. 如申請專利範圍第1項所述之封裝結構,其中該第一絕緣層之材料包括一金屬層及一第一絕緣薄膜,該第二絕緣層之材料包括樹脂材料,且該第一絕緣薄膜係設置在該金屬層上。The packaging structure as described in item 1 of the patent application scope, wherein the material of the first insulating layer includes a metal layer and a first insulating film, the material of the second insulating layer includes a resin material, and the first insulating film is Set on the metal layer. 如申請專利範圍第13項所述之封裝結構,其中該第三絕緣層之材料包括陶瓷材料。The packaging structure as described in item 13 of the patent application scope, wherein the material of the third insulating layer includes a ceramic material. 如申請專利範圍第13項所述之封裝結構,其中該第三絕緣層包括一金屬層及一第二絕緣薄膜。The packaging structure as described in item 13 of the patent application scope, wherein the third insulating layer includes a metal layer and a second insulating film. 如申請專利範圍第13項所述之封裝結構,其中該金屬層包括一導電部及一絕緣部,且該導電部與該絕緣部電性隔離。The packaging structure as recited in item 13 of the patent application range, wherein the metal layer includes a conductive portion and an insulating portion, and the conductive portion is electrically isolated from the insulating portion. 如申請專利範圍第1項所述之封裝結構,其中從平行該第一絕緣層及該第二絕緣層間界面的方向觀察,該第一絕緣層與該第二絕緣層不重疊,且該第二絕緣層與該第三絕緣層不重疊。The packaging structure as described in item 1 of the patent application scope, wherein the first insulating layer and the second insulating layer do not overlap when viewed from the direction parallel to the interface between the first insulating layer and the second insulating layer, and the second The insulating layer does not overlap with the third insulating layer. 如申請專利範圍第1項所述之封裝結構,更包括一第一導線層、一第二導線層、及複數導孔,其中該第一導線層係設置在該第一絕緣層及該第二絕緣層間,該第二導線層係設置在該第二絕緣層及該第三絕緣層間,且該等導孔電性連接該晶片、該第一導線層、及該第二導線層。The packaging structure as described in item 1 of the patent application scope further includes a first wire layer, a second wire layer, and a plurality of via holes, wherein the first wire layer is disposed on the first insulating layer and the second Between the insulation layers, the second wire layer is disposed between the second insulation layer and the third insulation layer, and the via holes are electrically connected to the chip, the first wire layer, and the second wire layer.
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