JP2010283035A - Electronic component, and method of manufacturing the same - Google Patents

Electronic component, and method of manufacturing the same Download PDF

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Publication number
JP2010283035A
JP2010283035A JP2009133400A JP2009133400A JP2010283035A JP 2010283035 A JP2010283035 A JP 2010283035A JP 2009133400 A JP2009133400 A JP 2009133400A JP 2009133400 A JP2009133400 A JP 2009133400A JP 2010283035 A JP2010283035 A JP 2010283035A
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Japan
Prior art keywords
bump
metal layer
electronic component
opening
forming
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Granted
Application number
JP2009133400A
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Japanese (ja)
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JP5658442B2 (en
Inventor
Tatsuo Uda
達夫 右田
Hirokazu Ezawa
弘和 江澤
Soichi Yamashita
創一 山下
Takashi Togasaki
隆 栂嵜
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Toshiba Corp
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Toshiba Corp
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Priority to JP2009133400A priority Critical patent/JP5658442B2/en
Priority to US12/721,741 priority patent/US8703600B2/en
Publication of JP2010283035A publication Critical patent/JP2010283035A/en
Application granted granted Critical
Publication of JP5658442B2 publication Critical patent/JP5658442B2/en
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing an electronic component capable of eliminating height differences among bumps that occur during the forming of the bumps in an electronic component that is connected to a wiring board or other electronic component via the bumps and stacked. <P>SOLUTION: A metal layer 33 is formed on the principle face of the electronic component formed with a pad 31. A resist is applied on the metal layer 33. Openings 52A, 52B corresponding to the formation position of the pad 31 are formed by lithography technique in such a way that the radius r2 of the opening 52B in bump formation areas linearly arranged is smaller than the radius r1 of some openings 52A in two-dimensionally arranged bump formation areas. A bump metal layer 350 is formed by plating technique on the metal layer 33 inside the openings 52A, 52B in such a way that the thickness of the bump metal layer 350 is smaller than the radius of the openings 52A, 52B. A resist mask 51 is removed. The metal layer 33 is removed by etching technique while the bump metal layer 350 is used as a mask. The bump metal layer 350 is made to reflow to form the bumps. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、電子部品とその製造方法に関する。   The present invention relates to an electronic component and a manufacturing method thereof.

半導体装置の小型化や高機能化などを実現するために、１つのパッケージ内に複数の半導体素子を積層して封止したパッケージ構造（ＣＯＣ（Chip on Chip）構造）が実用化されている。ＣＯＣパッケージはロジック素子と大容量のメモリ素子とを積層した構造などに応用されており、ＳｉＰ（System in Package）型の半導体装置として実用化が進められている。積層した半導体素子間の接続には、データ伝送速度の高速化などを図るためにフリップチップ接続の適用が検討されている（たとえば、特許文献１参照）。   In order to realize miniaturization and high functionality of a semiconductor device, a package structure (COC (Chip on Chip) structure) in which a plurality of semiconductor elements are stacked and sealed in one package has been put into practical use. The COC package is applied to a structure in which a logic element and a large-capacity memory element are stacked, and is being put into practical use as a SiP (System in Package) type semiconductor device. For connection between stacked semiconductor elements, application of flip chip connection is being studied in order to increase the data transmission speed (see, for example, Patent Document 1).

このような積層型半導体装置として、下面にパッドと半田ボールが設けられた配線基板の上面上に接着剤を介して第１の半導体素子が配置され、第１の半導体素子の上面上にさらに第２の半導体素子が配置される構造のものがある。配線基板の上面の外周部にはランド電極が配置され、第１の半導体素子の上面の外周部に配置された第１のパッドとワイヤボンディングによって接続される。また、第２の半導体素子の下面にはバンプが設けられており、第１の半導体素子の上面に形成された第２のパッドとフリップチップボンディングによって接続される。そして、第１の半導体素子と第２の半導体素子との間はアンダーフィル材によって充填され、さらに配線基板の上面の第１と第２の半導体素子は樹脂封止される。このように、フリップチップ接続によれば半導体素子間の接続距離が短縮されるため、たとえばメモリ素子とロジック素子との間のデータ伝送速度を高速化することができる。   In such a stacked semiconductor device, a first semiconductor element is disposed on an upper surface of a wiring board having pads and solder balls provided on the lower surface via an adhesive, and a first semiconductor element is further formed on the upper surface of the first semiconductor element. There is a structure in which two semiconductor elements are arranged. Land electrodes are disposed on the outer peripheral portion of the upper surface of the wiring substrate, and are connected to the first pads disposed on the outer peripheral portion of the upper surface of the first semiconductor element by wire bonding. Further, bumps are provided on the lower surface of the second semiconductor element, and are connected to a second pad formed on the upper surface of the first semiconductor element by flip chip bonding. The space between the first semiconductor element and the second semiconductor element is filled with an underfill material, and the first and second semiconductor elements on the upper surface of the wiring substrate are sealed with resin. As described above, according to the flip-chip connection, the connection distance between the semiconductor elements is shortened, so that, for example, the data transmission speed between the memory element and the logic element can be increased.

ところで、ＳｉＰ型の半導体装置では、下面に設けられるバンプが数千以上にも上る半導体素子（チップ）が用いられるようになっている。このようなバンプを数千以上も有する半導体素子においてはその厚さが薄くなってきており、チップ自身が有する反りの影響で配線基板または他のチップとの間で接続できないバンプが存在してしまう現象が生じている。そこで、バンプによってフリップチップ接続を行う際に、チップに反りが存在していても、すべてのバンプが接続されるように、チップの面内でバンプの高さを変える技術が提案されている（たとえば、特許文献２参照）。このように、従来、チップの反りなどに基づくフリップチップ接続前のバンプ形成位置の違いに由来するバンプの接続不良を解消する方法について提案されていたが、バンプを形成する際のプロセスに由来するバンプの高さの違いについては特に考慮されていなかった。   By the way, in a SiP type semiconductor device, a semiconductor element (chip) having thousands or more bumps provided on the lower surface is used. The thickness of such a semiconductor element having several thousand or more bumps has been reduced, and there are bumps that cannot be connected to the wiring board or other chips due to the warpage of the chip itself. A phenomenon has occurred. Therefore, when flip chip connection is performed using bumps, a technique has been proposed in which the bump height is changed within the surface of the chip so that all the bumps are connected even if there is warping in the chip ( For example, see Patent Document 2). As described above, a method for eliminating the bump connection failure resulting from the difference in the bump formation position before flip chip connection based on the warp of the chip has been proposed, but it originates from the process of forming the bump. The difference in bump height was not particularly taken into consideration.

特開２００９−３８２６６号公報JP 2009-38266 A 特開２００４−３３５６６０号公報JP 2004-335660 A

本発明は、バンプを介して配線基板または他の電子部品と接合して積層させる構造の半導体チップなどの電子部品において、バンプを形成する際のプロセスに由来するバンプの高さの違いを解消できる電子部品とその製造方法を提供することを目的とする。   INDUSTRIAL APPLICABILITY The present invention can eliminate a difference in bump height resulting from a process when forming a bump in an electronic component such as a semiconductor chip having a structure in which the wiring substrate or another electronic component is bonded and laminated via the bump. An object of the present invention is to provide an electronic component and a manufacturing method thereof.

本発明の一態様によれば、配線基板または他の電子部品との間で導電性バンプを介して接続される電子部品の製造方法において、導電性材料からなるパッドと、前記パッドの形成位置以外を覆うパッシベーション膜と、が形成された電子部品の主面上に、金属層を形成する第１の工程と、前記金属層上にレジストを塗布し、リソグラフィ法によって前記パッドの形成位置に対応する開口部を形成する第２の工程と、メッキ法によって、前記開口部内の前記金属層上にバンプ用金属層を形成する第３の工程と、前記レジストを除去する第４の工程と、前記バンプ用金属層をマスクとして、エッチング法によって前記金属層を除去する第５の工程と、リフロー処理によって、前記バンプ用金属層をリフローさせてバンプを形成する第６の工程と、を含み、前記第２の工程では、周囲に他のバンプが均等に配置されている第１のバンプ形成位置での前記開口部の径よりも、周囲に他のバンプが均等に配置されていない第２のバンプ形成位置での前記開口部の径を小さく形成し、前記第３の工程では、前記第２の工程で形成される開口部の径未満の厚さで前記バンプ用金属層を形成することを特徴とする電子部品の製造方法が提供される。   According to one aspect of the present invention, in a method of manufacturing an electronic component connected to a wiring board or another electronic component via a conductive bump, the pad made of a conductive material and a position other than the formation position of the pad A first step of forming a metal layer on the main surface of the electronic component on which the passivation film covering the substrate is formed; a resist is applied on the metal layer; A second step of forming an opening, a third step of forming a bump metal layer on the metal layer in the opening by a plating method, a fourth step of removing the resist, and the bump A fifth step of removing the metal layer by an etching method using the metal layer for a mask as a mask, and a sixth step of reflowing the bump metal layer by a reflow process to form a bump; In the second step, the other bumps are not evenly arranged around the diameter of the opening at the first bump forming position where the other bumps are uniformly arranged around the periphery. In the third step, the bump metal layer is formed with a thickness less than the diameter of the opening formed in the second step. An electronic component manufacturing method is provided.

また、本発明の一態様によれば、配線基板または他の電子部品との間で導電性バンプを介して接続される電子部品の製造方法において、中央部に二次元的に配置された第１のバンプ形成領域および周縁部に列状に配置された第２のバンプ形成領域に導電性材料からなるパッドを有し、前記パッドの形成位置以外を覆うようにパッシベーション膜が形成されてなる電子部品の主面上に、金属層を形成する第１の工程と、前記金属層上にレジストを塗布し、リソグラフィ法によって前記パッドの形成位置に対応する開口部を形成する第２の工程と、メッキ法によって、前記開口部内の前記金属層上にバンプ用金属層を形成する第３の工程と、前記レジストを除去する第４の工程と、前記バンプ用金属層をマスクとして、エッチング法によって前記金属層を除去する第５の工程と、リフロー処理によって、前記バンプ用金属層をリフローさせてバンプを形成する第６の工程と、を含み、前記第２の工程では、前記第２のバンプ形成領域での前記開口部の径を、前記第１のバンプ形成領域の少なくとも一部の前記開口部の径よりも小さく形成し、前記第３の工程では、前記第２の工程で形成される開口部の径未満の厚さで、前記バンプ用金属層を形成することを特徴とする電子部品の製造方法が提供される。   In addition, according to one aspect of the present invention, in the method of manufacturing an electronic component connected to a wiring board or another electronic component via a conductive bump, the first two-dimensionally arranged in the central portion. An electronic component having a pad made of a conductive material in the bump forming region and the second bump forming region arranged in a row at the periphery, and a passivation film is formed so as to cover other than the pad forming position A first step of forming a metal layer on the main surface, a second step of applying a resist on the metal layer, and forming an opening corresponding to the formation position of the pad by lithography, plating A third step of forming a bump metal layer on the metal layer in the opening by a method, a fourth step of removing the resist, and an etching method using the bump metal layer as a mask. A fifth step of removing the metal layer, and a sixth step of forming a bump by reflowing the bump metal layer by a reflow process. In the second step, forming the second bump A diameter of the opening in the region is smaller than a diameter of at least a part of the opening in the first bump formation region, and the opening formed in the second step is formed in the third step. There is provided a method of manufacturing an electronic component, wherein the bump metal layer is formed with a thickness less than the diameter of the part.

さらに、本発明の一態様によれば、所定の機能を有するように素子がチップ上に形成された電子部品において、一方の主面の中央部に二次元的に配置された第１のバンプ形成領域と、前記主面の周縁部に列状に配置された第２のバンプ形成領域と、に形成された導電性材料からなるパッドと、前記パッドの形成位置以外を覆うように前記主面上に形成されたパッシベーション膜と、前記パッド上に形成された金属層と、前記金属層上にメッキ形成された導電性材料からなるバンプと、を備え、前記第２のバンプ形成領域での前記金属層の径は、前記第１のバンプ形成領域の少なくとも一部の前記金属層の径よりも小さいことを特徴とする電子部品が提供される。   Furthermore, according to one aspect of the present invention, in an electronic component in which an element is formed on a chip so as to have a predetermined function, a first bump is two-dimensionally arranged at the center of one main surface. A pad made of a conductive material formed in a region, a second bump forming region arranged in a row at the peripheral edge of the main surface, and the main surface so as to cover other than the formation position of the pad A passivation layer formed on the pad, a metal layer formed on the pad, and a bump made of a conductive material plated on the metal layer, and the metal in the second bump formation region. An electronic component is provided in which the diameter of the layer is smaller than the diameter of at least a part of the metal layer in the first bump formation region.

本発明によれば、バンプを介して配線基板または他の電子部品と接合して積層させる構造の半導体チップなどの電子部品において、バンプを形成する際のプロセスに由来するバンプの高さの違いを解消できるという効果を奏する。   According to the present invention, in an electronic component such as a semiconductor chip having a structure in which a wiring board or another electronic component is bonded and laminated via a bump, the difference in height of the bump derived from the process at the time of forming the bump is determined. There is an effect that it can be eliminated.

図１は、本発明の実施の形態による電子部品装置の構成の一例を模式的に示す断面図である。FIG. 1 is a cross-sectional view schematically showing an example of the configuration of an electronic component device according to an embodiment of the present invention. 図２は、第２の半導体素子の電極形成面の一例を模式的に示す図である。FIG. 2 is a diagram schematically illustrating an example of an electrode formation surface of the second semiconductor element. 図３は、メッキ処理時のバンプ用金属層とリフロー処理後のバンプの一般的な状態を模式的に示す断面図である。FIG. 3 is a cross-sectional view schematically showing a general state of the bump metal layer during the plating process and the bump after the reflow process. 図４は、メッキ処理時のバンプ用金属層とリフロー処理後のバンプの他の状態を模式的に示す断面図である。FIG. 4 is a sectional view schematically showing another state of the bump metal layer during the plating process and the bump after the reflow process. 図５は、実施の形態によるメッキ処理時のバンプ用金属層とリフロー処理後のバンプの状態を模式的に示す断面図である。FIG. 5 is a cross-sectional view schematically showing the state of the bump metal layer during the plating process and the bump after the reflow process according to the embodiment. 図６は、実施の形態による電子部品の製造方法の手順の一例を模式的に示す断面図である（その１）。FIG. 6: is sectional drawing which shows typically an example of the procedure of the manufacturing method of the electronic component by embodiment (the 1). 図７は、実施の形態による電子部品の製造方法の手順の一例を模式的に示す断面図である（その２）。FIG. 7: is sectional drawing which shows typically an example of the procedure of the manufacturing method of the electronic component by embodiment (the 2).

以下に添付図面を参照して、本発明の実施の形態にかかる電子部品とその製造方法を詳細に説明する。なお、この実施の形態により本発明が限定されるものではない。また、以下の実施の形態で用いられる電子部品の断面図は模式的なものであり、層の厚みと幅との関係や各層の厚みの比率などは現実のものとは異なる。さらに、以下で示す膜厚は一例であり、これに限定されるものではない。   Exemplary embodiments of an electronic component and a manufacturing method thereof according to the present invention will be explained below in detail with reference to the accompanying drawings. In addition, this invention is not limited by this embodiment. The cross-sectional views of the electronic components used in the following embodiments are schematic, and the relationship between the thickness and width of the layers, the ratio of the thicknesses of the layers, and the like are different from the actual ones. Furthermore, the film thickness shown below is an example and is not limited thereto.

図１は、電子部品装置の構成の一例を模式的に示す断面図である。ここでは、電子部品装置としてＳｉＰ型の半導体装置である積層型半導体装置１を例に挙げる。積層型半導体装置１は、インタポーザとして機能する配線基板１０上に、電子部品である第１の半導体素子２０と第２の半導体素子３０とが、順に積層された構造を有する。   FIG. 1 is a cross-sectional view schematically showing an example of the configuration of an electronic component device. Here, a multilayer semiconductor device 1 which is a SiP type semiconductor device is taken as an example of the electronic component device. The stacked semiconductor device 1 has a structure in which a first semiconductor element 20 and a second semiconductor element 30 that are electronic components are sequentially stacked on a wiring substrate 10 that functions as an interposer.

配線基板１０は半導体素子を搭載することが可能で、かつ配線網を有するものであればよく、樹脂基板、セラミックス基板、ガラス基板などの各種絶縁基板やシリコンなどの半導体基板に内層配線や表面配線による配線網を設けたものなどが用いられる。樹脂基板を適用した配線基板１０としてはプリント配線板が例示される。   The wiring substrate 10 may be any substrate as long as a semiconductor element can be mounted and has a wiring network. Inner layer wiring or surface wiring on various insulating substrates such as a resin substrate, a ceramic substrate, a glass substrate, or a semiconductor substrate such as silicon. The one provided with the wiring network is used. A printed wiring board is exemplified as the wiring substrate 10 to which the resin substrate is applied.

配線基板１０の上面側の中央付近には、第１の半導体素子２０が配置され、外周部には、第１の半導体素子２０と電気的に接続するための接続パッド１１が設けられている。また、配線基板１０の下面側には、はんだバンプなどの外部接続端子１２が設けられている。配線基板１０の上面の外周部に設けられた接続パッド１１と、配線基板１０の下面の外部接続端子１２との間は、配線基板１０に設けられた配線網１３によって、それぞれ電気的に接続される。   A first semiconductor element 20 is disposed near the center of the upper surface side of the wiring substrate 10, and a connection pad 11 for electrical connection with the first semiconductor element 20 is provided on the outer periphery. In addition, external connection terminals 12 such as solder bumps are provided on the lower surface side of the wiring board 10. The connection pads 11 provided on the outer peripheral portion of the upper surface of the wiring substrate 10 and the external connection terminals 12 on the lower surface of the wiring substrate 10 are electrically connected by the wiring network 13 provided on the wiring substrate 10, respectively. The

第１の半導体素子２０は、配線基板１０の上面側の中央付近の素子搭載部に配置され、接着剤層４１によって接着されている。この第１の半導体素子２０の上面には、電極パッド２１が設けられており、電極パッド２１の形成面（電極形成面）を上方に向けて配線基板１０上に搭載されている。この電極パッド２１は、配線基板１０とは異なり、第１の半導体素子２０の上面の略全面に形成されている。そして、この電極パッド２１は、上面の外周部に形成され、配線基板１０と接続される第１のパッド群２１Ａと、上面の中央部に形成され、第２の半導体素子３０と接続される第２のパッド群２１Ｂと、を有する。第１のパッド群２１Ａはワイヤボンディング部を構成するものであり、第２のパッド群２１Ｂはフリップチップ接続部を構成するものである。第１のパッド群２１Ａは導電性ワイヤ４２を介して配線基板１０の接続パッド１１と電気的に接続される。この導電性ワイヤ４２として、一般的なＡｕ線やＣｕ線などの金属細線が用いられる。   The first semiconductor element 20 is disposed in an element mounting portion near the center on the upper surface side of the wiring substrate 10 and bonded by an adhesive layer 41. An electrode pad 21 is provided on the upper surface of the first semiconductor element 20 and is mounted on the wiring substrate 10 with the electrode pad 21 forming surface (electrode forming surface) facing upward. Unlike the wiring substrate 10, the electrode pad 21 is formed on substantially the entire upper surface of the first semiconductor element 20. The electrode pad 21 is formed on the outer peripheral portion of the upper surface and is formed in the first pad group 21A connected to the wiring substrate 10 and the central portion of the upper surface and connected to the second semiconductor element 30. 2 pad groups 21B. The first pad group 21A constitutes a wire bonding part, and the second pad group 21B constitutes a flip chip connecting part. The first pad group 21 </ b> A is electrically connected to the connection pad 11 of the wiring substrate 10 through the conductive wire 42. As the conductive wire 42, a thin metal wire such as a general Au wire or Cu wire is used.

第２の半導体素子３０は、第１の半導体素子２０上に配置され、所定の機能を有するように素子が形成されたデバイスチップからなる。第２の半導体素子３０の下面（主面）側には、図示しないパッドが設けられ、このパッド上にバンプ（はんだバンプ）３５が接続されている。このバンプ３５として、Ｃｕ／Ｓｎなどが用いられる。第２の半導体素子３０のバンプ３５の形成位置を、第１の半導体素子２０の上面に形成された第２のパッド群２１Ｂの形成位置に合わせて、フリップチップ接続して、両者を接続している。また、第１の半導体素子２０と第２の半導体素子３０との間の隙間には、アンダーフィル剤として樹脂４３が充填されている。この樹脂４３には、たとえばエポキシ樹脂、フェノール樹脂、シリコーン樹脂などの熱硬化性樹脂が用いられる。   The second semiconductor element 30 is a device chip that is disposed on the first semiconductor element 20 and on which elements are formed to have a predetermined function. A pad (not shown) is provided on the lower surface (main surface) side of the second semiconductor element 30, and a bump (solder bump) 35 is connected to the pad. As this bump 35, Cu / Sn or the like is used. The bump 35 of the second semiconductor element 30 is formed at a position corresponding to the formation position of the second pad group 21B formed on the upper surface of the first semiconductor element 20, and is flip-chip connected. Yes. In addition, a gap between the first semiconductor element 20 and the second semiconductor element 30 is filled with a resin 43 as an underfill agent. For the resin 43, for example, a thermosetting resin such as an epoxy resin, a phenol resin, or a silicone resin is used.

そして、配線基板１０上に積層、配置された第１と第２の半導体素子２０，３０は、たとえばエポキシ樹脂のような封止樹脂４４で導電性ワイヤ４２などとともに封止されており、これらによって積層型半導体装置１が構成されている。   The first and second semiconductor elements 20 and 30 stacked and arranged on the wiring substrate 10 are sealed together with the conductive wires 42 with a sealing resin 44 such as an epoxy resin, for example. A stacked semiconductor device 1 is configured.

図２は、第２の半導体素子の電極形成面の一例を模式的に示す図であり、（ａ）は第２の半導体素子の電極形成面の一部断面図であり、（ｂ）は裏面図である。この図２では、バンプをリフロー処理した後の様子を示している。なお、これらの図は、模式的に示した図であり、実際のバンプの個数や配置状態を示すものではない。   FIG. 2 is a diagram schematically showing an example of an electrode formation surface of the second semiconductor element, (a) is a partial cross-sectional view of the electrode formation surface of the second semiconductor element, and (b) is a back surface. FIG. FIG. 2 shows a state after the reflow processing of the bumps. These drawings are schematic views, and do not show the actual number or arrangement of bumps.

図２（ａ）に示されるように、第２の半導体素子３０の主面には、アルミニウムなどの導電性材料からなる所定の形状のパッド３１と、パッド形成位置以外の第２の半導体素子３０の主面全体を覆うシリコン窒化膜などからなるパッシベーション膜３２と、が形成される。パッド３１上およびその周囲のパッシベーション膜３２上には、ＴｉとＣｕの積層膜などからなるバリアメタル層３３と、Ｎｉなどからなるバリア層３４と、が順に積層され、バリア層３４上にはＣｕとＳｎなどからなるバンプ（はんだバンプ）３５が形成されている。バリアメタル層３３のＴｉ膜はパッド３１とＣｕ膜との密着性を高める役割を有し、Ｃｕ膜はバリア用金属層を形成するためのメッキ処理時の通電層の役割を有する。また、バリア層３４は、バンプ３５とバリアメタル層３３との間の相互拡散を防止する役割を有する。   As shown in FIG. 2A, on the main surface of the second semiconductor element 30, a pad 31 having a predetermined shape made of a conductive material such as aluminum, and the second semiconductor element 30 other than the pad formation position. And a passivation film 32 made of a silicon nitride film or the like covering the entire main surface. On the pad 31 and the passivation film 32 around it, a barrier metal layer 33 made of a laminated film of Ti and Cu and a barrier layer 34 made of Ni or the like are sequentially laminated. Bumps (solder bumps) 35 made of Sn and Sn are formed. The Ti film of the barrier metal layer 33 has a role of improving the adhesion between the pad 31 and the Cu film, and the Cu film has a role of an energization layer during plating for forming a barrier metal layer. Further, the barrier layer 34 has a role of preventing mutual diffusion between the bump 35 and the barrier metal layer 33.

ここで、図２（ｂ）に示されるように、第２の半導体素子３０の主面には、多数のバンプ３５が配置されているが、主面の周縁部近傍の領域ＲDに配置されるバンプ３５はたとえば電源用のバンプであり、主面の中央部付近の領域ＲSに配置されるバンプ３５はたとえば信号用のバンプである。電源用のバンプは、通常は第２の半導体素子３０の主面の外周に沿う１〜２列のバンプ３５によって形成される。また、信号用のバンプは、複数のバンプ３５が二次元的に密集したバンプ群によって構成される。 Here, as shown in FIG. 2B, a large number of bumps 35 are arranged on the main surface of the second semiconductor element 30, but are arranged in a region RD near the peripheral edge of the main surface. that the bumps 35 are bumps for power supply for example, bumps 35 are arranged in the region R S in the vicinity of the center portion of the main surface is a bump for example signals. The power supply bumps are usually formed by one or two rows of bumps 35 along the outer periphery of the main surface of the second semiconductor element 30. The signal bumps are constituted by a bump group in which a plurality of bumps 35 are two-dimensionally dense.

このバンプ３５には、密の配置形態を有する第１のバンプ３５１と疎の配置形態を有する第２のバンプ３５２の２つの配置の種類がある。密の配置形態を有する第１のバンプ３５１とは、ある１つのバンプ３５に注目したときに、その周囲に規則的に他のバンプ３５が配置されているバンプ３５のことをいう。この第１のバンプ３５１として、たとえば図中の信号用のバンプにおける最外周以外のバンプを例示することができ、図中ではハッチングを付して後述する第２のバンプ３５２と区別して示している。また、第１のバンプ３５１は、バンプ３５の径と隣接するバンプ３５との距離の比が、およそ１対１であるバンプ３５として定義することもできる。   The bumps 35 are classified into two types, that is, a first bump 351 having a dense arrangement form and a second bump 352 having a sparse arrangement form. The first bump 351 having a dense arrangement form means a bump 35 in which other bumps 35 are regularly arranged around one bump 35 when attention is paid to one bump 35. As the first bumps 351, for example, bumps other than the outermost periphery in the signal bumps in the figure can be exemplified, and in the figure, hatching is given and distinguished from the second bumps 352 described later. . The first bump 351 can also be defined as a bump 35 having a ratio of the distance between the diameter of the bump 35 and the adjacent bump 35 of approximately 1: 1.

一方の疎の配置形態を有する第２のバンプ３５２とは、ある１つのバンプ３５に注目したときに、その周囲に規則的に他のバンプ３５が配置されていないバンプ３５のことをいう。この第２のバンプ３５２として、たとえば図中の信号用バンプにおける最外周のバンプや電源用のバンプを例示することができる。これらの第２のバンプ３５２は、規則的に配置されたバンプのうち最も外側に配置されるバンプである。また、第２のバンプ３５２は、バンプ３５の径と周囲のバンプ３５のうち隣接する少なくとも１つのバンプとの距離の比が１対２以上であるバンプ３５として定義することもできる。   The second bump 352 having one sparse arrangement form refers to a bump 35 in which, when attention is paid to a certain bump 35, other bumps 35 are not regularly arranged around it. As the second bump 352, for example, the outermost bump or the power supply bump in the signal bump in the figure can be exemplified. These second bumps 352 are the bumps arranged on the outermost side among the regularly arranged bumps. The second bump 352 can also be defined as a bump 35 in which the ratio of the diameter of the bump 35 and the distance between at least one adjacent bump 35 is 1 or more.

図３は、メッキ処理時のバンプ用金属層とリフロー処理後のバンプの一般的な状態を模式的に示す断面図である。まず、図３（ａ）に示されるように、バリアメタル層３３上に形成されたレジストマスク５１の第１と第２のバンプ形成用開口部５２Ａ，５２Ｂ内にメッキ法によって、バリア層３４とバンプ用金属層３５０が形成される。メッキ処理では、疎の配置形態を有する第２のバンプ形成用開口部５２Ｂには他の部分よりも電界が強くかかるため、ここで形成されるバンプ用金属層３５０の膜厚ｈ２は、第１のバンプ形成用開口部５２Ａでの膜厚ｈ１よりも厚くなっている。つぎに、レジストマスク５１を除去し、バンプ用金属層３５０をマスクとしてパッド３１形成位置付近以外のバリアメタル層３３を除去した後に、リフロー処理することによって、図３（ｂ）に示されるバンプ３５１，３５２が形成される。   FIG. 3 is a cross-sectional view schematically showing a general state of the bump metal layer during the plating process and the bump after the reflow process. First, as shown in FIG. 3A, the barrier layer 34 and the first bump formation openings 52A and 52B of the resist mask 51 formed on the barrier metal layer 33 are plated by plating. A bump metal layer 350 is formed. In the plating process, since the electric field is applied to the second bump forming opening 52B having a sparse arrangement form more strongly than the other portions, the film thickness h2 of the bump metal layer 350 formed here is the first thickness. It is thicker than the film thickness h1 in the bump forming opening 52A. Next, the resist mask 51 is removed, the barrier metal layer 33 other than the vicinity of the pad 31 formation position is removed using the bump metal layer 350 as a mask, and then the reflow process is performed, whereby the bump 351 shown in FIG. , 352 are formed.

ここでは、図３（ａ）に示されるように、密の配置形態を有する第１のバンプ３５１を形成するための第１のバンプ形成用開口部５２Ａの径ｒ１と、疎の配置形態を有する第２のバンプ３５２を形成するための第２のバンプ形成用開口部５２Ｂの径ｒ２とを、同じ大きさに設定している。このような状態で、リフロー処理を行うと、図３（ｂ）に示されるように、バンプ用金属層３５０の膜厚が厚い第２のバンプ３５２の高さＨ２が、第１のバンプ３５１の高さＨ１よりも高くなる。   Here, as shown in FIG. 3A, the first bump forming opening 52A for forming the first bump 351 having a dense arrangement form has a diameter r1 and a sparse arrangement form. The diameter r2 of the second bump forming opening 52B for forming the second bump 352 is set to the same size. When the reflow process is performed in such a state, as shown in FIG. 3B, the height H2 of the second bump 352 having the thick bump metal layer 350 becomes larger than that of the first bump 351. It becomes higher than the height H1.

この図３（ｂ）に示されるような高さの異なるバンプ３５１，３５２を有する電子部品をフリップチップ接続すると、バンプ３５１，３５２の高さの違いによって、高さの低い第１のバンプ３５１が配線基板や他の電子部品のパッドと接続することができないという事態が発生してしまう。   When an electronic component having bumps 351 and 352 having different heights as shown in FIG. 3B is flip-chip connected, the first bump 351 having a lower height is caused by the difference in height between the bumps 351 and 352. The situation that it cannot connect with the pad of a wiring board or another electronic component will generate | occur | produce.

そこで、本発明者らは、レジストマスクのバンプ形成用開口部の径が異なるが、高さ（厚さ）が同じとなるようにバンプ用金属層を形成し、それをリフロー処理する実験を行った。図４は、メッキ処理時のバンプ用金属層とリフロー処理後のバンプの他の状態を模式的に示す断面図である。図４（ａ）に示されるように、各バンプ形成用開口部の径を、１５，１６，１７，１８，１９，２０μｍとし、高さをいずれも１０μｍとしたバンプ用金属層３５０を形成する。そして、これをリフロー処理したところ、図４（ｂ）に示されるように、バンプ形成用開口部の径が小さいほどリフロー処理後のバンプ３５の高さが低くなることを見出した。   Therefore, the present inventors conducted an experiment in which a bump metal layer was formed so as to have the same height (thickness) and the reflow treatment was performed although the diameter of the bump formation opening of the resist mask was different. It was. FIG. 4 is a sectional view schematically showing another state of the bump metal layer during the plating process and the bump after the reflow process. As shown in FIG. 4 (a), a bump metal layer 350 having a diameter of each bump forming opening of 15, 16, 17, 18, 19, 20 μm and a height of 10 μm is formed. . Then, as a result of reflow processing, as shown in FIG. 4 (b), it was found that the smaller the diameter of the bump forming opening, the lower the height of the bump 35 after the reflow processing.

ただし、上記のような現象が生じるのは、バンプ用金属層３５０の厚さｈがバンプ形成用開口部の径ｒ未満の場合に限られる。これは、バンプ用金属層３５０の厚さｈがバンプ形成用開口部の径ｒ以上になると、リフロー処理によって表面積が最小の球状に近づくようにより横方向に広がる傾向があるからである。その結果、バンプ形成用開口部の径が大きなバンプ用金属層３５０の方が、リフロー処理後にバンプ形成用開口部の径が小さなバンプ用金属層３５０よりも低くなってしまう可能性があり、図４（ｂ）に示されるような結果が得られるとは限らない場合がある。また、リフロー処理によってバンプが球となるように横方向に広がってしまうと、隣接するバンプとの接触の虞を排除するためのマージンが必要となり、微細化を阻む要因となる。そのため、この実施の形態では、バンプ用金属層３５０の厚さｈをバンプ形成用開口部の径ｒ未満としている。   However, the phenomenon described above occurs only when the thickness h of the bump metal layer 350 is less than the diameter r of the bump forming opening. This is because, when the thickness h of the bump metal layer 350 becomes equal to or larger than the diameter r of the bump forming opening, the surface area tends to expand in a lateral direction so as to approach a sphere having the smallest surface area by the reflow process. As a result, there is a possibility that the bump metal layer 350 having a larger diameter for the bump forming opening becomes lower than the bump metal layer 350 having a smaller diameter for the bump forming opening after the reflow process. The result shown in 4 (b) may not always be obtained. Further, if the bumps are spread laterally so as to form a sphere by the reflow process, a margin for eliminating the possibility of contact with the adjacent bumps is necessary, which becomes a factor that prevents miniaturization. Therefore, in this embodiment, the thickness h of the bump metal layer 350 is less than the diameter r of the bump forming opening.

以上より、バンプ用金属層３５０の厚さｈがバンプ形成用開口部の径ｒ未満である状態を保ちつつ、バンプ形成用開口部の径が小さい方のバンプ用金属層３５０の厚さを、バンプ形成用開口部の径が大きい方のバンプ用金属層３５０の厚さよりも厚くしていけば、リフロー処理後の２つのバンプの高さが等しくなる場合が存在することになる。そこで、この実施の形態では、バンプ用金属層３５０の厚さｈがバンプ形成用開口部の径ｒ未満である条件を満たすとともに、第２のバンプ形成用開口部５２Ｂの開口径を第１のバンプ形成用開口部５２Ａの開口径よりも小さくしている。図５は、実施の形態によるメッキ処理時のバンプ用金属層とリフロー処理後のバンプの状態を模式的に示す断面図である。図５（ａ）に示されるように、疎の配置形態を有する第２のバンプ形成用開口部５２Ｂの開口径ｒ２を、密の配置形態を有する第１のバンプ形成用開口部５２Ａの開口径ｒ１よりも小さくしている。また、メッキ処理時には、上記したように、第２のバンプ形成用開口部５２Ｂには、第１のバンプ形成用開口部５２Ａよりも強い電界がかかるので、形成されるバンプ用金属層３５０の厚さｈ２は、第１のバンプ形成用開口部５２Ａでのバンプ用金属層３５０の厚さｈ１よりも厚くなる。この厚さは、たとえば図３（ａ）での第２のバンプ形成用開口部５２Ｂで形成されるバンプ用金属層３５０の厚さｈ２と同じである。これによって、図３（ａ）の場合の第２のバンプ形成用開口部５２Ｂと比べて、高さｈ２が同じで開口部の径ｒ２が小さくなっているので、リフロー処理後の第２のバンプ３５２の高さは、図５（ｂ）に示されるように、第１のバンプ３５１とほぼ同じ高さとなり、バンプ３５間のばらつきが緩和されるようになる。   As described above, the thickness of the bump metal layer 350 with the smaller diameter of the bump forming opening is maintained while the thickness h of the bump metal layer 350 is less than the diameter r of the bump forming opening. If the bump forming opening is made thicker than the bump metal layer 350 having a larger diameter, the two bumps after the reflow process may have the same height. Therefore, in this embodiment, the condition that the thickness h of the bump metal layer 350 is less than the diameter r of the bump forming opening is satisfied, and the opening diameter of the second bump forming opening 52B is set to the first diameter. It is smaller than the opening diameter of the bump forming opening 52A. FIG. 5 is a cross-sectional view schematically showing the state of the bump metal layer during the plating process and the bump after the reflow process according to the embodiment. As shown in FIG. 5A, the opening diameter r2 of the second bump forming opening 52B having a sparse arrangement is defined as the opening diameter r2 of the first bump forming opening 52A having a dense arrangement. It is smaller than r1. In addition, as described above, since a stronger electric field is applied to the second bump forming opening 52B than the first bump forming opening 52A during the plating process, the thickness of the bump metal layer 350 to be formed is increased. The length h2 is thicker than the thickness h1 of the bump metal layer 350 in the first bump formation opening 52A. This thickness is, for example, the same as the thickness h2 of the bump metal layer 350 formed by the second bump formation opening 52B in FIG. Accordingly, the height h2 is the same and the diameter r2 of the opening is smaller than that of the second bump forming opening 52B in the case of FIG. As shown in FIG. 5B, the height of 352 is substantially the same as that of the first bump 351, and variations between the bumps 35 are alleviated.

つまり、図２において、第２のバンプ３５２のバリアメタル層３３の径を、第１のバンプ３５１のバリアメタル層３３の径よりも小さく形成している。たとえば、第１のバンプ３５１のバリアメタル層３３の径は２０μｍであり、第２のバンプ３５２のバリアメタル層３３の径は１８μｍである。このように、疎の配置形態を有する第２のバンプ３５２のバリアメタル層３３の径を、密の配置形態を有する第１のバンプ３５１のバリアメタル層３３の径よりも小さくすることによって、リフロー処理後の各バンプ３５の高さを略同じ高さに制御することができる。   That is, in FIG. 2, the diameter of the barrier metal layer 33 of the second bump 352 is formed smaller than the diameter of the barrier metal layer 33 of the first bump 351. For example, the diameter of the barrier metal layer 33 of the first bump 351 is 20 μm, and the diameter of the barrier metal layer 33 of the second bump 352 is 18 μm. As described above, the diameter of the barrier metal layer 33 of the second bump 352 having the sparse arrangement form is made smaller than the diameter of the barrier metal layer 33 of the first bump 351 having the dense arrangement form. The height of each bump 35 after processing can be controlled to be substantially the same.

つぎに、このような電子部品の製造方法について説明する。図６〜図７は、この実施の形態による電子部品の製造方法の手順の一例を模式的に示す断面図である。まず、図示しない電界効果型トランジスタや配線などを形成したシリコン基板などの基板１０１の主面上に、アルミニウム膜を形成し、フォトリソグラフィ技術とエッチング技術によって所定形状のパッド３１を形成する。また、パッド３１が形成された主面上には、ＣＶＤ（Chemical Vapor Deposition）法などの成膜法によってシリコン窒化膜などのパッシベーション膜３２を形成する。そして、フォトリソグラフィ技術とエッチング技術によって、パッド３１の形成位置のみパッシベーション膜３２が除去され、パッド３１の表面が露出される状態となる（図６（ａ））。   Next, a method for manufacturing such an electronic component will be described. 6-7 is sectional drawing which shows typically an example of the procedure of the manufacturing method of the electronic component by this embodiment. First, an aluminum film is formed on a main surface of a substrate 101 such as a silicon substrate on which field effect transistors and wirings (not shown) are formed, and a pad 31 having a predetermined shape is formed by a photolithography technique and an etching technique. Further, a passivation film 32 such as a silicon nitride film is formed on the main surface on which the pad 31 is formed by a film forming method such as a CVD (Chemical Vapor Deposition) method. Then, the passivation film 32 is removed only at the formation position of the pad 31 by the photolithography technique and the etching technique, and the surface of the pad 31 is exposed (FIG. 6A).

ついで、パッド３１とパッシベーション膜３２上に、バリアメタル層３３を形成する（図６（ｂ））。たとえば、バリアメタル層３３として、２００ｎｍのＴｉ膜と３００ｎｍのＣｕ膜を、スパッタ法や蒸着法などの成膜法によって形成する。   Next, a barrier metal layer 33 is formed on the pad 31 and the passivation film 32 (FIG. 6B). For example, as the barrier metal layer 33, a 200 nm Ti film and a 300 nm Cu film are formed by a film forming method such as sputtering or vapor deposition.

その後、バリアメタル層３３上に、レジストを塗布し、フォトリソグラフィ技術によって、バンプ形成位置にバンプ形成用開口部５２Ａ，５２Ｂを設けるように露光、現像を行ってレジストマスク５１を形成する（図６（ｃ））。このとき、第２のバンプ３５２（信号用のバンプ形成領域ＲSの最外周のバンプと電源用のバンプ形成領域ＲDのバンプ）の形成位置に対応する開口部（第２のバンプ形成用開口部）５２Ｂの開口径ｒ２は、第１のバンプ３５１（信号用のバンプ形成領域ＲSのうち最外周以外のバンプ）の形成位置に対応する開口部（第１のバンプ形成用開口部）５２Ａの開口径ｒ１よりも所定の量だけ小さくされる。たとえば、第１のバンプ形成用開口部５２Ａの開口径ｒ１が２０μｍの場合には、第２のバンプ形成用開口部５２Ｂの開口径ｒ２は１８μｍとする。 Thereafter, a resist is applied onto the barrier metal layer 33, and exposure and development are performed by a photolithography technique so as to provide bump formation openings 52A and 52B at bump formation positions, thereby forming a resist mask 51 (FIG. 6). (C)). At this time, an opening (second bump formation opening) corresponding to the formation position of the second bump 352 (the outermost periphery bump of the signal bump formation region RS and the bump of the power supply bump formation region RD ). Portion) 52B has an opening diameter r2 corresponding to the position where the first bump 351 (the bump other than the outermost periphery in the signal bump formation region RS ) is formed (first bump formation opening) 52A. Is smaller than the opening diameter r1 by a predetermined amount. For example, when the opening diameter r1 of the first bump forming opening 52A is 20 μm, the opening diameter r2 of the second bump forming opening 52B is 18 μm.

ついで、たとえば電解メッキ法によって、メッキ処理溶液中でバリアメタル層３３のＣｕ膜に通電し、レジストマスク５１の各バンプ形成用開口部５２Ａ，５２Ｂ内のバリアメタル層３３上にバリア層３４と、バンプとなるバンプ用金属層３５０を順に形成する（図６（ｄ））。ここでは、バリア層３４として５〜６μｍのＮｉ膜を形成し、バンプ用金属層３５０として０．３５〜０．５０μｍのＣｕ膜と６〜７μｍのＳｎ膜を順に形成する。このとき、バリア層３４とバンプ用金属層３５０の膜厚が所定の厚さとなるように、メッキ処理時間が制御される。また、この実施の形態では、バンプ形成用開口部５２Ａ，５２Ｂの径よりも形成するバンプ用金属層３５０の厚さが薄い場合を対象としている。   Next, the Cu film of the barrier metal layer 33 is energized in a plating solution by, for example, electrolytic plating, and the barrier layer 34 is formed on the barrier metal layer 33 in the bump forming openings 52A and 52B of the resist mask 51. A bump metal layer 350 to be a bump is formed in order (FIG. 6D). Here, a 5 to 6 μm Ni film is formed as the barrier layer 34, and a 0.35 to 0.50 μm Cu film and a 6 to 7 μm Sn film are sequentially formed as the bump metal layer 350. At this time, the plating processing time is controlled so that the film thickness of the barrier layer 34 and the bump metal layer 350 becomes a predetermined thickness. In this embodiment, the bump metal layer 350 to be formed is thinner than the bump forming openings 52A and 52B.

その後、アッシングなどによってレジストマスク５１を除去し（図６（ｅ））、バンプ用金属層３５０をマスクとして、エッチング法によってバンプ用金属層３５０が形成されていない領域のバリアメタル層３３を除去する（図７（ａ））。   Thereafter, the resist mask 51 is removed by ashing or the like (FIG. 6E), and the barrier metal layer 33 in a region where the bump metal layer 350 is not formed is removed by an etching method using the bump metal layer 350 as a mask. (FIG. 7A).

ついで、バンプ用金属層３５０を被覆するように図示しないフラックスを塗布し、窒素リフロー炉で熱処理しバンプ用金属層３５０を溶融してバンプ３５１，３５２を形成する（図７（ｂ））。その後、フラックスをたとえばグリコールエーテル系の有機溶剤で除去することで、基板１０１の主面上に形成されたすべてのバンプ３５１，３５２の高さが揃った電子部品を得ることができる。   Next, a flux (not shown) is applied so as to cover the bump metal layer 350 and heat-treated in a nitrogen reflow furnace to melt the bump metal layer 350 to form bumps 351 and 352 (FIG. 7B). Thereafter, by removing the flux with, for example, a glycol ether organic solvent, it is possible to obtain an electronic component in which all the bumps 351 and 352 formed on the main surface of the substrate 101 have the same height.

その後は、たとえば基板１０１をダイサーでダイシングしてデバイスチップとし、配線基板または他の電子部品と重ねて、加熱しながら圧力を加えることで、フリップチップ接続された電子部品が得られる。   After that, for example, the substrate 101 is diced with a dicer to form a device chip, and is superimposed on the wiring board or other electronic components, and pressure is applied while heating to obtain flip-chip connected electronic components.

なお、上述した説明では、バリア層３４を電解メッキ法によってレジストマスク５１のバンプ形成用開口部５２Ａ，５２Ｂ内に形成したが、バリアメタル層３３を形成した直後でレジストマスク５１を形成する前に、スパッタ法や蒸着法などの方法でバリア層３４をバリアメタル層３３上に形成してもよい。   In the above description, the barrier layer 34 is formed in the bump forming openings 52A and 52B of the resist mask 51 by electrolytic plating, but immediately after the barrier metal layer 33 is formed and before the resist mask 51 is formed. Alternatively, the barrier layer 34 may be formed on the barrier metal layer 33 by a method such as sputtering or vapor deposition.

さらに、上述した説明では、積層型半導体装置を構成する半導体素子（半導体チップ）を電子部品として例に挙げて説明したが、本発明はこれに限定されるものではなく、メッキ形成されたバンプ用金属層３５０をリフロー処理してバンプ３５を形成する構造の電子部品全般に本発明を適用することができる。   Furthermore, in the above description, the semiconductor element (semiconductor chip) constituting the stacked semiconductor device has been described as an example of an electronic component. However, the present invention is not limited to this, and for bumps formed by plating. The present invention can be applied to all electronic components having a structure in which the bump 35 is formed by reflowing the metal layer 350.

また、上述した説明では、バンプ形成用開口部の径を２段階とした場合を示したが、３段階以上としてもよい。   Further, in the above description, the case where the bump forming opening has a two-stage diameter is shown, but three or more stages may be used.

この実施の形態によれば、疎の配置形態を有する第２のバンプ形成用開口部５２Ｂの開口径ｒ２を、密の配置形態を有する第１のバンプ形成用開口部５２Ａの開口径ｒ１よりも小さくして、メッキ処理によってバンプ用金属層３５０を形成した。これによって、従来では、電界が強くかかる疎の配置形態を有するバンプ形成用開口部で、他の位置よりもバンプ用金属層３５０が厚く形成されてしまうことによって発生していたリフロー処理後のバンプの高さのばらつきを抑えることができる。つまり、電子部品にバンプ３５を形成する際のプロセスに由来するバンプ３５の高さの違いを解消でき、配線基板や他の電子部品との接続において良好なロバスト性を提供できるという効果を有する。また、バンプ用金属層３５０をリフロー処理してバンプ３５とする際に、バンプ３５の横方向への広がりを抑えることができるので、電子部品の微細化にも効果がある。   According to this embodiment, the opening diameter r2 of the second bump forming opening 52B having the sparse arrangement form is made larger than the opening diameter r1 of the first bump forming opening 52A having the dense arrangement form. The bump metal layer 350 was formed by plating to reduce the size. As a result, bumps after reflow processing, which has conventionally been generated by forming bump metal layers 350 thicker than other positions in bump forming openings having a sparse arrangement form with a strong electric field, are formed. Variation in height can be suppressed. That is, it is possible to eliminate the difference in height of the bumps 35 resulting from the process of forming the bumps 35 on the electronic component, and to provide good robustness in connection with the wiring board and other electronic components. Further, when the bump metal layer 350 is reflow-processed to form the bumps 35, the spread of the bumps 35 in the lateral direction can be suppressed, which is effective in miniaturizing electronic components.

１…積層型半導体装置、１０…配線基板、１１…接続パッド、１２…外部接続端子、１３…配線網、２０…第１の半導体素子、２１…電極パッド、２１Ａ…第１のパッド群、２１Ｂ…第２のパッド群、３０…第２の半導体素子、３１…パッド、３２…パッシベーション膜、３３…バリアメタル層、３４…バリア層、３５…バンプ、４１…接着剤層、４２…導電性ワイヤ、４３…樹脂、４４…封止樹脂、５１…レジストマスク、５２Ａ…第１のバンプ形成用開口部、５２Ｂ…第２のバンプ形成用開口部、１０１…基板、３５０…バンプ用金属層、３５１…第１のバンプ、３５２…第２のバンプ。   DESCRIPTION OF SYMBOLS 1 ... Stacked-type semiconductor device, 10 ... Wiring board, 11 ... Connection pad, 12 ... External connection terminal, 13 ... Wiring network, 20 ... 1st semiconductor element, 21 ... Electrode pad, 21A ... 1st pad group, 21B 2nd pad group, 30 ... 2nd semiconductor element, 31 ... Pad, 32 ... Passivation film, 33 ... Barrier metal layer, 34 ... Barrier layer, 35 ... Bump, 41 ... Adhesive layer, 42 ... Conductive wire 43 ... Resin, 44 ... Sealing resin, 51 ... Resist mask, 52A ... First bump forming opening, 52B ... Second bump forming opening, 101 ... Substrate, 350 ... Bump metal layer, 351 ... first bump, 352 ... second bump.

Claims (5)

配線基板または他の電子部品との間で導電性バンプを介して接続される電子部品の製造方法において、
導電性材料からなるパッドと、前記パッドの形成位置以外を覆うパッシベーション膜と、が形成された電子部品の主面上に、金属層を形成する第１の工程と、
前記金属層上にレジストを塗布し、リソグラフィ法によって前記パッドの形成位置に対応する開口部を形成する第２の工程と、
メッキ法によって、前記開口部内の前記金属層上にバンプ用金属層を形成する第３の工程と、
前記レジストを除去する第４の工程と、
前記バンプ用金属層をマスクとして、エッチング法によって前記金属層を除去する第５の工程と、
リフロー処理によって、前記バンプ用金属層をリフローさせてバンプを形成する第６の工程と、
を含み、
前記第２の工程では、周囲に他のバンプが均等に配置されている第１のバンプ形成位置での前記開口部の径よりも、周囲に他のバンプが均等に配置されていない第２のバンプ形成位置での前記開口部の径を小さく形成し、
前記第３の工程では、前記第２の工程で形成される開口部の径未満の厚さで前記バンプ用金属層を形成することを特徴とする電子部品の製造方法。 In a method for manufacturing an electronic component connected to a wiring board or other electronic component via a conductive bump,
A first step of forming a metal layer on a main surface of an electronic component on which a pad made of a conductive material and a passivation film covering a portion other than the pad formation position are formed;
A second step of applying a resist on the metal layer and forming an opening corresponding to the formation position of the pad by lithography;
A third step of forming a bump metal layer on the metal layer in the opening by plating;
A fourth step of removing the resist;
A fifth step of removing the metal layer by etching using the bump metal layer as a mask;
A sixth step of forming a bump by reflowing the bump metal layer by a reflow process;
Including
In the second step, the second bump in which the other bumps are not evenly arranged around the diameter of the opening at the first bump formation position where the other bumps are uniformly arranged around the second step. Form a small diameter of the opening at the bump formation position,
In the third step, the bump metal layer is formed with a thickness less than the diameter of the opening formed in the second step. 前記バンプが所定の間隔で二次元的に配置されているバンプ群を構成する場合に、前記第２の工程では、最外周のバンプ形成位置を前記第２のバンプ形成位置とし、最外周以外のバンプ形成位置を前記第１のバンプ形成位置として、前記開口部を形成することを特徴とする請求項１に記載の電子部品の製造方法。   In the case of configuring a bump group in which the bumps are two-dimensionally arranged at a predetermined interval, in the second step, the outermost bump formation position is set as the second bump formation position, and other than the outermost periphery. The method of manufacturing an electronic component according to claim 1, wherein the opening is formed with a bump forming position as the first bump forming position. 前記バンプが１列または２列に所定の間隔で一方向に配置されているバンプ群を構成する場合に、前記第２の工程では、前記１列または２列に配置されるバンプ形成位置を前記第２のバンプ形成位置として、前記開口部を形成することを特徴とする請求項１または２に記載の電子部品の製造方法。   In the case of configuring a bump group in which the bumps are arranged in one direction at predetermined intervals in one or two rows, in the second step, the bump forming positions arranged in the one or two rows are The method of manufacturing an electronic component according to claim 1, wherein the opening is formed as a second bump formation position. 配線基板または他の電子部品との間で導電性バンプを介して接続される電子部品の製造方法において、
中央部に二次元的に配置された第１のバンプ形成領域および周縁部に列状に配置された第２のバンプ形成領域に導電性材料からなるパッドを有し、前記パッドの形成位置以外を覆うようにパッシベーション膜が形成されてなる電子部品の主面上に、金属層を形成する第１の工程と、
前記金属層上にレジストを塗布し、リソグラフィ法によって前記パッドの形成位置に対応する開口部を形成する第２の工程と、
メッキ法によって、前記開口部内の前記金属層上にバンプ用金属層を形成する第３の工程と、
前記レジストを除去する第４の工程と、
前記バンプ用金属層をマスクとして、エッチング法によって前記金属層を除去する第５の工程と、
リフロー処理によって、前記バンプ用金属層をリフローさせてバンプを形成する第６の工程と、
を含み、
前記第２の工程では、前記第２のバンプ形成領域での前記開口部の径を、前記第１のバンプ形成領域の少なくとも一部の前記開口部の径よりも小さく形成し、
前記第３の工程では、前記第２の工程で形成される開口部の径未満の厚さで、前記バンプ用金属層を形成することを特徴とする電子部品の製造方法。 In a method for manufacturing an electronic component connected to a wiring board or other electronic component via a conductive bump,
The first bump formation region arranged two-dimensionally in the central portion and the second bump formation region arranged in a row at the peripheral portion have pads made of a conductive material, A first step of forming a metal layer on a main surface of an electronic component in which a passivation film is formed so as to cover;
A second step of applying a resist on the metal layer and forming an opening corresponding to the formation position of the pad by lithography;
A third step of forming a bump metal layer on the metal layer in the opening by plating;
A fourth step of removing the resist;
A fifth step of removing the metal layer by etching using the bump metal layer as a mask;
A sixth step of forming a bump by reflowing the bump metal layer by a reflow process;
Including
In the second step, the diameter of the opening in the second bump formation region is smaller than the diameter of the opening in at least part of the first bump formation region,
In the third step, the bump metal layer is formed with a thickness less than the diameter of the opening formed in the second step. 所定の機能を有するように素子がチップ上に形成された電子部品において、
一方の主面の中央部に二次元的に配置された第１のバンプ形成領域と、前記主面の周縁部に列状に配置された第２のバンプ形成領域と、に形成された導電性材料からなるパッドと、
前記パッドの形成位置以外を覆うように前記主面上に形成されたパッシベーション膜と、
前記パッド上に形成された金属層と、
前記金属層上にメッキ形成された導電性材料からなるバンプと、
を備え、
前記第２のバンプ形成領域での前記金属層の径は、前記第１のバンプ形成領域の少なくとも一部の前記金属層の径よりも小さいことを特徴とする電子部品。 In an electronic component in which an element is formed on a chip so as to have a predetermined function,
Conductivity formed in a first bump formation region that is two-dimensionally arranged at the center of one main surface and a second bump formation region that is arranged in a row at the peripheral edge of the main surface A pad made of material,
A passivation film formed on the main surface so as to cover other than the pad formation position;
A metal layer formed on the pad;
A bump made of a conductive material plated on the metal layer;
With
The diameter of the said metal layer in a said 2nd bump formation area is smaller than the diameter of the said metal layer of the at least one part of a said 1st bump formation area, The electronic component characterized by the above-mentioned.
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