KR102218736B1 - Bump structure, method of manufacturing the same and semiconductor package inclunding the same - Google Patents

Abstract

In the bump structure, the bump structure is provided on the pad of the substrate, has a columnar shape, and surrounds the sidewall of the body portion and includes a second metal different from the first metal. Include. The bump structure according to exemplary embodiments may have a fine pitch, which is advantageous for high integration of a semiconductor device. In addition, by coating the side wall of the body part with the support part, the body part can maintain the columnar shape. Since the body portion mainly contains pure tin, even when the semiconductor package is subjected to thermal and mechanical stress, the stresses can be flexibly buffered.

Description

A bump structure, a method for manufacturing the same, and a semiconductor package including the same TECHNICAL FIELD [Bump STRUCTURE, METHOD OF MANUFACTURING THE SAME AND SEMICONDUCTOR PACKAGE INCLUNDING THE SAME}

The present invention relates to a bump structure and a method of manufacturing the same. More specifically, the present invention relates to a bump structure included in a stacked semiconductor package and a method of manufacturing the same.

In order to implement high density chip stacking, a package on package (POP) technology has been proposed in which another package is stacked on a package in which a plurality of semiconductor chips are stacked. The package-on-package technology may provide an advantage of reducing a defect rate by stacking packages of good products that have already been tested.

As semiconductor packages become highly integrated, bump structures included in semiconductor packages must be formed with a fine pitch and at the same time have an appropriate height for electrically connecting stacked semiconductor packages. In addition, bump structures included in the semiconductor package must have properties capable of mitigating thermal and mechanical stress applied to the semiconductor package.

An object of the present invention is to provide a bump structure having fine pitch and stress buffering properties.

Another object of the present invention is to provide a semiconductor package including a bump structure having fine pitch and stress buffering properties.

Another object of the present invention is to provide a method for manufacturing the above-described bump structure.

However, the problem to be solved of the present invention is not limited to the above-mentioned problems, and may be variously extended without departing from the spirit and scope of the present invention.

In order to achieve one object of the present invention, the bump structure according to exemplary embodiments is provided on a pad of a substrate, has a columnar shape, and surrounds a body portion including a first metal, and a sidewall of the body portion, and the It includes a support including a second metal different from the first metal.

In example embodiments, the second metal of the support may include nickel (Ni).

In example embodiments, the thickness of the support may be within a range of 1 μm to 10 μm.

In example embodiments, the body portion may have a cylindrical shape.

In example embodiments, an under bump metallization (UBM) pattern layer formed directly on the pad may be further included, and the body portion may be provided on the UBM pattern layer.

In order to achieve another object of the present invention, a stacked package according to exemplary embodiments includes a first semiconductor package including a first substrate and at least one first semiconductor chip mounted on the first substrate, and the first A second semiconductor package stacked on a semiconductor package and including a second substrate and at least one second semiconductor chip mounted on the second substrate, and the second semiconductor package disposed between the first and second semiconductor packages The first and second semiconductor packages are electrically connected to each other, have a columnar shape, and surround a body portion including a first metal and a sidewall of the body portion and include a support portion including a second metal different from the first metal. May include bump structures.

In order to achieve another object of the present invention, in the method of forming the bump structure according to exemplary embodiments, the body portion is formed in a columnar shape on the pad of the first substrate. Each support part is coated on the sidewalls of the body to form a bump structure.

In example embodiments, an under bump metallization (UBM) pattern layer may be further formed on the pad. The pillar-shaped body portion may be formed on the UBM pattern layer.

In example embodiments, forming the body portion in a columnar shape on the pad of the first substrate may be formed using an electroplating process.

In example embodiments, forming a bump structure by coating each of the support portions on the sidewalls of the body portion may include coating the support portions using an electroless plating process.

The stacked package according to the invention configured as described above may include bump structures formed with fine pitches. In addition, the bump structures may have a fine pitch and at the same time have a height for electrically connecting the stacked semiconductor packages.

The stacked semiconductor packages are subjected to thermal and mechanical stress during operation, and bump structures according to exemplary embodiments may have a property of buffering thermal and mechanical stress applied to the semiconductor packages. Accordingly, operation reliability of the semiconductor package can be improved.

However, the effects of the present invention are not limited to the above-mentioned effects, and may be variously extended without departing from the spirit and scope of the present invention.

1 is a cross-sectional view illustrating a stacked package according to example embodiments.
2 is a cross-sectional view illustrating a bump according to exemplary embodiments.
3 is a plan view showing the bump of FIG. 2.
4 to 17 are cross-sectional views illustrating a method of manufacturing a stacked package according to exemplary embodiments.

With respect to the embodiments of the present invention disclosed in the text, specific structural or functional descriptions have been exemplified only for the purpose of describing the embodiments of the present invention, and the embodiments of the present invention may be implemented in various forms. It should not be construed as being limited to the embodiments described in.

Since the present invention can apply various changes and have various forms, specific embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to a specific form of disclosure, it is to be understood as including all changes, equivalents, or substitutes included in the spirit and scope of the present invention.

Terms such as first and second may be used to describe various elements, but the elements should not be limited by the terms. The terms may be used for the purpose of distinguishing one component from another component. For example, without departing from the scope of the present invention, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component.

When a component is referred to as being "connected" or "connected" to another component, it is understood that it may be directly connected or connected to the other component, but other components may exist in the middle. Should be. On the other hand, when a component is referred to as being "directly connected" or "directly connected" to another component, it should be understood that there is no other component in the middle. Other expressions describing the relationship between components, such as "between" and "just between" or "adjacent to" and "directly adjacent to" should be interpreted as well.

The terms used in the present application are only used to describe specific embodiments, and are not intended to limit the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In the present application, terms such as "comprise" or "have" are intended to designate the presence of a set feature, number, step, action, component, part, or combination thereof, and one or more other features or numbers It is to be understood that the possibility of addition or presence of, steps, actions, components, parts, or combinations thereof is not preliminarily excluded.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. Terms as defined in a commonly used dictionary should be interpreted as having a meaning consistent with the meaning of the context of the related technology, and should not be interpreted as an ideal or excessively formal meaning unless explicitly defined in this application. .

Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the accompanying drawings. The same reference numerals are used for the same elements in the drawings, and duplicate descriptions for the same elements are omitted.

1 is a cross-sectional view illustrating a stacked package according to example embodiments. 2 is a cross-sectional view illustrating a bump according to exemplary embodiments. 3 is a plan view showing the bump of FIG. 2. FIG. 2 is an enlarged view of area A of FIG. 1.

1 to 3, the stacked package 1 may include a first semiconductor package 10, a second semiconductor package 20, and bump structures 140.

The first semiconductor package 10 may include a first substrate 100 and a first semiconductor chip 110. The first semiconductor package 10 may further include a first molding member 160.

The first substrate 100 may be, for example, a printed circuit board (PCB), and may include first and second pads 120 and 130. Although not shown, the first substrate 100 may further include various wires electrically connected to the first and second pads 120 and 130.

In example embodiments, a plurality of first pads 120 may be formed on the upper surface 102 of the first substrate 100 so as to be spaced apart from the first semiconductor chip 110. The second pads 130 may be formed in plural under the first substrate 100. The first and second pads 120 and 130 may include a conductive material, for example, a metal.

The first semiconductor chip 110 may be mounted on the first substrate 100, for example, may be mounted on the central upper surface 102 of the first substrate 100.

In example embodiments, the first semiconductor chip 110 may be adhered to the upper surface 102 of the first substrate by conductive bumps 115. The conductive bumps 115 may include, for example, solder balls. Alternatively, the first semiconductor chip 110 may be adhered to the first substrate 100 through an adhesive layer (not shown).

The first semiconductor chip 110 may include, for example, an application processor (AP) chip, a logic chip, or the like.

The first molding member 160 may include, for example, an insulating material such as epoxy molding compound (EMC).

The first molding member 160 may be formed on the first substrate 100 to cover the upper surface 112, sidewall and lower surface 114 of the first semiconductor chip 110. In example embodiments, the top surface 112 of the first semiconductor chip 110 may be exposed to the outside.

The top surfaces of the first pads 120 may contact the bump structures 140. Some of the bump structures 140 may protrude above the upper surface of the first molding member 160, and thus may have a height higher than the upper surface of the first molding member 160. The bump structures 140 may be disposed between the first and second semiconductor packages to electrically connect the first and second semiconductor packages.

As shown in FIGS. 2 to 3, each bump structure 140 may include a body part 142 having a columnar shape and a support part 144 formed on a sidewall of the bump structure 140. Each bump structure 140 may be provided on the under bump metallization (UBM) pattern layer 150. For example, the body portion may be solder.

In example embodiments, the UBM pattern layer 150 may be provided on the first pad 120 and the protective layer pattern 162. The protective layer pattern 162 may be provided on the first substrate 100 and a portion of the first pad. The protective layer pattern 162 may be patterned to protect the first substrate 100 from an external environment and expose a part of the first pad 120. For example, the protective layer pattern 162 may include a material such as silicon nitride.

In example embodiments, the UBM pattern layer 150 may include an adhesive layer pattern 152, a barrier layer pattern 154, and a wet layer pattern 156.

The adhesive layer pattern 152 may be provided on a part of the protective layer pattern 162 and the first pad 120. The adhesive layer pattern 152 allows the bump structure 140 to be adhered to the first pad 120. For example, the adhesive layer pattern 152 may include titanium or the like.

The barrier layer pattern 154 may be provided on the protective layer pattern 162. The barrier layer pattern 154 may prevent the body portion 142 from spreading to the first pad 120. For example, the barrier layer pattern 154 may include molybdenum or the like.

The wet layer pattern 156 may be provided on the barrier layer pattern 154. The wet layer pattern 156 allows the body portion 142 to spread evenly and contact the upper surface of the wet layer pattern without gap. For example, the wet layer pattern 156 may include nickel, gold, copper, cobalt, or the like.

The body portion 142 may be provided on the wet layer pattern 156. In example embodiments, the body portion 142 may have a columnar shape. For example, the body portion 142 may have a cylindrical shape or a square column shape. In addition, the body portion 142 may include a first metal. For example, the body portion 142 may include pure tin (Sn) or the like.

1 to 3 illustrate that the UBM pattern layer 150 includes an adhesive layer pattern 152, a barrier layer pattern 154, and a wet layer pattern 156 as an example, but is not limited thereto. . For example, the UBM pattern layer 150 may have only the adhesive layer pattern 152 and the wet layer pattern 156. In addition, the UBM pattern layer 150 may have only the adhesive layer pattern 152 and the barrier layer pattern 154.

The support part 144 may be provided on the sidewall of the body part 142. In addition, the support part 144 may include a second metal. For example, the support 144 may include nickel or the like. In addition, the thickness of the support part 144 may be within the range of 1um to 10um.

Referring back to FIG. 1, the second semiconductor package 20 may include a second substrate 200 and a second semiconductor chip 210. The second semiconductor package 20 may further include a second molding member 260.

The second substrate 200 may be, for example, a printed circuit board (PCB), and may include third and fourth pads 220 and 230. Although not shown, the second substrate 200 may further include various wires electrically connected to the third and fourth pads 220 and 230.

In example embodiments, a plurality of fourth pads 230 may be formed on the lower surface 204 of the second substrate 200, respectively. In this case, the fourth pads 230 may be formed at positions corresponding to the first pads 120 of the first substrate 100, respectively, and may contact the bump structures 140, respectively. A plurality of third pads 220 may be formed on the upper surface 202 of the second substrate 200. The third and fourth pads 220 and 230 may include a conductive material, for example, a metal.

The bump structures 140 on the first pads 120 on the first substrate 100 and the fourth pads on the lower surface 204 of the second substrate 200 in contact with the bump structures 140 ( By 230, the first and second semiconductor packages 10 and 20 may be electrically connected to each other.

The second semiconductor chip 210 may be mounted on the second substrate 200, for example, may be mounted on the central upper surface 202 of the second substrate 200. In example embodiments, the second semiconductor chip 210 may be adhered to the upper surface 202 of the second substrate through the adhesive layer 270. Alternatively, the second semiconductor chip 210 may be adhered to the upper surface 202 of the second substrate 200 through a conductive bump (not shown) such as a solder ball.

The second semiconductor chip 210 may include a fifth pad 250 formed thereon. In example embodiments, a plurality of fifth pads 250 may be formed. The fifth pad 250 may include a conductive material, for example, a metal.

Each of the fifth pads 250 of the second semiconductor chip 210 and each of the third pads 220 of the second substrate 200 may be electrically connected to each other by a conductive wire 240. However, when the second semiconductor chip 210 is adhered to the second substrate 200 by the conductive bumps, the conductive wire 240 may not be formed.

The second semiconductor chip 210 may include, for example, a memory chip.

The second molding member 260 may include, for example, an insulating material such as epoxy molding compound (EMC). The second molding member 260 may be formed on the second substrate 200 to seal the second semiconductor chip 210, the adhesive layer 270 and the conductive wires 240, thereby protecting them from the external environment. Can be.

1 illustrates that the second semiconductor package 20 has only one second semiconductor chip 210, but is not limited thereto, and the second semiconductor package 20 is a plurality of sequentially stacked It may include four semiconductor chips.

Also, as an example, the first semiconductor package 10 is illustrated to have only one first semiconductor chip 110, but is not limited thereto, and the first semiconductor package 10 is a plurality of sequentially stacked It may also include semiconductor chips.

In addition, although FIG. 1 illustrates that the stacked package has only two semiconductor packages 10 and 20, it is not necessarily limited thereto, and may include three or more semiconductor packages sequentially stacked.

Meanwhile, external connection members (not shown) may be formed on the second pads 130 formed under the first substrate 100, and may be electrically connected to a main board (not shown) through this.

In exemplary embodiments, the external connection members are also supported on the sidewalls of the body portion 142 and the body portion 142 having a columnar shape like the bump structure 140 according to the exemplary embodiments. ) May be provided.

Since each bump structure 140 included in the semiconductor package according to the exemplary embodiments has a pillar shape instead of a conventional spherical or elliptical shape, even when the height of the bump structure 140 increases, There is no problem of a short circuit with the bump structure 140. In addition, since the bump structure 140 can be formed with a fine pitch, it is advantageous for high integration of a semiconductor package.

In addition, since the conventional bump structure 140 having a pillar shape mainly contains copper (Cu), it does not have the property of buffering thermal and mechanical stress received by the semiconductor package, which lowers the operational reliability of the semiconductor package. Became. The bump structure 140 according to exemplary embodiments may have a columnar shape and mainly include solder, so that thermal and mechanical stresses received by the semiconductor package may be buffered. Accordingly, operation reliability of the semiconductor package can be secured.

Hereinafter, a method of manufacturing the laminated package of FIG. 1 will be described.

4 to 17 are diagrams illustrating a method of manufacturing a stacked package according to exemplary embodiments.

Referring to FIG. 4, a protective layer pattern 162 may be formed on a first substrate 100 including first and second pads 120 and 130. The protective layer pattern 162 may be formed by first forming a protective layer (not shown) on the first substrate 100 and then patterning to expose a portion of the first pad 120. The protective layer pattern 162 may protect the first substrate 100 from an external environment. For example, the protective layer pattern 162 may be patterned using a laser drill or a mechanical drill on the protective layer.

For example, the first substrate 100 may be a printed circuit board (PCB). A plurality of first pads 120 may be formed on the upper surface 102 of the first substrate 100 so as to be spaced apart from the first semiconductor chip 110. The first pads 120 may be arranged on the first substrate 100 at regular intervals. A plurality of second pads 130 may be formed on the lower surface 104 of the first substrate 100. The first and second pads 120 and 130 may include a conductive material, for example, a metal.

Referring to FIG. 5, an adhesive layer 166 and a barrier layer 168 may be sequentially formed on a part of the protective layer pattern 162 and the first pad 120.

In example embodiments, the adhesive layer 166 and the barrier layer 168 are a chemical vapor deposition (CVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, and an atomic layer deposition. It can be formed through (Atomic Layer Deposition: ALD) process.

For example, the adhesive layer 166 may be formed using a metal such as titanium. The barrier layer 168 may be formed using a metal such as molybdenum. The adhesive layer 166 provides adhesive force so that the first pad 120 and the bump structure 140 are adhered. When the body part 142 is melted, the barrier layer 168 may prevent diffusion into the first pad 120 and the first substrate 100.

Referring to FIG. 6, a blocking layer 170 may be formed on the barrier layer 168. In example embodiments, the blocking layer 170 may be a photoresist layer or a hard mask layer.

For example, the hard mask film may be formed using silicon nitride.

Referring to FIG. 7, first openings 182 for exposing a part of the barrier layer 168 corresponding to the first pad 120 in a direction substantially perpendicular to the upper surface of the substrate by removing a part of the blocking layer 170. ) Can be formed. In addition, by removing a part of the blocking layer 170, the blocking layer 170 may be converted into the blocking layer pattern 172.

For example, when the blocking layer 170 is a photoresist layer, patterning may be performed through a developing process.

Referring to FIG. 8, a wet layer pattern 156 may be formed on a portion of the barrier layer 168 exposed by the first openings 182.

For example, the wet layer pattern 156 may be formed through a plasma chemical vapor deposition (PECVD) process, which is an anisotropic deposition method. In addition, the wet layer pattern 156 may be formed to include nickel, gold, copper, or cobalt. The wet layer pattern 156 allows the body portion 142 to be described later to be spread evenly and contact with the upper surface of the wet layer pattern 156 without gap.

Referring to FIG. 9, a body portion 142 having a columnar shape may be formed on the wet layer pattern 156.

Specifically, after forming a solder layer (not shown) sufficiently filling the first openings 182 on the blocking layer pattern 172, the solder layer is formed until the upper surface of the blocking layer pattern 172 is exposed. By flattening, a plurality of body portions 142 filling the first openings 182 may be formed.

In example embodiments, the body portion 142 may be formed on the wet layer pattern 156 while having a columnar shape using an electroplating process.

In the case of the conventional reflow process, a spherical or elliptical body portion 142 may be formed, whereas the body portion 142 according to exemplary embodiments may have a columnar shape.

Accordingly, in the case of the body portion 142 having a columnar shape, the possibility of a short circuit with another body portion 142 adjacent to it is reduced. In addition, the body portion 142 having a columnar shape may have a height for connecting semiconductor packages.

Referring to FIG. 10, second openings 184 exposing part of the barrier layer 168 may be formed by removing the formed blocking layer pattern 172. For example, the blocking layer pattern 172 may be removed by an ashing and/or strip process.

Referring to FIG. 11, a portion of the protective layer pattern 162 may be exposed by removing a portion of the barrier layer 168 and the adhesive layer 166 exposed by the second openings 184.

As the barrier layer 168 and the adhesive layer 166 are partially removed, the barrier layer 168 and the adhesive layer 166 may be converted into the barrier layer pattern 154 and the adhesive layer pattern 152.

For example, some of the barrier layer 168 and the adhesive layer 166 may be removed by a plasma ion sputtering process.

Referring to FIG. 12, on the upper surface and sidewall of the body portion 142, the wet layer pattern 156, the barrier layer pattern 154, and the sidewall of the adhesive layer pattern 152, and the upper surface of the protective layer pattern 152. A metal layer 146 may be formed.

The metal layer 146 may be formed using an electrodeless plating process. The electroless plating process has the advantage of forming a metal layer with a uniform thickness. For example, the metal layer 146 may be formed using nickel or the like.

Referring to FIG. 13, the upper portion of the metal layer 146 may be removed until the upper surface of the body portion 142 is exposed.

By removing the upper portion of the metal layer 146, the metal layer 146 may be converted into a support part 144. The upper portion of the metal layer 146 may be removed by mechanical polishing or laser. For example, the thickness of the support part 144 may be within the range of 1 um to 10 um.

By coating the support portion 144 on the sidewall of the body portion 142, the body portion 142 may be prevented from collapsing, and rigidity may be provided so that the body portion 142 may maintain a columnar shape.

Referring to FIG. 14, a part of the first substrate 100 is exposed by removing a part of the protective layer pattern 162. The first semiconductor chip 110 is mounted on the exposed first substrate 100.

For example, in order to remove a part of the protective layer pattern 162, an etching mask (not shown) on a part of the protective layer pattern 162, the sidewalls and upper surfaces of the support part 144, and the upper surface of the body part 142 Not). The etching mask may be patterned, and a portion of the protective layer pattern 162 exposed by the etching mask may be etched to be removed. The process of removing a part of the protective layer pattern 162 by removing the patterned etching mask may be completed.

The first semiconductor chip 110 may be mounted on the first substrate 100 exposed by the conductive bumps 115. That is, for example, conductive bumps 115 including solder balls are disposed on the central upper surface 102 of the first substrate 100, and the lower surface 114 of the first semiconductor chip 110 is a conductive bump. The first semiconductor chip 110 is disposed above the central portion of the first substrate 100 so as to contact them 115, and then a reflow process is performed to transfer the conductive bumps 115 to the first semiconductor chip 110. ) It may be bonded to the lower surface 114 and the upper surface 102 of the first substrate.

Referring to FIG. 15, a first molding member 160 is formed on the first substrate 100 to cover a portion of the first semiconductor chip 110 and the bump structures 140. In this case, the first molding member 160 may be formed using, for example, an epoxy molding compound (EMC).

In example embodiments, the first molding member 160 may be formed so that a part of the bump structures 140 protrude above the upper surface of the first molding member 160.

In addition, external connection members (not shown) are adhered to the lower surface 104 of the first substrate 100, and the first substrate 100 is separated into a plurality of pieces through a sawing process and singulated. A first semiconductor package 10 is formed.

Meanwhile, a temporary adhesive (not shown) that covers the external connection members is attached to the lower surface 104 of the first substrate 100, and a carrier substrate (not shown) is attached to the temporary adhesive. , It may be individualized by performing a sawing process on the first substrate 100.

Referring to FIG. 16, a second semiconductor chip 210 is mounted on a second substrate 200, and the second substrate 200 and the second semiconductor chip 210 are electrically connected through a conductive wire 240. Then, a second molding member 260 for sealing the second semiconductor chip 210 and the conductive wire 240 is formed on the second substrate 200 to form the second semiconductor package 20.

The second substrate 200 may be, for example, a PCB substrate, and may include third and fourth pads 220 and 230. In example embodiments, a plurality of fourth pads 230 may be formed under the second substrate 200, respectively. In example embodiments, a plurality of third pads 220 may be formed on the second substrate 200. The third and fourth pads 220 and 230 may include a conductive material, for example, a metal.

The second semiconductor chip 210 forms an adhesive layer 270 on the upper surface 202 of the central portion of the second substrate 200, and then attaches the lower surface 214 of the second semiconductor chip 210 to the adhesive layer 270. By making contact, it can be mounted on the second substrate 200. The second semiconductor chip 210 may include a plurality of fifth pads 250 formed thereon. The fifth pad 250 may include a conductive material, for example, a metal.

The conductive wire 240 may be disposed to connect the fifth pads 250 of the second semiconductor chip 210 and the third pads 220 of the second substrate 200.

The second molding member 260 may be formed using, for example, an insulating material such as an epoxy molding compound (EMC).

Referring to FIG. 17, the second semiconductor package 20 is disposed above the first semiconductor package 10 and then bonded to each other to manufacture the stacked package.

Specifically, after bringing the fourth pads 230 formed under the second substrate 200 into contact with the bump structures 140 formed on the upper surface 102 of the first substrate, they are combined with each other through a reflow process. I can.

Thereafter, the carrier substrate and the temporary adhesive attached to the lower surface 104 of the first substrate 100 may be removed, and the external connection members may be mounted on a main board (not shown).

As described above, the stacked package according to the present invention includes a bump structure 140 having a columnar shape. Accordingly, even when the bump structure 140 increases to connect the semiconductor packages, the possibility of a short circuit with the other bump structures 140 is reduced. In addition, the bump structure 140 may have a fine pitch, which is advantageous for high integration of a semiconductor device.

By coating the sidewall of the body part 142 having a columnar shape with a support part 144 containing nickel, etc., the body part 142 can maintain the columnar shape and prevent the body part 142 from falling can do. In addition, even when the semiconductor package is subjected to thermal and mechanical stress, the body portion 142 may flexibly buffer the stresses. Accordingly, operation reliability of the semiconductor device can be maintained even under thermal and mechanical stress conditions.

1: stacked package 10: first semiconductor package
20: second semiconductor package 100: first substrate
110: first semiconductor chip 120: first pad
130: second pad 140: bump structure
142: body portion 144: support portion
150: UBM pattern film 160: first molding member
115: conductive bump 200: second substrate
210: second semiconductor chip 220: third pad
230: fourth pad 240: conductive wire
250: fifth pad 260: second molding member

Claims (10)

A first semiconductor package including a first substrate and at least one first semiconductor chip mounted on the first substrate;
A second semiconductor package stacked on the first semiconductor package and including a second substrate and at least one second semiconductor chip mounted on the second substrate; And
The first and second semiconductor packages are interposed between the first and second semiconductor packages to electrically connect the first and second semiconductor packages, have a columnar shape, and surround a body portion including a first metal and a sidewall of the body portion, Including a plurality of bump structures having a support including a second metal different from the 1 metal,
The body portion of the bump structure is provided on a pad formed on the upper surface of the first substrate, and the upper surface of the body portion is exposed to the outside by the support portion to contact the pad formed on the lower surface of the second substrate,
The stacked package, characterized in that the upper surface of the body portion and the upper surface of the support portion are located on the same plane. The stacked package of claim 1, wherein the second metal of the support part comprises nickel (Ni). The laminate package of claim 2, wherein the thickness of the support portion is within the range of 1 um to 10 um. The laminate package of claim 1, wherein the body portion has a cylindrical shape. The method of claim 1, further comprising an UBM (Under Bump Metallization) pattern layer formed directly on the pad formed on the upper surface of the first substrate,
The stacked package, characterized in that the body portion is provided on the UBM pattern layer. A first semiconductor package including a first substrate and at least one first semiconductor chip mounted on the first substrate;
A second semiconductor package stacked on the first semiconductor package and including a second substrate and at least one second semiconductor chip mounted on the second substrate; And
The first and second semiconductor packages are interposed between the first and second semiconductor packages to electrically connect the first and second semiconductor packages, have a columnar shape, and surround a body portion including a first metal and a sidewall of the body portion. Including a plurality of bump structures having a support including a second metal different from the 1 metal,
The upper surface of the body part of the bump structure is exposed to the outside by the support part to contact the pad of the second substrate,
The stacked package, characterized in that the upper surface of the body portion and the upper surface of the support portion are located on the same plane. Forming a body portion in a columnar shape on the pad of the first substrate; And
Including the step of forming a bump structure by coating each support portion on the side wall of the body,
Forming the bump structure,
Coating the support part on the upper surface and the side wall of the body part by forming a metal layer using an electroless plating process; And
Forming the support part on the sidewall of the body part by removing the upper part of the metal layer until the upper surface of the body part is exposed,
The method of forming a bump structure, wherein the upper surface of the body part and the upper surface of the support part are located on the same plane. The method of claim 7,
Further comprising forming an under bump metallization (UBM) pattern layer on the pad,
The method of forming a bump structure, wherein the columnar body portion is formed on the UBM pattern layer. The method of claim 7,
The step of forming the body portion in a columnar shape on the pad of the first substrate is formed using an electroplating process. delete

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