JP2010251742A - 半導体デバイスとその形成方法(高k金属ゲートCMOS) - Google Patents
半導体デバイスとその形成方法(高k金属ゲートCMOS) Download PDFInfo
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- JP2010251742A JP2010251742A JP2010075677A JP2010075677A JP2010251742A JP 2010251742 A JP2010251742 A JP 2010251742A JP 2010075677 A JP2010075677 A JP 2010075677A JP 2010075677 A JP2010075677 A JP 2010075677A JP 2010251742 A JP2010251742 A JP 2010251742A
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/28158—Making the insulator
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- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
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Abstract
【解決手段】 基板のp型デバイス領域の上にGe含有層を形成することを含む、半導体デバイスを形成する方法が提供される。その後、基板の第2の部分内に第1の誘電体層が形成され、基板の第2の部分内の第1の誘電層及び基板の第1の部分の上を覆うように、第2の誘電体層が形成される。次に、基板のp型デバイス領域及びn型デバイス領域の上にゲート構造体を形成することができ、n型デバイス領域へのゲート構造体は希土類金属を含む。
【選択図】 図14
Description
本発明は、デバイス性能の改善された、低閾値電圧の相補型金属酸化膜半導体(CMOS)デバイスのためのゲート構造体を提供することを目的とする。
6:ハードマスク誘電体層
7:第1のエッチング・マスク
8:第2のエッチング・マスク
9:第3のエッチング・マスク
10:n型デバイス領域
13:分離領域
20:p型デバイス領域
30:Ge含有層
40:第1の誘電体層
50:基板の第1の部分
60:基板の第2の部分
70:第2の誘電体層
75:希土類金属層
80a、80b、80c、80d:ゲート構造体
85:ゲート金属層
90:ゲート電極
100:半導体デバイス
110a、110b:n型導電性デバイス
120a、120b:p型導電性デバイス
Claims (20)
- 第1のデバイス領域及び第2のデバイス領域を含む基板と、
少なくとも第1の高k誘電体と、前記第1の高k誘電体の上にある少なくとも1つの希土類金属とを有する第1のゲート構造体を含む、前記第1のデバイス領域内にあるn型導電性デバイスと、
第2の高k誘電体を有する第2のゲート構造体を含む、前記第2のデバイス領域内にあるp型導電性デバイスであって、デバイス・チャネルの上の前記第2のゲート構造体はGe含有層を含む、p型導電性デバイスと、
を含み、
前記第2の高k誘電体は前記第1の高k誘電体より大きい電荷を有する、
半導体デバイス。 - 前記第1の高k誘電体及び前記第2の高k誘電体の少なくとも一方は、HfO2、ZrOx、Al2O3、又はHfSiOxNyである、請求項1に記載の半導体デバイス。
- 前記第1の高k誘電体及び前記第2の高k誘電体の少なくとも一方は、窒化物含有層を含む、請求項1に記載の半導体デバイス。
- 前記第1のゲート構造体及び前記第2のゲート構造体は金属ゲート導体を含み、前記第1のゲート構造体の前記金属ゲート導体は、前記第2のゲート構造体の前記金属ゲート導体と実質的に同じ組成である、請求項1に記載の半導体デバイス。
- 前記ゲート導体はTiNを含む、請求項4に記載の半導体デバイス。
- 前記p型導電性デバイスは、前記Ge含有層からなる前記デバイス・チャネルの上を覆うSiキャップをさらに含む、請求項1に記載の半導体デバイス。
- 前記希土類金属は、La、Ce、Pr、Nd、Pm、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb、Lu、又はそれらの合金を含む、請求項1に記載の半導体デバイス。
- 前記Ge含有層はSiGeである、請求項1に記載の半導体デバイス。
- 各々が第1の厚さのゲート誘電体を含むゲート構造体を有する半導体デバイスからなる第1の部分と、各々が第2の厚さのゲート誘電体を含むゲート構造体を有する半導体デバイスからなる第2の部分とを含む基板であって、前記第2の厚さは前記第1の厚さより厚い、基板と、
前記基板の前記第1の部分及び前記第2の部分の各々の中に存在するn型デバイス領域であって、前記n型デバイス領域内に存在する前記半導体デバイスは少なくとも1つの希土類金属からなるゲート構造体を含む、n型デバイス領域と、
前記基板の前記第1の部分及び前記第2の部分の各々の中に存在するp型デバイス領域であって、前記p型デバイス領域内に存在する前記半導体デバイスはGe含有層を含むデバイス・チャネルを含む、p型デバイス領域と、
を含む半導体デバイス。 - 前記ゲート誘電体の前記第1の厚さは1nmから10nmまでの範囲であり、前記ゲート誘電体の前記第2の厚さは1nmから3nmまでの範囲である、請求項9に記載の半導体デバイス。
- 前記基板の前記第1の部分内に存在する前記半導体デバイスはアナログ・デバイスであり、前記基板の前記第2の部分内に存在する前記半導体デバイスはデジタル・デバイスである、請求項9に記載の半導体デバイス。
- 前記Ge含有層はSiGeである、請求項9に記載の半導体デバイス。
- 半導体デバイスを形成する方法であって、
p型デバイス領域及びn型デバイス領域を有する基板を準備するステップと、
前記基板のp型デバイス領域の上にGe含有層を形成するステップであって、前記Ge含有層は前記基板の前記n型デバイス領域内には存在しない、ステップと、
前記p型デバイス領域及び前記n型デバイス領域の上に第1の誘電体層を形成するステップと、
前記p型デバイス領域の少なくとも1つ及び前記n型デバイス領域の少なくとも1つを含む前記基板の第1の部分から前記第1の誘電体層を除去するステップであって、前記第1の誘電体層の残りの部分は前記基板の第2の部分内に存在する、ステップと、
前記基板の前記第1の部分内の前記第1の誘電体層及び前記基板の前記第2の部分の上を覆うように第2の誘電体層を形成するステップと、
前記p型デバイス領域及び前記n型デバイス領域の上にゲート構造体を形成するステップであって、前記n型デバイス領域への前記ゲート構造体は希土類金属を含む、ステップと、
を含む方法。 - p型デバイス領域及びn型デバイス領域を有する前記基板を準備する前記ステップは、前記p型デバイス領域及び前記n型デバイス領域の各々の上面にハードマスク誘電体層を形成するステップをさらに含む、請求項13に記載の方法。
- 前記基板の前記p型デバイス領域の上に前記Ge含有層を形成する前記ステップの前に、前記方法は、前記n型デバイス領域の上に前記p型デバイス領域を露出させるエッチング・マスクを形成するステップと、前記n型デバイス領域内のハードマスク誘電体層をエッチングして前記p型デバイス領域内の前記基板の上面を露出させるステップと、前記エッチング・マスクを除去するステップとをさらに含む、請求項13に記載の方法。
- 前記Ge含有層はSiGeからなる、請求項13に記載の方法。
- 前記p型デバイス領域及び前記n型デバイス領域の上に前記第1の誘電体層を形成する前記ステップは、前記n型デバイス領域からハードマスク誘電体層の残りの部分を除去するステップと、1nmから10nmまでの範囲の厚さを有する前記誘電体層を堆積させるステップとを含む、請求項16に記載の方法。
- 前記基板の前記第1の部分内の前記第1の誘電体層及び前記基板の前記第2の部分の上を覆うように第2の誘電体層を形成する前記ステップは、1nmから3nmまでの範囲の厚さを有する高k誘電体材料を堆積させるステップを含む、請求項17に記載の方法。
- 前記p型デバイス領域及び前記n型デバイス領域の上にゲート構造体を形成する前記ステップは、
前記高k誘電体材料の上に希土類金属を堆積させるステップと、
前記p型デバイス領域から前記希土類金属を除去するステップと、
前記n型デバイス領域内の前記希土類金属及び前記p型デバイス領域内の高k誘電体材料の上を覆うように金属窒化物層を形成するステップと、
前記金属窒化物層の上にSi含有層を形成するステップと、
を含む、請求項17に記載の方法。 - 前記基板の前記第1の部分内のアナログ・デバイスと、前記基板の前記第2の部分内のデジタル・デバイスとを含む、請求項17に記載の方法。
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KR101439599B1 (ko) | 2012-04-26 | 2014-09-11 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | 고유전율 및 금속 게이트 스택을 위한 장치 및 방법 |
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US20110156158A1 (en) | 2011-06-30 |
JP5583448B2 (ja) | 2014-09-03 |
CN101866924A (zh) | 2010-10-20 |
TW201108398A (en) | 2011-03-01 |
US7943460B2 (en) | 2011-05-17 |
US8507992B2 (en) | 2013-08-13 |
CN101866924B (zh) | 2013-01-16 |
US20100264495A1 (en) | 2010-10-21 |
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