JP2010232663A - チップモジュール並びにチップモジュールを製造する方法 - Google Patents
チップモジュール並びにチップモジュールを製造する方法 Download PDFInfo
- Publication number
- JP2010232663A JP2010232663A JP2010074638A JP2010074638A JP2010232663A JP 2010232663 A JP2010232663 A JP 2010232663A JP 2010074638 A JP2010074638 A JP 2010074638A JP 2010074638 A JP2010074638 A JP 2010074638A JP 2010232663 A JP2010232663 A JP 2010232663A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- substrate
- method step
- chip module
- carrier element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 71
- 238000000034 method Methods 0.000 claims abstract description 70
- 230000001154 acute effect Effects 0.000 claims abstract description 16
- 239000004020 conductor Substances 0.000 claims description 16
- 238000005219 brazing Methods 0.000 claims description 6
- 230000002411 adverse Effects 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 19
- 239000010408 film Substances 0.000 description 13
- 238000000465 moulding Methods 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 239000000853 adhesive Substances 0.000 description 4
- 230000001070 adhesive effect Effects 0.000 description 4
- 239000011247 coating layer Substances 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000011156 evaluation Methods 0.000 description 2
- 239000004033 plastic Substances 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 239000000805 composite resin Substances 0.000 description 1
- 238000000748 compression moulding Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/0032—Packages or encapsulation
- B81B7/0074—3D packaging, i.e. encapsulation containing one or several MEMS devices arranged in planes non-parallel to the mounting board
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R33/00—Arrangements or instruments for measuring magnetic variables
- G01R33/02—Measuring direction or magnitude of magnetic fields or magnetic flux
- G01R33/0206—Three-component magnetometers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C2203/00—Forming microstructural systems
- B81C2203/01—Packaging MEMS
- B81C2203/0154—Moulding a cap over the MEMS device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
【解決手段】基板がモールドケーシングを有するようにし、かつ、第1の方法ステップにおいて、予め構造化されたキャリアエレメントに少なくとも1つのチップ(3)を実装し、第2の方法ステップにおいて、チップ(3)に基板(2)を製造するモールド質量体を、前記基板の第1の主延在平面(2′)とチップの第2の主延在平面との間に鋭角(4)が形成されているように配置し、第3の方法ステップにおいて、基板(2)をチップ(3)と一緒にキャリアエレメントから剥離するようにした。
【選択図】図6
Description
Claims (10)
- 基板(2)と、該基板(2)に接続された少なくとも1つのチップ(3)とを備えたチップモジュール(1)であって、基板(2)は第1の主延在平面(2′)を有し、チップ(3)は第2の主延在平面(3′)を有し、第1の主延在平面(2′)と第2の主延在平面(3′)との間に鋭角(4)が形成されている、チップモジュール(1)において、
基板(2)はモールドケーシングを有していることを特徴とする、チップモジュール。 - チップ(3)及び/又はチップモジュール(1)はSMD構成部材を有しており、チップ(3)は特に接触面(5)を有しており、該接触面(5)はチップ(3)の基板(2)とは反対の側に配置されており、基板(2)は有利にはボンディングコンタクト(6)を有しており、該ボンディングコンタクト(6)はプリント配線板と特に有利には導電的に接続されていることを特徴とする、請求項1記載のチップモジュール。
- チップ(3)は少なくとも部分的に基板(2)内に埋設されており、特に接触面(5)は基板(2)に対して露出して設けられていることを特徴とする、請求項1又は2記載のチップモジュール。
- 基板(2)は少なくとも1つの別のチップ(30)を有しており、該別のチップ(30)の第3の主延在平面(30′)が第1の主延在平面(2)に対してほぼ平行に配向されていることを特徴とする、請求項1から3までのいずれか一項記載のチップモジュール。
- チップモジュール(1)は導体層(7)を有しており、該導体層(7)は特に基板(2)のチップ(3)を有する側に配置されており、かつ、接触面(5)とボンディングコンタクト(6)との間、及び/又は、接触面(5)と別のチップ(30)の別の接触面(50)との間に特に導電性接続部を有していることを特徴とする、請求項1から4までのいずれか一項記載のチップモジュール。
- 特に請求項1から5までのいずれか一項記載のチップモジュール(1)を製造する方法において、
第1の方法ステップにおいて、予め構造化されたキャリアエレメント(8)に少なくとも1つのチップ(3)を実装し、
第2の方法ステップにおいて、チップ(3)に基板(2)の製造のためのモールド質量体を、前記基板の第1の主延在平面(2′)とチップ(3)の第2の主延在平面(3′)との間に鋭角(4)が形成されているように配置し、
第3の方法ステップにおいて、基板(2)をチップ(3)と一緒にキャリアエレメント(8)から剥離する、
ことを特徴とする、チップモジュールを製造する方法。 - 時系列的に第1の方法ステップより先に実施する第0の方法ステップにおいて、キャリアエレメント(8)を、チップ(3)を実装したい表面領域(8″)が前記キャリアエレメントの第4の主延在平面(8′)に対して鋭角(4)を有するように予め構造化し、かつ/又は、第0の方法ステップにおいて、キャリアエレメント(8)の、チップ(3)を実装したい表面領域(8″)にフィルムをコーティングし、かつ/又は、第0の方法ステップにおいて、キャリアエレメント(8)を特にホットスタンピング加工により予め構造化されたフィルムから製造することを特徴とする、請求項6記載の方法。
- 第1の方法ステップにおいて、キャリアエレメント(8)に少なくとも1つの別のチップ(30)を実装し、有利には別のチップ(30)の第3の主延在平面(30′)が、第1及び/又は第4の主延在平面(2′,8′)に対してほぼ平行に配向されていることを特徴とする、請求項6又は7記載の方法。
- 第4の方法ステップにおいて、導体層(7)を基板(2)、チップ(3)及び/又は別のチップ(30)に配置し、かつ/又は、第5の方法ステップにおいて、基板(2)をプリント配線板にろう付するかつ/又は接着することを特徴とする、請求項6から8までのいずれか一項記載の方法。
- 第1の方法ステップにおいて、キャリアエレメント(8)に複数のチップ(3)及び/又は別のチップ(30)を実装し、かつ/又は、時系列的に特に第5の方法ステップより先に実施される第6の方法ステップにおいて、基板(2)を分割して複数のチップモジュール(1)に個別化することを特徴とする、請求項6から9までのいずれか一項記載の方法。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102009001932A DE102009001932A1 (de) | 2009-03-27 | 2009-03-27 | Chipmodul und Verfahren zur Herstellung eines Chipmoduls |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2010232663A true JP2010232663A (ja) | 2010-10-14 |
Family
ID=42663852
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2010074638A Pending JP2010232663A (ja) | 2009-03-27 | 2010-03-29 | チップモジュール並びにチップモジュールを製造する方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US8198130B2 (ja) |
JP (1) | JP2010232663A (ja) |
DE (1) | DE102009001932A1 (ja) |
IT (1) | IT1400084B1 (ja) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW201123377A (en) * | 2009-12-16 | 2011-07-01 | Raydium Semiconductor Corp | Electronic chip and substrate with void |
US8316552B1 (en) * | 2011-05-05 | 2012-11-27 | Honeywell International Inc. | Systems and methods for three-axis sensor chip packages |
CN102385043B (zh) * | 2011-08-30 | 2013-08-21 | 江苏多维科技有限公司 | Mtj三轴磁场传感器及其封装方法 |
JP2014209091A (ja) | 2013-03-25 | 2014-11-06 | ローム株式会社 | 半導体装置 |
EP2957881A1 (de) * | 2014-06-18 | 2015-12-23 | Technische Universität Darmstadt | Messaufnehmersystem, Messaufnehmerelement, Verfahren zur Herstellung des Messaufnehmerelements und Einlegteil mit dem Messaufnehmerelement |
DE102019205149A1 (de) | 2019-04-10 | 2020-10-15 | Robert Bosch Gmbh | Elektronisches Modul und Verfahren zu dessen Herstellung |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001290056A (ja) * | 2000-04-07 | 2001-10-19 | Seiko Epson Corp | プラットフォーム及び光モジュール並びにこれらの製造方法並びに光伝達装置 |
JP2002076185A (ja) * | 2000-08-25 | 2002-03-15 | Toshiba Corp | 回路基板装置及びその製造方法 |
JP2003318323A (ja) * | 2002-04-19 | 2003-11-07 | Casio Comput Co Ltd | 半導体装置およびその製造方法 |
JP2004006752A (ja) * | 2002-03-27 | 2004-01-08 | Yamaha Corp | 磁気センサおよびその製造方法 |
JP2006337069A (ja) * | 2005-05-31 | 2006-12-14 | Sanyo Electric Co Ltd | 回路装置およびその製造方法 |
JP2008216181A (ja) * | 2007-03-07 | 2008-09-18 | Citizen Holdings Co Ltd | 方位センサ及び電子機器 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE4106932A1 (de) * | 1991-03-05 | 1992-09-10 | Bosch Gmbh Robert | Neigungssensor |
DE10250321A1 (de) | 2001-12-14 | 2003-06-26 | Bosch Gmbh Robert | Verfahren und Anordnung zur Erfassung eines räumlichen Bewegungszustandes bewegter Objekte |
EP1892537B1 (en) * | 2002-07-29 | 2011-05-25 | Yamaha Corporation | Three-axis magnetic sensor |
JP4627632B2 (ja) * | 2004-05-17 | 2011-02-09 | Okiセミコンダクタ株式会社 | 半導体装置 |
US7595548B2 (en) * | 2004-10-08 | 2009-09-29 | Yamaha Corporation | Physical quantity sensor and manufacturing method therefor |
US20070152315A1 (en) * | 2006-01-03 | 2007-07-05 | Samsung Electronics Co.; Ltd | Multi-die package and method for fabricating same |
KR100997787B1 (ko) * | 2008-06-30 | 2010-12-02 | 주식회사 하이닉스반도체 | 적층 반도체 패키지 및 이의 제조 방법 |
-
2009
- 2009-03-27 DE DE102009001932A patent/DE102009001932A1/de not_active Ceased
-
2010
- 2010-03-11 US US12/721,785 patent/US8198130B2/en not_active Expired - Fee Related
- 2010-03-23 IT ITMI2010A000473A patent/IT1400084B1/it active
- 2010-03-29 JP JP2010074638A patent/JP2010232663A/ja active Pending
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001290056A (ja) * | 2000-04-07 | 2001-10-19 | Seiko Epson Corp | プラットフォーム及び光モジュール並びにこれらの製造方法並びに光伝達装置 |
JP2002076185A (ja) * | 2000-08-25 | 2002-03-15 | Toshiba Corp | 回路基板装置及びその製造方法 |
JP2004006752A (ja) * | 2002-03-27 | 2004-01-08 | Yamaha Corp | 磁気センサおよびその製造方法 |
JP2003318323A (ja) * | 2002-04-19 | 2003-11-07 | Casio Comput Co Ltd | 半導体装置およびその製造方法 |
JP2006337069A (ja) * | 2005-05-31 | 2006-12-14 | Sanyo Electric Co Ltd | 回路装置およびその製造方法 |
JP2008216181A (ja) * | 2007-03-07 | 2008-09-18 | Citizen Holdings Co Ltd | 方位センサ及び電子機器 |
Also Published As
Publication number | Publication date |
---|---|
DE102009001932A1 (de) | 2010-09-30 |
ITMI20100473A1 (it) | 2010-09-28 |
US20100252939A1 (en) | 2010-10-07 |
IT1400084B1 (it) | 2013-05-17 |
US8198130B2 (en) | 2012-06-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8520396B2 (en) | Method for producing an electronic module | |
JP6822940B2 (ja) | 回路基板 | |
US8902604B2 (en) | Component support and assembly having a MEMS component on such a component support | |
US20220053633A1 (en) | Embedding Component in Component Carrier by Component Fixation Structure | |
US11574849B2 (en) | Package with embedded electronic component being encapsulated in a pressureless way | |
KR20150104033A (ko) | 초박형 임베디드 반도체 소자 패키지 및 그 제조 방법 | |
JP5093353B2 (ja) | 部品内蔵モジュールの製造方法及び部品内蔵モジュール | |
JP2010232663A (ja) | チップモジュール並びにチップモジュールを製造する方法 | |
KR20130103600A (ko) | 케이스형 전기 소자 | |
US20180350725A1 (en) | Electronic Device With a Plurality of Component Carrier Packages Being Electrically and Mechanically Connected | |
WO2017168342A1 (en) | Component embedding in thinner core using dielectric sheet | |
KR20190018135A (ko) | 모듈 및 복수의 모듈을 제조하는 방법 | |
KR20110100127A (ko) | 접속용 패드의 제조 방법 | |
US20170196094A1 (en) | Electronic component packaged in a flexible component carrier | |
KR101131289B1 (ko) | 전자부품 내장형 리지드-플렉시블 기판 및 그 제조방법 | |
KR101701380B1 (ko) | 소자 내장형 연성회로기판 및 이의 제조방법 | |
JP2020113761A (ja) | センサユニットならびに基板およびキャリアを相互接続する方法 | |
US9624093B2 (en) | Method and apparatus of making MEMS packages | |
US11410965B2 (en) | Electronic device with embedded component carrier | |
US20080237894A1 (en) | Integrated circuit package and method for the same | |
KR101147343B1 (ko) | 복수의 소자가 내장된 집적 인쇄회로기판 및 그 제조 방법 | |
JP2006310821A (ja) | 半導体モジュールおよびその製造方法 | |
KR20160084143A (ko) | 전자소자 내장기판 및 그 제조 방법 | |
KR20140081231A (ko) | 전자소자 내장형 인쇄회로기판 및 그 제조방법 | |
JP2009049281A (ja) | 半導体センサモジュール |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20101227 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20130326 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20140630 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20140818 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20150330 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20150611 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20151214 |