JP2010231005A - Electro-optical device, driving method thereof, and electronic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress generation of flickers and display deterioration regarding an electro-optical device, a driving method thereof, and an electronic device. <P>SOLUTION: The electro-optical device includes: a digital code generation means for dividing a one-frame period of image data into a plurality of sub-frame periods and generating a digital code for defining lighting/nonlighting of a pixel in each of the plurality of sub-frame periods; a voltage supply means for supplying a data voltage corresponding to the digital code to the pixel electrode of the pixel; and a common voltage supply means for supplying a common voltage to the common electrode of the pixel. The digital code generation means generates the digital code so that one of lighting and nonlighting concentrate during a continuous sub-frame period including an earlier sub-frame period or a later sub-frame period in the one-frame period of the plurality of sub-frame periods. The common voltage supply means invert the common voltage by an odd-number of times during the one-frame period. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

 Some embodiments according to the present invention relate to an electro-optical device, a driving method thereof, an electronic apparatus, and the like.

  In a liquid crystal device which is one form of an electro-optical device, positive and negative voltages are alternately applied to a common electrode (common electrode) in order to prevent deterioration (burn-in) of the liquid crystal element (AC drive). )There is a need. As such an AC driving method, common inversion driving in which the voltage of a common line (common potential line) is applied is known (see Patent Documents 1 and 2 below). In general common inversion driving, common inversion operation is performed once per frame period (1/60 second). That is, assuming that a period in which a positive voltage is applied to the common electrode is + field and a period in which a negative voltage is applied is −field, each of the + field and −field has a period of 2 frames (1 / 30 second period).

  Here, at the switching timing between + field and −field, that is, common inversion timing, the feedthrough phenomenon of the pixel transistor (the charge accumulated in the pixel capacitor is discharged through the parasitic capacitance between the gate and drain of the pixel transistor. Phenomenon), a luminance difference occurs between the + field and the − field. Since this luminance difference appears at a 1/30 second period (30 Hz), the luminance difference is visually recognized as flicker by the user's eyes. In the technique of Patent Document 2 below, flicker is suppressed by adjusting the common voltage according to the characteristics of the liquid crystal panel and eliminating the luminance difference between the + field and the − field.

JP 2005-241741 A JP 2003-344825 A

 In recent years, by performing a common inversion operation a plurality of times in one frame period and setting the generation period of the luminance difference between the + field and the − field to 1/60 second period (60 Hz) or more, flicker is visually recognized by the user. Techniques for preventing this have been proposed. However, according to this technique, it has been found that there is a problem that display deterioration (burn-in) occurs when digital time-division driving is adopted as a gradation expression method.

 As is well known, digital time-division driving means that one frame period is divided into a plurality of subframes, and a digital signal (binary voltage corresponding to lighting / non-lighting) is written to each pixel in each subframe period. In this method, intermediate gradation expression is performed by time integration of binary display in each subframe period. In this digital time-division driving, black display (non-lighting) is defined in the case of a normally white liquid crystal element as one of the digital code arrangement methods that prescribes lighting / non-lighting of pixels in each subframe period. There is a method of arranging the codes (for example, “1”) to be left-justified (in other words, determining the arrangement of digital codes so that the black display is concentrated in a predetermined range of subframes including the first subframe). A digital code having such an arrangement is called a left-justified code, and is inserted as a black period and is used as a digital code suitable for moving image display.

 Here, for example, consider a case where the common inversion operation is performed twice in one frame period (that is, + field and −field appear once in one frame period). In this case, if the left-justified code is used as a digital code, black display (writing of a non-lighting voltage) is biased in one of the + field and the − field, and the liquid crystal element cannot be driven with an alternating current. (Burn-in) is likely to occur.

 Some aspects of the present invention have been made in view of the above-described circumstances, and provide an electro-optical device, a driving method thereof, and an electronic apparatus that can suppress the occurrence of flicker and display degradation. Objective.

In order to achieve the above object, according to an electro-optical device according to the present invention, in an electro-optical device that displays image data, one frame period of the image data is divided into a plurality of sub-frame periods, and the plurality of sub-frame periods Digital code generating means for generating a digital code that defines lighting / non-lighting of the pixel in each of the above, a data voltage supply means for supplying a data voltage corresponding to the digital code to the pixel electrode of the pixel, A common voltage supply means for supplying a common voltage to a common electrode, wherein the digital code generation means is a first subframe period of the one frame period or an end of the one frame period of the plurality of subframe periods. Either lighting or non-lighting is concentrated in consecutive subframe periods including subframe periods Wherein generating a digital code, the common voltage supplying means, in the one frame period, and performs an odd number of times the inversion operation of the common voltage.
According to the electro-optical device having such a characteristic, in one frame period, the pixel electrode voltage (data voltage) is positive with respect to the common electrode voltage (common voltage) (+ field) and the common electrode voltage Thus, since the pixel electrode voltage appears alternately in the negative polarity period (-field), the lighting or non-lighting display (for example, black display in the normally white mode) is not biased in one field. In other words, in the electro-optical device according to the present invention, AC driving is sufficiently performed, generation of display deterioration (burn-in) can be suppressed, and the common inversion operation is performed an odd number of times or more, so that flicker is also generated. Can be suppressed.

In the electro-optical device described above, it is preferable that the common voltage supply unit performs the common voltage inversion operation three times in the one frame period.
Although it is possible to invert the common voltage five times or more in one frame period, in that case, the common voltage (common electrode voltage) is inverted at a high frequency, which causes another problem in display quality. May occur. The purpose of suppressing the occurrence of flicker and suppressing the occurrence of display deterioration (burn-in) can be sufficiently achieved by performing the common voltage inversion operation three times in one frame period.

On the other hand, an electronic apparatus according to the present invention includes the above-described electro-optical device.
According to the electronic apparatus having such a feature, high performance can be realized because the electro-optical device is provided with high display quality by suppressing flicker and display deterioration (burn-in).

Furthermore, the electro-optical device driving method according to the present invention is the electro-optical device driving method for displaying image data, wherein one frame period of the image data is divided into a plurality of sub-frame periods, and the plurality of sub-frame periods are divided. A first step of generating a digital code defining lighting / non-lighting of the pixel in each of the above, a second step of supplying a data voltage corresponding to the digital code to the pixel electrode of the pixel, A third step of supplying a common voltage to the common electrode, wherein the first step includes the first subframe period of the one frame period or the one frame period of the plurality of subframe periods. Generating the digital code so that either one of lighting or non-lighting is concentrated in a continuous subframe period including the last subframe period; In step, in one frame period, and it performs an odd number of times the inversion operation of the common voltage.
According to the driving method of the electro-optical device having such a feature, occurrence of flicker and display deterioration (burn-in) can be suppressed.

1 is a block configuration diagram of a liquid crystal device (electro-optical device) 100 according to an embodiment of the present invention. It is a detailed explanatory view regarding the pixel 110 in the liquid crystal device 100 according to the present embodiment. 4 is a detailed explanatory diagram of a data conversion circuit 400 in the liquid crystal device 100 according to the present embodiment. FIG. It is explanatory drawing regarding the correspondence of the frame structure and digital code Ds in the liquid crystal device 100 which concerns on this embodiment. 4 is a detailed explanatory diagram of a data line driving circuit 600 in the liquid crystal device 100 according to the present embodiment. FIG. 1 is an overall configuration diagram of a liquid crystal device 100 according to an embodiment. 4 is a timing chart showing the operation of the liquid crystal device 100 according to the present embodiment. It is explanatory drawing regarding the common inversion operation | movement of the liquid crystal device 100 which concerns on this embodiment. It is a block diagram of the projector which is an example of the electronic device to which the liquid crystal device 100 which concerns on this embodiment is applied. It is a block diagram of the personal computer which is an example of the electronic device to which the liquid crystal device 100 which concerns on this embodiment is applied. It is a block diagram of the mobile telephone which is an example of the electronic device to which the liquid crystal device concerning this embodiment is applied.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram illustrating an electro-optical device according to this embodiment. As an example of the electro-optical device according to the present embodiment, a liquid crystal device 100 having a configuration in which an element substrate and a counter substrate are attached with a certain gap therebetween and liquid crystal as an electro-optic material is sandwiched in the gap is illustrated. I will explain.

 Note that the liquid crystal device 100 according to the present embodiment employs common inversion driving as an AC driving method and digital time-division driving (digital code is a left-justified code) as a gradation expression method. The display mode of the liquid crystal device 100 is normally white, and it is assumed that black display (non-lighting) is performed when a voltage is applied to a pixel and white display (lighting) is performed when no voltage is applied.

In such a liquid crystal device 100, a transparent substrate such as a glass substrate is used as an element substrate,
A peripheral driving circuit and the like are formed on the element substrate together with transistors for driving pixels. On the other hand, in the display region 101a on the element base slope, m scanning lines 112 and storage capacitor lines 113 are formed extending in the X direction, and n data lines 114 are extending along the Y direction. In addition, the pixels 110 are arranged in a matrix of m rows × n columns corresponding to each intersection of the scanning lines 112 and the data lines 114 (m and n are integers of 2 or more).

FIG. 2 shows an example of a specific configuration of the pixel 110. As shown in FIG.
0 is a transistor (MOS type FET) 116 as a switching means having a gate connected to the scanning line 112, a source connected to the data line 114, a drain connected to the pixel electrode 118, and a pixel electrode 118 and a counter electrode (common electrode). ) 108 is sandwiched between the liquid crystal 105 as an electro-optic material and a liquid crystal layer is formed.

 Here, the counter electrode 108 is a transparent electrode formed on the entire surface of the counter substrate so as to face the pixel electrode 118. In addition, a storage capacitor 119 is formed between the pixel electrode 118 and the storage capacitor line 113, and the charge is supplementarily stored together with electrodes sandwiching the liquid crystal layer. Note that the common voltage VCOM is supplied to the counter electrode 108 and the storage capacitor line 113 from a drive voltage generation circuit 300 described later.

   Each scanning line 112 is supplied with scanning signals G1, G2,..., Gm from a scanning line driving circuit 500 described later. The transistors 116 constituting the pixels of the respective lines are turned on by the respective scanning signals, whereby display data signals d1, d2,..., Dn supplied from the data line driving circuit 600 described later to the respective data lines 114 are converted into pixels. The voltage is supplied to the electrode 118 and written into the liquid crystal 105 and the storage capacitor 119. Here, since digital time division driving is adopted, the display data signals d1, d2,..., Dn are binary voltages corresponding to non-lighting (black) / lighting (white). Thus, the alignment state of the molecular assembly of the liquid crystal 105 changes according to the voltage written to the pixel 110, that is, the potential difference between the pixel electrode 118 and the counter electrode 108, and the illumination light is modulated.

 Hereinafter, returning to FIG. 1, the electrical configuration of the liquid crystal device 100 according to the present embodiment will be described. In FIG. 1, the liquid crystal device 100 according to this embodiment includes a timing signal generation circuit 200, a drive voltage generation circuit 300, a data conversion circuit 400, a scanning line drive circuit 500, and a data line drive circuit 600. Yes. Of the above components, the timing signal generation circuit 200 and the data conversion circuit 400 correspond to digital code generation means, and the drive voltage generation circuit 300, the scanning line drive circuit 500, and the data line drive circuit 600 are data voltage supply means. The drive voltage generation circuit 300 corresponds to a common voltage supply unit.

 The timing signal generation circuit 200 is connected to a polarity inversion signal FR, a scanning start pulse DY, and scanning side transfer according to timing signals such as a vertical synchronization signal Vs, a horizontal synchronization signal Hs, and a dot clock DCLK supplied from a host controller (not shown). A clock CLY, a data enable signal ENBX, a data transfer clock CLX, a data transfer start pulse DDS, and a subframe identification signal SF are generated.

 The polarity inversion signal FR is a signal that defines the polarity inversion period of the write voltage of the pixel 110 (in other words, a signal that defines the common inversion operation period), and is output to the drive voltage generation circuit 300 and the data conversion circuit 400. In the present embodiment, the polarity inversion period is determined so that the polarity is inverted odd times (three times) in one frame period. That is, the polarity inversion signal FR is a pulse signal whose level changes three times in one frame period (a pulse signal having a period of one frame period Tf × 2/3) (see FIG. 7 described later). In the present embodiment, it is assumed that a positive voltage is written into the pixel 110 when the polarity inversion signal FR is at a high level, and a negative voltage is written into the pixel 110 when the polarity inversion signal FR is at a low level.

 The scan start pulse DY is a pulse signal that defines the start timing of each subframe, and is output to the scan line driving circuit 500. The scanning side transfer clock CLY is a signal that defines the scanning speed on the scanning side (Y side) (in other words, a signal that defines the output timing of the scanning signals G1, G2,..., Gm). Is output. The data enable signal ENBX is a signal that defines the timing at which the data stored in the X shift register 610 in the data line driving circuit 600 is output in parallel for the number of horizontal pixels, and is output to the data line driving circuit 600.

 The data transfer clock CLX is a data transfer clock signal and is output to the data conversion circuit 400 and the data line driving circuit 600. The data transfer start pulse DDS is a signal that defines the timing for starting data transfer from the data conversion circuit 400 to the data line driving circuit 600, and is output to the data conversion circuit 400. The subframe identification signal SF is a signal for notifying the data conversion circuit 400 of what subframe the subframe is in one frame period.

 The drive voltage generation circuit 300 generates a voltage VG (gate-on voltage of the transistor 116) of the scanning signals G1, G2,..., Gm and outputs it to the scanning line driving circuit 500, and displays the display data signals d1, d2,. A reference voltage V0, a maximum voltage VD1 (non-lighting (black) voltage in the case of positive polarity), and a minimum voltage VD2 (non-lighting (black) voltage in the case of negative polarity) are generated and output to the data line driving circuit 600. Further, the common voltage VCOM is generated and output to the counter electrode 108 and the storage capacitor line 113. The maximum voltage VD1 and the minimum voltage VD2 are set to values that are symmetrical about the reference voltage V0.

 Further, the drive voltage generation circuit 300 has a function of inverting the polarity of the common voltage VCOM around the reference voltage V0 in accordance with the level of the polarity inversion signal FR (common inversion drive). That is, when the polarity inversion signal FR is at a high level (positive polarity), the common voltage VCOM is a negative value (minimum value) with respect to the reference voltage V0, and when the polarity inversion signal FR is at a low level (negative polarity), The common voltage VCOM is a positive-side value (maximum value) with respect to the reference voltage V0. The maximum value of the common voltage VCOM is set to be equal to the maximum voltage VD1 of the display data signal, and the minimum value of the common voltage VCOM is set to be equal to the minimum voltage VD2 of the display data signal.

 FIG. 3 is a detailed configuration diagram of the data conversion circuit 400. As shown in FIG. 3, the data conversion circuit 400 includes a write address generation unit 410, a read address generation unit 420, a memory controller 430, frame memories 440 and 450, and a data encoder 460.

  The write address generation unit 410 specifies the position (that is, the position of the pixel) on the screen of the image data sent from the host controller by using the horizontal synchronization signal Hs, the vertical synchronization signal Vs, and the dot clock DCLK. Based on the specified result, a write address for storing the image data in the frame memories 440 and 450 is generated and output to the memory controller 430. The read address generation unit 420 determines the display position on the screen from the timing signal such as the data transfer clock CLX, and based on the determination result, the data is read from the frame memories 440 and 450 according to the same rule as at the time of writing. Is read out and output to the memory controller 430.

  The memory controller 430 performs control for writing image data input from the host controller into the frame memories 440 and 450 and reading out image data to be displayed from the frame memories 440 and 450. In other words, the memory controller 430 writes the image data to the write address generated by the write address generation unit 410 in synchronization with the dot clock DCLK, while the read address generation unit synchronizes with the data transfer clock CLX. Image data is read from the read address generated at 420 and output to the data encoder 460.

 The frame memories 440 and 450 are image data storage memories that are used alternately for writing or reading for each frame, and each has a storage capacity capable of storing at least one frame of image data. Yes.

 The data encoder 460 identifies the current subframe based on the subframe identification signal SF, and uses the image data input from the memory controller 430 as a digital code that defines lighting / non-lighting of the pixel 110 in the current subframe period. The data is converted to Ds and output to the data line driving circuit 600 in synchronization with the data transfer start pulse DDS.

 FIG. 4 shows the temporal correspondence between the subframe configuration within one frame period and the digital code Ds in the present embodiment. As shown in FIG. 4, one frame period is equally divided into a plurality (k) of subframes SF1 to SFk, and the digital code Ds is not lit (black) corresponding to each of the subframes SF1 to SFk. ) Or lighting (white). In the present embodiment, since the left-justified code is adopted as the digital code Ds, the code (“1”) that defines non-lighting (black) is arranged left-justified (in other words, the first subframe SF1 is arranged). The arrangement of the digital code Ds is determined so that the black display is concentrated on the subframe group within a predetermined range including the same).

 Returning to FIG. 1, the description continues and the scanning line driving circuit 500 grasps the start timing of each subframe from the scanning start pulse DY and also applies a voltage to each scanning line 112 in synchronization with the scanning transfer clock CLY. Scan signals G1, G2, G3,..., Gm having VG are sequentially output.

 The data line driving circuit 600 sequentially latches n digital codes Ds corresponding to the number of data lines 114 in a certain horizontal scanning period, and then the latched n digital codes Ds are displayed data signals in the next horizontal scanning period. are converted to d1, d2, d3,..., dn, and output simultaneously to the corresponding data lines 114. FIG. 5 shows a specific configuration of the data line driving circuit 600. As shown in FIG. 5, the data line driving circuit 600 includes an X shift register 610, a first latch circuit 620, a second latch circuit 630, and a voltage selection circuit 640.

   Among these, the X shift register 610 transfers the data enable signal ENBX supplied at the beginning of the horizontal scanning period in accordance with the data transfer clock CLX, and sequentially supplies it exclusively as the latch signals S1, S2, S3,. Is. The first latch circuit 620 sequentially latches the digital code Ds corresponding to each data line 114 at the falling edge of the latch signals S1, S2, S3,. The second latch circuit 630 latches each of the digital codes Ds latched by the first latch circuit 620 at the falling edge of the data enable signal ENBX.

   Based on the value of the digital code Ds corresponding to each of the data lines 114 latched by the second latch circuit 630 and the level of the polarity inversion signal FR, the voltage selection circuit 640 applies to each of the data lines 114. A data voltage to be output as the display data signals d1, d2, d3,. That is, when the digital code Ds is a code (“1”) that defines non-lighting (black) and the polarity inversion signal FR is at a high level (positive polarity), the voltage selection circuit 640 displays a display data signal. The maximum voltage VD1 is selected as the data voltage to be output. In addition, the voltage selection circuit 640 displays a display data signal when the digital code Ds is a code (“1”) that defines non-lighting (black) and the polarity inversion signal FR is at a low level (negative polarity). The minimum voltage VD2 is selected as the data voltage to be output.

 On the other hand, the voltage selection circuit 640 outputs a display data signal when the digital code Ds is a code (“0”) that defines lighting (white) and the polarity inversion signal FR is at a high level (positive polarity). The minimum voltage VD2 is selected as the data voltage to be used. The voltage selection circuit 640 outputs a display data signal when the digital code Ds is a code (“0”) that defines lighting (white) and the polarity inversion signal FR is at a low level (negative polarity). The maximum voltage VD1 is selected as the data voltage to be used.

 Due to the selection operation of the data voltage to be output as the display data signal by the voltage selection circuit 640 and the common voltage inversion operation by the drive voltage generation circuit 300 described above, the polarity inversion signal FR is in a high level period (hereinafter referred to as “this”). In the period in which the period is referred to as + field), a positive voltage is written to the pixel 110 with respect to the common voltage VCOM, and in the period in which the polarity inversion signal FR is at a low level (hereinafter, this period is referred to as -field). 110 is written with a negative voltage with respect to the common voltage VCOM.

   Next, the overall configuration of the liquid crystal device 100 will be described with reference to FIG. Here, FIG. 6A is a plan view showing the entire configuration of the liquid crystal device 100, and FIG. 6B is a cross-sectional view taken along the line A-A 'in FIG. As shown in these drawings, in the liquid crystal device 100, the element substrate 101 on which the pixel electrode 118 and the like are formed and the counter substrate 102 on which the counter electrode 108 and the like are formed have a certain gap by a sealant 104. The liquid crystal 105 as an electro-optic material is sandwiched between the gaps while being bonded together. Actually, the sealing material 104 has a cut-out portion, and after the liquid crystal 105 is sealed through this, the sealing material 104 is sealed with a sealing material, but is omitted in these drawings.

   The counter electrode 102 is a transparent substrate made of glass or the like. In the above description, the element substrate 101 is described as being made of a transparent substrate. However, in the case of a reflective liquid crystal device, it may be a semiconductor substrate. In this case, since the semiconductor substrate is opaque, the pixel electrode 118 is formed of a reflective metal such as aluminum. In the element substrate 101, a light shielding film 106 is provided on the inner side of the sealing material 104 and on the outer side of the display region 101 a. In the region where the light shielding film 106 is formed, the scanning line driving circuit 500 is formed in the region 130a, and the data line driving circuit 600 is formed in the region 140a.

   That is, the light shielding film 106 prevents light from entering the drive circuit formed in this region. A common voltage VCOM is applied to the light shielding film 106 together with the counter electrode 108. Further, in the element substrate 101, a plurality of connection terminals are formed outside the region 140a where the data line driving circuit 600 is formed and separated from the sealant 104. It is configured to input power.

   On the other hand, the counter electrode 108 of the counter substrate 102 is electrically connected to the light-shielding film 106 and the connection terminal in the element substrate 101 by a conductive material (not shown) provided in at least one of the four corners of the substrate bonding portion. Conduction is achieved. That is, the common voltage VCOM is applied to the light shielding film 106 via a connection terminal provided on the element substrate 101 and further to the counter electrode 108 via a conductive material.

   In addition, the counter substrate 102 is first provided with a color filter arranged in a stripe shape, a mosaic shape, a triangle shape, or the like according to the use of the liquid crystal device LD, for example, if it is a direct view type. 2 is provided with a light shielding film (black matrix) made of, for example, a metal material or resin. In the case of the use of color light modulation, for example, when used as a light valve of a projector described later, a color filter is not formed. In the case of the direct-view type, the liquid crystal device 100 is provided with a light for irradiating light from the counter substrate 102 side or the element substrate side as necessary.

 In addition, the electrode formation surfaces of the element substrate 101 and the counter substrate 102 are each provided with an alignment film (not shown) that is rubbed in a predetermined direction to define the alignment direction of the liquid crystal molecules when no voltage is applied. On the other hand, a polarizer (not shown) corresponding to the orientation direction is provided on the counter substrate 101 side. However, if a polymer dispersion type liquid crystal dispersed as fine particles in a polymer is used as the liquid crystal 105, the above-described alignment film, polarizer and the like are not required, so that the light utilization efficiency is increased. This is advantageous in terms of reducing power consumption.

Next, the operation of the liquid crystal device 100 according to the present embodiment configured as described above will be described with reference to the timing chart of FIG.
As shown in FIG. 7, the polarity inversion signal FR is a pulse signal whose level changes three times during one frame period Tf (a pulse signal having a period of one frame period Tf × 2/3). On the other hand, the scan start pulse DY is supplied at the start of each subframe SF1 to SFk. Here, at time t1, which is the start timing of one frame period Tf, when a scan start pulse DY defining the start timing of the first subframe SF1 is supplied, the scan line driving circuit 500 synchronizes with the scan side transfer clock CLY. The scanning signals G1, G2, G3,..., Gm are sequentially output in the vertical scanning period (1V).

 These scanning signals G1, G2, G3,..., Gm each have a pulse width corresponding to a half cycle of the scanning side transfer clock CLY, and are applied to the first (first row) scanning line 112 counted from the top. The corresponding scanning signal G1 is output with a delay of at least a half cycle of the scanning side transfer clock CLY after the scanning side transfer clock CLY first rises after the scanning start pulse DY is supplied. . Accordingly, the first clock (G0) of the data enable signal ENBX is supplied to the data line driving circuit 600 from the supply of the scan start pulse DY to the output of the scan signal G1.

 First, a case where the first one clock (G0) of the data enable signal ENBX is supplied will be described. When one clock (G0) of the data enable signal ENBX is supplied to the data line driving circuit 600, the latch signals S1, S2, S3,..., Sn are horizontal from the X shift register 610 in synchronization with the data transfer clock CLX. The signals are sequentially output in the scanning period (1H). Note that each of the latch signals S1, S2, S3,..., Sn has a pulse width corresponding to a half cycle of the data transfer clock CLX.

 At this time, at the falling edge of the latch signal S1, the first latch circuit 620 includes the first (first row) scanning line 112 counted from the top and the first (first column) data line counted from the left. The digital code Ds corresponding to the pixel 110 arranged at the intersection with the pixel 114 is latched, and then at the falling edge of the latch signal S2, the scan line 112 at the first row and the data line 114 at the second column are intersected. The digital code Ds corresponding to the arranged pixel 110 is latched. Hereinafter, similarly, the digital code Ds corresponding to the pixel 110 arranged at the intersection of the scanning line 112 of the first row and the data line 114 of the nth column is latched. Latch.

 Accordingly, first, the digital code Ds for one row of pixels connected to the first row scanning line 112 is latched dot-sequentially by the first latch circuit 620. Note that the data conversion circuit 400 converts the image data corresponding to each pixel into a digital code Ds corresponding to each subframe and sequentially outputs it in accordance with the latch timing of the first latch circuit 620. Not too long. Next, when the scanning-side transfer clock CLY falls and the scanning signal G1 is output, the scanning line 112 in the first row is selected. As a result, all the transistors 116 of the pixels 110 connected to the scanning line 112 are selected. Turn on.

 On the other hand, the data enable signal ENBX (G1) is output again at the falling timing of the scanning transfer clock CLY. The digital codes Ds latched dot-sequentially by the first latch circuit 620 as described above are simultaneously latched by the second latch circuit 630 at the rising timing of the data enable signal ENBX (G1).

 The voltage selection circuit 640 then selects each data line based on the value of the digital code Ds corresponding to each of the data lines 114 latched simultaneously by the second latch circuit 630 and the level of the polarity inversion signal FR. A data voltage to be output as the display data signals d1, d2, d3,. For example, if the polarity inversion signal FR is at a high level (+ field) in the subframe SF1 and the digital code Ds is a code that defines non-lighting (black) (“1”), the display data signal is output. The maximum voltage VD1 is selected as the power data voltage. At this time, the drive voltage generation circuit 300 sets the common voltage VCOM to a negative-side value (minimum value) with respect to the reference voltage V0.

  Through the above operation, in the first subframe SF1, the display data signals d1, d2, d3,..., Dn are written to all the pixels 110 in the first row in accordance with the polarity defined by the polarity inversion signal FR. It will be done at the same time. In parallel with this writing, the digital code Ds for one row of pixels connected to the second (second row) scanning line 112 from the top is latched dot-sequentially by the first latch circuit 620. Thereafter, the same operation is repeated until the scanning signal Gm corresponding to the m-th scanning line 112 is output.

 The above is the operation performed for one subframe (here, subframe SF1), and a black image is displayed in the subframe SF1 by the black voltage (non-lighting voltage) written to all the pixels 110 in the display region 101a. . Then, the operation for each subframe is repeated for one frame (that is, here, from subframe SF1 to subframe SFk), thereby displaying an image for one frame. Here, since the left-justified code is adopted in the present embodiment, as shown in FIG. 4, black display is performed in order from the first subframe SF1 on the time axis.

 On the other hand, FIG. 8A shows a + field that appears every frame by the common inversion operation of the liquid crystal device 100 according to the present embodiment, that is, the common inversion operation that is performed odd times (here, 3 times) in one frame period. A distribution of (a period in which the writing voltage of the pixel 110 is positive with respect to the common voltage VCOM) and -field (a period in which the writing voltage of the pixel 110 is negative with respect to the common voltage VCOM) is shown. For comparison with FIG. 8 (a), FIG. 8 (b) shows a + field and a − field that appear every frame by the conventional common inversion operation (the common inversion operation is performed twice in one frame period). The distribution of.

 As shown in FIG. 8B, according to the conventional common inversion operation, when the above left-justified code is adopted as the digital code Ds, black display (writing of non-lighting voltage) is biased in the + field, and white display in the − field. (Lighting voltage writing) is biased. Thus, when the display is biased to one of the +/− fields, the AC drive is not sufficiently performed, and display deterioration (burn-in) is likely to occur.

 On the other hand, as shown in FIG. 8A, according to the common inversion operation of the liquid crystal device 100 according to the present embodiment, the + field and the − field appear alternately in one frame period, so that black display is displayed in the + field. There is no bias (the first + field is biased to black, but the next + field is white). That is, in the liquid crystal device 100 according to the present embodiment, AC driving is sufficiently performed, and the occurrence of display deterioration (burn-in) can be suppressed.

 As described above, according to the liquid crystal device 100 according to the present embodiment, since the common inversion operation is performed odd times (three times) in one frame period, the left justification code is adopted as the digital code of the digital time division driving. In addition, it is possible to suppress the occurrence of flicker and display deterioration (burn-in).

 In the above embodiment, the common inversion operation performed in one frame period is three times. However, the common inversion operation is not limited to this. As described above, the common voltage inversion operation can be performed five times or more in one frame period. In this case, the common voltage (common electrode voltage) is inverted at a high frequency. Another problem may occur. The purpose of suppressing the occurrence of flicker and suppressing the occurrence of display deterioration (burn-in) can be sufficiently achieved by performing the common voltage inversion operation three times in one frame period.

 In the above embodiment, the case where the normally white mode is adopted has been described. However, even when the normally black mode is adopted, the code defining white (lighting) is arranged from the left and the left justified code. Therefore, the occurrence of flicker and display deterioration (burn-in) can be suppressed as in the normally white mode by setting the common inversion operation performed in one frame period to an odd number of times.

 Furthermore, in the above-described embodiment, the case where the left-justified code is adopted has been described as an example. However, the right-occupied code (digital code so that lighting or non-lighting is concentrated in a predetermined range of subframes including the last subframe SFk) Even in the case of adopting (deciding the arrangement of), the occurrence of flicker and display deterioration (burn-in) is suppressed in the same way as the left-justified code by setting the common inversion operation to be performed odd times in one frame period. Is possible.

<Electronic equipment>
Next, an example of an electronic apparatus including the liquid crystal device 100 (electro-optical device) will be described.
(1) Projector First, a projector using the liquid crystal device 100 according to the present embodiment as a light valve will be described. FIG. 9 is a plan view showing the configuration of the projector. As shown in FIG. 9, a polarization illumination device 1110 is disposed inside the projector 1100 along the system optical axis PL. In this polarization illumination device 1110, the light emitted from the lamp 1112 becomes a substantially parallel light beam as reflected by the reflector 1114, and enters the first integrator lens 1120. Thereby, the emitted light from the lamp 1112 is divided into a plurality of intermediate light beams. The divided intermediate light beam is converted into one type of polarized light beam (s-polarized light beam) whose polarization directions are substantially aligned by a polarization conversion element 1130 having a second integrator lens on the light incident side, and the polarized illumination device 1110 It will be emitted from.

   The s-polarized light beam emitted from the polarization illumination device 1110 is reflected by the s-polarized light beam reflecting surface 1141 of the polarization beam splitter 1140. Of this reflected light beam, the blue light (B) light beam is reflected by the blue light reflecting layer of the dichroic mirror 1151 and modulated by the reflective liquid crystal device 100B. Of the light beams transmitted through the blue light reflecting layer of the dichroic mirror 1151, the red light (R) light beam is reflected by the red light reflecting layer of the dichroic mirror 1152 and modulated by the reflective liquid crystal device 100R. On the other hand, among the light beams transmitted through the blue light reflecting layer of the dichroic mirror 1151, the green light (G) light beam is transmitted through the red light reflecting layer of the dichroic mirror 1152 and modulated by the reflective liquid crystal device 100G.

 In this way, the red, green, and blue lights that have been color-light modulated by the liquid crystal devices 100R, 100G, and 100B are sequentially combined by the dichroic mirrors 1152 and 1151, and the polarization beam splitter 1140, and then are projected by the projection optical system 1160. It is projected on the screen 1170. In addition, since light beams corresponding to R, G, and B primary colors are incident on the liquid crystal devices 100R, 100B, and 100G by the dichroic mirrors 1151, 1152, a color filter is not necessary. In the present embodiment, a reflective liquid crystal device is used, but a projector using a transmissive display liquid crystal device may be used.

(2) Mobile Computer Next, an example in which the liquid crystal device 100 is applied to a mobile personal computer will be described. FIG. 10 is a perspective view showing the configuration of this personal computer. In the drawing, a personal computer 1200 includes a main body 1204 provided with a keyboard 1202 and a display unit 1206. The display unit 1206 is configured by adding a front light to the front surface of the liquid crystal device 100 described above. In this configuration, since the liquid crystal device 100 is used as a reflection direct view type, it is desirable that the pixel electrode 118 has irregularities so that the reflected light is scattered in various directions.

(3) Mobile phone Further, an example in which the liquid crystal device 100 is applied to a mobile phone will be described. FIG. 11 is a perspective view showing the configuration of this mobile phone. In the figure, a mobile phone 1300 includes a liquid crystal device 100 along with a plurality of operation buttons 1302, an earpiece 1304, and a mouthpiece 1306. The liquid crystal device 100 is also provided with a front light on the front surface as necessary. Also in this configuration, since the liquid crystal device 100 is used as a reflection direct view type, a configuration in which irregularities are formed in the pixel electrode 118 is desirable.

    As electronic devices, in addition to those described with reference to FIGS. 9 to 11, a liquid crystal television, a viewfinder type, a monitor direct view type video tape recorder, a car navigation device, a pager, an electronic notebook, a calculator, a word processor. , Workstations, videophones, POS terminals, devices with touch panels, and the like.

 DESCRIPTION OF SYMBOLS 100 ... Liquid crystal device (electro-optical device), 101 ... Element substrate, 101a ... Display area, 102 ... Counter substrate, 105 ... Liquid crystal, 108 ... Counter electrode, 112 ... Scan line, 114 ... Data line, 116 ... Transistor, 118 ... Pixel electrode, 119 ... holding capacitor, 200 ... timing signal generation circuit, 300 ... drive voltage generation circuit, 400 ... data conversion circuit, 500 ... scanning line drive circuit, 600 ... data line drive circuit

Claims (4)

In an electro-optical device that displays image data,
A digital code generating means for dividing one frame period of the image data into a plurality of subframe periods and generating a digital code defining lighting / non-lighting of pixels in each of the plurality of subframe periods;
Data voltage supply means for supplying a data voltage corresponding to the digital code to the pixel electrode of the pixel;
Common voltage supply means for supplying a common voltage to the common electrode of the pixel;
With
The digital code generation means is lit or unlit in a continuous subframe period including a first subframe period of the one frame period or a last subframe period of the one frame period among the plurality of subframe periods. Generate the digital code so that either one is concentrated,
The common voltage supply means performs the common voltage inversion operation an odd number of times in the one frame period.
An electro-optical device.   2. The electro-optical device according to claim 1, wherein the common voltage supply unit performs the common voltage inversion operation three times in the one frame period.   An electronic apparatus comprising the electro-optical device according to claim 1. In a driving method of an electro-optical device for displaying image data,
A first step of dividing one frame period of the image data into a plurality of subframe periods and generating a digital code defining lighting / non-lighting of pixels in each of the plurality of subframe periods;
A second step of supplying a data voltage corresponding to the digital code to the pixel electrode of the pixel;
A third step of supplying a common voltage to the common electrode of the pixel;
Have
In the first step, lighting or non-lighting is performed in consecutive subframe periods including the first subframe period of the one frame period or the last subframe period of the one frame period among the plurality of subframe periods. Generate the digital code so that either one is concentrated,
In the third step, the common voltage inversion operation is performed an odd number of times in the one frame period.
A driving method for an electro-optical device.

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