JP2010226162A - Clock supply device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a system clock supply device in which an in-use clock and a standby system clock are matched in phase with each other together with a wiring delay amount between back boards and a variation amount of buffer delay due to temperature variation and voltage variation. <P>SOLUTION: The system clock supply device includes the in-use and standby system clock supply unit 200 having redundant constitution such that in-use and standby system clocks 6 phase-synchronized to a system clock 1 are output, and a back board 8 configured to distribute the in-use and standby system clocks to respective parts in the device. A PLL 210 for generating the clock 22 phase-synchronized to the system clock 1 includes a phase difference adjusting unit 211 which controls the phase of the standby system clock based upon the in-use system clock. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a clock supply device, and more particularly to a clock supply device having an active clock supply unit and a standby clock supply unit.

  A system configuration of a conventional transmission apparatus will be described with reference to FIG. The transmission apparatus 100 includes an operational clock board 4-1, a standby clock board 4-2, a control board 10, a back board 8, and four interface boards 9 that are redundantly configured to improve reliability. ing. Each of the two clock boards 4 includes a PLL 41 and a CLK (clock) distribution unit 43. The backboard 8 is arranged in parallel on the back surface of the transmission apparatus 100 and includes a plurality of connectors (not shown) for inserting and connecting the clock board 4, the control board 10, and the interface board 9. The back board 8 interconnects the clock board 4, the control board 10, and the interface board 9. The interface board 9 includes a selector 91, a PLL 92, a Serdes (Serializer / deserializer) 94, and an optical Mod (Module) 95.

  The clock board 4 generates a clock 42 that is phase-synchronized with the system clock 1 supplied from the host device by the PLL 41. The clock board 4 further uses the clock board 42 generated by the PLL 41 as the operation system clock 7-1 and the standby system clock 7-2 via the CLK distribution unit 43 and the back board 8 as a device such as the interface board 9 or the like. Distribute to each part. In the control panel 10, the CLK control unit 11 generates a selection signal 12 for the operation system clock 7-1 and the standby system clock 7-2. The control board 10 inputs the selection signal 12 to the selector 91 of the interface board 9. The interface board 9 generates a line clock 93 that is phase-synchronized with the system clock 7 selected by the selection signal 12 in the PLL 92. The line clock 93 generated by the PLL 92 is used as a reference clock for the Serdes 94 that performs data processing. The Serdes 94 converts the received parallel electric signal into a high-speed serial electric signal, and transmits it to the optical Mod 95. The Serdes 94 further converts the serial electrical signal received from the optical Mod 95 into a low-speed parallel electrical signal. The optical module 95 converts the electrical signal received from the Serdes 94 into an optical signal and transmits the optical signal to the optical fiber 96. The optical module 95 also converts the optical signal received from the optical fiber 96 into an electrical signal and transmits it to the Serdes 94.

  In the transmission apparatus described above, when an abnormality occurs in the operating system clock, the transmission system is switched to the standby system clock so that the interface panel 9 is not affected. Here, when the system clock is switched, if there is a phase difference between the clocks of the active and standby system clocks, the interface panel 9 causes the clock phase jump (extension) and glitch ( Output flutter). Since the interface board 9 performs data processing based on the system clock, the occurrence of a clock phase jump or glitch may cause a communication failure due to data loss.

  Further, in communication systems such as transmission apparatuses, the amount of phase fluctuation of the active and standby system clocks and line clocks accompanying the switching of the system clock is recommended by international standards such as ITU-T. In order to avoid communication failures when switching system clocks and comply with international standards such as ITU-T, phase alignment between the active and standby system clocks or suppression of phase fluctuations by PLL mounted on the interface panel, etc. Can be mentioned. Depending on the amount of phase difference generated between the active and standby system clocks, strict design specifications are given to the PLL characteristics, making circuit design difficult. For this reason, it is necessary to minimize the phase difference generated between the active system and the standby system clock.

  In order to solve these problems, Patent Document 1 discloses a system clock supplied from a higher-level device and a system clock supplied from the higher-level device to the operation system and standby system clock output terminals that are phase-synchronized with the system clock. A technique for adjusting the phase difference between the active and standby system clocks so that the delay amount is the same is disclosed.

  Patent Document 2 discloses a technique in which an operating system and a standby system clock that are phase-synchronized with a system clock supplied from a host device adjust a phase difference between clocks at an output terminal.

JP 2004-229020 A JP 2007-060180 A

  In Patent Document 1, in order to adjust the phase between the clocks of the active and standby system clocks, it is necessary to adjust both the delay amount given to the active system clock and the delay amount given to the standby system clock. When the apparatus is in operation, the amount of delay given to the system clock selected as the operation system is adjusted when adjusting the buffer delay amount due to temperature change or voltage fluctuation. Also, when the standby system clock supply device is replaced, the delay amount applied to the system clock selected as the active system is adjusted as described above. This may cause a phase jump or glitch in the system clock selected as the operating system. In order to avoid the above-described clock phase jump or glitch, when a PLL is provided in the subsequent stage, the system cost increases due to an increase in the number of components, and it is difficult to cope with downsizing.

  Patent Document 2 adjusts the amount of delay given to the standby system clock based on the phase of the system clock selected as the active system. Therefore, the system clock selected as the operation system does not generate a phase jump or glitch. However, since a delay circuit using a delay line is adopted as means for adjusting the phase, the maximum adjustable range of the phase is limited by the number of delay lines mounted and the delay amount. Further, when a change occurs in the delay amount of the delay line due to a temperature change or a voltage change, there is a possibility that a phase change occurs between the operating system and the selected system clock. Further, the delay amount by the delay line is discrete. Further, even the phase difference caused by the wiring delay of the confounding signal between the active system and the standby system cannot be adjusted. For this reason, when switching from the active system clock to the standby system clock, there is a risk of causing a phase jump or glitch of the system clock.

  The object of the present invention is to solve the above-mentioned problems and change the phase of the active and standby system clocks in the redundant configuration to the amount of wiring delay between backboards, change in buffer delay due to temperature change or voltage fluctuation. It is an object of the present invention to provide a system clock supply device that matches the amount.

  The problem described above is to clock the first clock supply unit, the second clock supply unit, the first clock from the first clock supply unit, and the second clock from the second clock supply unit. Connect to the supply destination, connect the first interlaced signal from the first clock supply unit to the first clock supply unit and the second clock supply unit, and further to the second clock from the second clock supply unit A printed circuit board for connecting the confounding signal to the first clock supply unit and the second clock supply unit, and a clock control unit for selecting one of the first clock and the second clock, Each of the clock supply unit and the second clock supply unit includes a PLL and an input / output buffer, and the PLL detects a phase difference of the clock of the own system with reference to the clock of the other system, Detection result of phase difference detector And a integrator that integrates, with reference to the output of the integrator, the clock supply device which controls the clock phase can be achieved.

  According to the clock supply device of the present invention, the phases of the active and standby system clocks configured in a redundant configuration include the wiring delay amount between the backboards, the change amount of the buffer delay due to the temperature change or the voltage change. Can be matched.

It is a block diagram of a transmission apparatus. It is a block diagram of the transmission apparatus explaining the system clock supply apparatus which made the system clock supply part redundant. It is a block diagram of PLL. It is another block diagram of PLL.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings using examples. Note that the same reference numerals are assigned to substantially the same parts, and description thereof will not be repeated.

  In FIG. 2, the transmission device 300 includes two system clock supply units 200, four interface boards 9, a backboard 8 </ b> A, and a control board 10. The backboard 8A distributes the system clock 6 from the system clock supply unit 200 to the interface board 9.

  The system clock supply device includes two system clock supply units 200, a backboard 8A, and a CLK control unit. In the system clock supply device, two system clock supply units 200 make the clock redundant. The system clock supply unit 200 outputs a system clock 6 that is phase-synchronized with the system clock 1 supplied from the host device.

  The system clock supply unit 200 includes a PLL 210 that outputs a clock 22 and a confounding signal 24 that are phase-synchronized with the system clock 1, and a buffer IC 230 that includes a CLK distribution output buffer and a CLK input buffer. In the operation system and standby system clock supply unit 200, the wirings 29-1 and 29-2 between the PLL 210 and the buffer IC 230 are designed to have the same wiring length. In the backboard 8, the wiring 81-1 of the operating system clock 6-1 and the wiring 81-2 of the standby system clock 6-2 distributed to each part in the apparatus are designed to have the same length. Further, the confounding signal 25 between the active system clock supply unit 200-1 and the standby system clock supply unit 200-2 and the own system phase detection signal 26 which is input to the own system clock supply device via the backboard 8 are returned. The wirings 83-1 and 83-2 are designed to have the same wiring length.

  The CLK control unit 11 of the control panel 10 generates and outputs an operation system and standby system clock selection signal 12 in the interface panel 9. The CLK control unit 11 of the control panel 10 generates and outputs a system notification signal 13 in the active system and standby system clock supply unit 200. Note that the polarities of the active notification signal 13-1 and the standby notification signal 13-2 are reversed.

  The PLL 210 includes a phase difference adjustment unit 211. The phase difference adjustment unit 211 transmits the phase control value to the PLL. Note that the phase difference adjustment value of the operational phase difference adjustment unit 211 is “0”. Further, the phase difference adjustment value of the standby phase difference adjustment unit 211 is an integral value of the difference from the standby system clock phase with reference to the active system clock phase.

  The configuration of the PLL 210 will be described with reference to FIG. In FIG. 3, the PLL 210 </ b> A includes a phase comparison unit 30, an LPF (Low Pass Filter) 32, a D / A converter 33, a VCO (Voltage Controlled Oscillator) 34, and a phase difference adjustment unit 211. The phase difference adjustment unit 211 further includes a phase difference detection unit 36, an integrator 35, a selector 37, and a phase control unit 31.

  The phase comparison unit 30 compares the phases of the system clock 1 and the output of the VCO 34. When the phase comparator 30 detects a phase difference between the system clock 1 and the output of the VCO 34, the phase comparator 30 generates an error signal pulse. The LPF 32 converts the error signal pulse into a DC voltage signal. The D / A converter 33 performs D / A conversion on the DC voltage signal to convert it into a DC voltage. The VCO 34 changes the output frequency by a frequency corresponding to the DC voltage. The loop of the phase difference detection unit 30, the phase control unit 31, the LPF 32, the D / A converter 32, the VCO 34, and the phase difference detection unit 36 constituting the PLL 210 is referred to as a main loop.

  The phase difference detection unit 36 detects a difference from the clock phase of the own system on the basis of the clock phase of the other system. The integrator 35 integrates the phase difference for N times of feedback of the main loop. The selector 37 receives the 0 (zero) signal, the output of the integrator 35, and the system notification signal 13. The selector 37 outputs a 0 signal when the system notification signal 13 is the active system notification signal 13-1. The selector 37 outputs the output of the integrator 35 when the system notification signal 13 is the standby system notification signal 13-2. The phase control unit 31 adds the output of the phase comparison unit 30 and the output of the selector 37 once every N feedback times of the main loop. The loop of the phase control unit 31, the LPF 32, the D / A 33, the VCO 34, the buffer IC 230 (two stages) in FIG. 2, the phase difference detection unit 36, the integrator 35, the selector 37, and the phase control unit 31 is again called a sub-loop. Note that the phase difference adjustment unit 211 may be placed outside the PLL 210A.

  Returning to FIG. 2, the operation of the system clock supply device will be described. For convenience of explanation, the system clock supply 200-1 will be described as an active system, and the system clock supply unit 200-2 will be described as a standby system.

  In FIG. 2, the system clock 1 supplied from the host device is input to the active system clock supply unit and the standby system clock supply unit 200. The PLL 210 generates a clock 22 that is phase-synchronized with the system clock 1. The PLL 210 further generates confounding signals 24-1 and 24-2 between the active system clock supply unit 200-1 and the standby system clock supply unit 200-2.

  Further, the buffer IC 230 distributes the clock 22 to the interface board 9 as the operation system clock or the standby system clock 6. The buffer IC 230 further distributes the confounding signal 24 to the active system clock supply unit 200-1 and the standby system clock supply unit 200-2 as the own system phase detection signal 25 and the other system phase detection signal 26. Further, the buffer IC 230 sends the other system phase detection signal 25 and the own system phase detection signal 26 supplied from the active system or standby system clock supply unit 200 to the PLL 210, and the other system phase detection signal 28 and the own system phase detection signal. Input as 27.

  Here, standby system clock supply unit 200-2 performs phase control of clock 22 output from PLL 210 by standby system notification signal 13-2 input from control panel 10. Note that since the polarity-inverted control signal 13-1 is input to the operational system clock supply unit 200-1, phase control of the clock 22 output from the PLL 210 is not performed.

  Here, the delay amount Act Clk Delay to the interface board 9 of the operating system clock 6-1 output from the operating system clock supply unit 200-1 is represented by the delay amount resulting from (Equation 1).

Act Clk Delay
= PLL210-1 + wiring 29-1 + buffer 230-1 + wiring 81-1 (Formula 1)
Similarly, the delay amount Stb Clk Delay of the standby system clock 6-2 output from the standby system clock supply unit 200-2 to the interface board 9 is represented by the delay amount resulting from (Equation 2).

Stb Clk Delay
= PLL210-2 + wiring 29-2 + buffer 230-2 + wiring 81-2 (Formula 2)
Here, the clock phase difference Clk Ph Diff of the operation system clock 6-1 and the standby system clock 6-2 in the interface board 9 is a difference between (Expression 1) and (Expression 2). Further, considering that the wirings 29-1 and 29-2 and the wirings 81-1 and 81-2 have the same wiring length design, a phase difference caused by (Equation 3) occurs.

Clk Ph Diff
= Act Clk Delay-Stb Clk Delay
= PLL210-1−PLL210-2 + buffer 230-1−buffer 230-2 (formula 3)
Therefore, by setting the phase difference caused by (Equation 3) to zero, it is possible to supply the operation system clock 6-1 and the standby system clock 6-2 having the same phase to the interface board 9.

  Further, in the phase difference adjustment unit 211 in the PLL 210-2 of the standby system clock supply unit 200-2, the delay amount Act Sig Delay of the other system phase detection signal 28 from the operation system system clock supply unit 200-1 is ( It is shown by the amount of delay due to equation 4).

Act Sig Delay
= PLL210-1 + wiring 29-1 + buffer 230-1
+ Wiring 83-1 + buffer 230-2 + wiring 29-2 (Expression 4)
Further, the delay amount Stb Sig Delay of the own-system phase detection signal 27 that is input back to the standby system clock supply unit 200-2 is represented by the delay amount resulting from (Equation 5).

Stb Sig Delay
= PLL210-2 + wiring 29-2 + buffer 230-2
+ Wiring 83-2 + buffer 230-2 + wiring 29-2 (Formula 5)
Here, the other system phase detection signal 28 from the operation system clock supply unit 200-1 obtained by the phase difference adjustment unit 211 in the PLL 210 of the standby system clock supply unit 200-2 and the standby system clock supply unit 200. The phase difference Sig Ph Diff of the own system phase detection signal 27 that is input back to -2 is the difference between (Equation 4) and (Equation 5). Furthermore, when considering that the wirings 29-1 and 29-2 and the wirings 83-1 and 83-2 have the same wiring length design, the phase difference resulting from (Equation 6) is obtained.

Sig Ph Diff
= Act Sig Delay-Stb Sig Delay
= PLL210-1−PLL210-2 + buffer 230-1−buffer 230-2 (formula 6)
Note that the phase control unit 31 in the PLL 210 of the standby system clock supply unit 200-2 controls the phase of the clock 22 so that the phase difference obtained by (Equation 6) is zero.
Since (Equation 3) and (Equation 6) are the same, making the phase difference obtained in (Equation 6) zero means that the phase difference generated in (Equation 3) is made zero. Are the same. In other words, it is possible to supply the operation system clock 6-1 and the standby system clock 6-2 having the same phase to the interface board 9.

  In FIG. 3, the standby PLL 210-2 includes the other system phase detection signal 28 from the operation system clock supply unit 200-1 and the own system phase detection signal 27 that is input to the standby system clock supply unit 200-2. Is entered. Further, the phase difference detection unit 36 uses the other system phase detection signal 28 as a reference, and the phase difference between the other system phase detection signal 28 and the own system phase detection signal 27 is delayed or advanced, and a positive or negative phase difference detection result is obtained. 51 is output. Further, the phase difference detection result 51 is input to the integrator 35. The integrator 35 outputs a phase difference integration result 52. The phase difference integration result 52 is input to the selector 37. The selector 37 further selects the phase difference integration result 52 according to the standby system notification signal 13-2 input from the control panel 10 and outputs it as the phase control value 53. Note that the operating system clock supply unit 200-1 selects zero based on the operating system notification signal 13-1 input from the control panel 10 and outputs the phase comparison result 50 as it is. Supply unit 200-1 does not perform phase control between clocks.

  Further, the phase comparison unit 30 outputs a phase comparison result 50 for generating the clock 22 that is phase-synchronized with the system clock 1 supplied from the host device. The phase control unit 31 adds the phase comparison result 50 of the main loop and the phase control value 53 of the sub loop. The phase control unit 31 outputs the phase control result 54. In addition, the addition cycle of the phase comparison result 50 and the phase control value 53 in the phase control unit 31 is performed in an addition cycle that does not affect the main loop characteristics. The phase control result 54 is converted into a control voltage 55 by the LPF 32 and the D / A converter 33. The VCO 34 changes the frequency of the clock 22 by the control voltage 55. Note that changing the frequency of the clock 22-2 also changes the phase. As a result, the phase comparison result 50 that is the output of the phase comparison unit 30 and the phase difference detection result 51 that is the output of the phase difference detection unit 36 also change. This operation is repeated until the phase control result 54 that is the output result of the phase control unit 31 converges to a constant value that is in a steady state.

  Here, the fact that the phase control result 54 in the phase control unit 31 converges to a constant value means that the phase control value 53 selected by the selector 37 and the phase comparison result 50 in the phase comparison unit 30 converge to a constant value. is doing. Further, the fact that the phase control value 53 selected by the selector 37 converges to a constant value means that the phase difference detection result 51 input to the integrator 35 becomes zero. Further, this is that the phase difference detection unit 36 matches the phase of the other-system phase detection signal 28 and the own-system phase detection signal 27. That is, it indicates that the phases of the operation system clock 6-1 and the standby system clock 6-2 are in agreement.

  A configuration of a PLL according to another embodiment will be described with reference to FIG. 4, the PLL 210B includes a frequency comparison unit 38, an integration unit 39, a phase difference adjustment unit 211, an LPF 32, a D / A 33, and a VCO 34. The phase difference adjustment unit 211, LPF 32, D / A 33, and VCO 34 are the same as those in FIG. As is clear from the comparison with FIG. 3, the PLL 120 </ b> B has a configuration in which the phase comparison unit 30 is replaced with a frequency comparison unit 38 and an integrator 39. The frequency comparison unit 38 compares the frequency of the system clock 1 with the output frequency of the VCO 34. The frequency comparison unit 38 outputs an error signal when there is a difference between the two. The integrator 39 integrates the error signal and converts it into a phase difference error signal pulse. The phase difference adjustment unit 211 may be placed outside the PLL 210B.

  Even when the main loop is configured by the frequency comparison unit 38 and the integrator 39 that perform frequency comparison, the phase control result 54 that is the output result of the phase control unit 31 is repeated until it converges to a constant value in a steady state. This means that the phase control value 53 selected by the selector 37 converges to a constant value. Furthermore, this means that the phase difference detection result 51 input to the integrator 35 becomes zero, and the same effect can be obtained.

  As described above, according to the present embodiment, the phase of the redundantly configured active system clock and standby system clock is determined based on the amount of wiring delay between backboards, the amount of change in buffer delay due to temperature change, or voltage variation. Can be matched.

  DESCRIPTION OF SYMBOLS 8 ... Back board, 9 ... Interface board, 10 ... Control board, 11 ... CLK control part, 30 ... Phase comparison part, 31 ... Phase control part, 32 ... LPF, 33 ... D / A converter, 34 ... VCO, 35 ... integrator, 36 ... phase difference detection unit, 37 ... selector, 38 ... frequency comparison unit, 39 ... integrator, 91 ... selector, 92 ... PLL, 100 ... transmission device, 200 ... system clock supply unit, 210 ... PLL, 211: Phase difference adjusting unit, 230: Buffer IC, 300: Transmission apparatus.

Claims (3)

A first clock supply unit, a second clock supply unit, a first clock from the first clock supply unit, and a second clock from the second clock supply unit are set as clock supply destinations. And connecting the first confounding signal from the first clock supply unit to the first clock supply unit and the second clock supply unit, and further from the second clock supply unit. A printed circuit board that connects two interlaced signals to the first clock supply unit and the second clock supply unit, and a clock control unit that selects one of the first clock and the second clock. A clock supply device comprising:
Each of the first clock supply unit and the second clock supply unit includes a PLL and an input / output buffer.
The PLL includes a phase difference detection unit that detects the phase difference of the clock of the own system with reference to the clock of the other system, and an integrator that integrates the detection result of the phase difference detection unit, and outputs the output of the integrator. A clock supply device that controls a phase of a clock with reference to the clock supply device. The clock supply device according to claim 1,
The input / output buffer connects the clock and the confounding signal output from the PLL to the printed circuit board, and further connects the own system confounding signal and the other system confounding signal from the printed circuit board to the PLL. Clock supply device. The clock supply device according to claim 1,
The printed circuit board has a wiring length difference between the first clock and the second clock equal to or less than a predetermined first value, and a wiring length difference between the first confounding signal and the second confounding signal. Is a predetermined second value or less.

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