JP2012044446A - Clock data recovery circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a CDR circuit making it possible to have a wide frequency variable range of data, while eliminating constraints of timing skew between the data and a clock with a simple structure.SOLUTION: A CDR circuit having an LT mode locking a clock signal in a desired frequency by using a reference clock signal and a normal operation mode synchronizing the phase of the clock signal with that of a data signal comprises: a VCO; an LPF smoothing an input signal to generate a control voltage and outputting it to the VCO; a frequency loop performing frequency comparison between the reference clock signal and the clock signal in the LT mode and outputting a signal according to the comparison result to the LPF; a phase loop performing phase comparison between the data signal and the clock signal in the normal operation mode and outputting a signal according to the comparison result to the LPF; and a frequency detection circuit adjusting a frequency range to be set to the VCO according to a frequency count value of the reference clock signal.

Description

  The present invention relates to a clock data recovery circuit that extracts a recovered clock having a phase and frequency that match serially transmitted input data and performs retiming of input data using the recovered clock.

  In recent years, the interface speed of products has been increased, and development of data transmission systems using high-speed serial communication is progressing. In such a system, the transmission signal is only data, and it is necessary to reproduce the clock synchronized with the data and extract the data on the receiving side. Since the phases of the input data and the internal clock are not synchronized, a clock data recovery (CDR) circuit is generally used to extract data (see, for example, Patent Documents 1 to 3). .

JP 2001-126507 A JP-A-2-203622 JP 2008-252616 A

  Here, for example, in a video display device such as a liquid crystal television, an LVDS (Low Voltage Difference Signaling) interface is provided as an interface between the image processing device and the image display device in order to perform data transmission at high speed and low power consumption. The data transmission system used has been developed. FIG. 9 is a block diagram illustrating a configuration example of a data transmission system using an LVDS interface.

  Referring to FIG. 9, the data transmission system includes an image processing device 10, an LVDS interface 20, a timing controller chip 30, and a flat panel display 40.

  The image processing apparatus 10 is an ADC (Analog Digital Converter) 102 that converts received analog video data into a digital signal as a receiver for receiving and outputting video data supplied from an input terminal (not shown), and HDMI (High Definition Multimedia Interface) 104 and DVI (Digital Visual Interface) 106.

  A DTV (Digital Television) engine 108 converts the video data output from the receiver unit into a signal for display and outputs the signal.

  On the output side of the DTV engine 108, a plurality of (for example, four) LVDS transmission units (LVDS-Tx) 110 to 116 are provided in parallel to the DTV engine 108. Although not shown, the LVDS transmitters 110 to 116 convert a parallel signal of video data input from the DTV engine 108 into a serial signal, and convert the serial signal into two differential amplitude signals. LVDS transmitter.

  The plurality of LVDS transmission units 110 to 116 are connected to a plurality of (for example, four) LVDS reception units (LVDS-Rx) 300 to 306 arranged inside the timing controller chip 30 via the LVDS interface 20. Each is connected.

  Although not shown, the LVDS receivers 300 to 306 receive a current output as a differential amplitude signal from the corresponding LVDS transmitter as a voltage, and a serial of video data output from the LVDS receiver. And a serial / parallel conversion circuit for converting the signal into a parallel signal.

  The timing controller chip 30 further includes a timing controller 308 and an LVDS transmitter 310 in addition to the LVDS receivers 300 to 306 described above.

  The timing controller 308 controls the timing at which the video data output from the LVDS receivers 300 to 306 is output to the flat panel display 40 via the LVDS transmitter 310. The flat panel display 40 receives video data whose timing is controlled by the timing controller 308 via the LVDS receiver 400 and displays an image on the liquid crystal panel 402.

  In such a data transmission system using an LVDS interface, a pair of an LVDS transmission unit and an LVDS reception unit can perform data transmission at a high data transmission rate while minimizing electromagnetic noise.

  Here, in recent liquid crystal televisions, as represented by keywords such as full HD (High Definition image), DeepColor, and double speed processing, the transmission rate of video data has been increased, and the data transmission system shown in FIG. However, it is required to cope with an increase in transmission rate.

  On the other hand, the LVDS interface requires that the clock and data are synchronized with each other, and therefore, the restriction on the timing skew between the clock and data becomes severe as the data transmission rate (ie, frequency) increases. As a result, there is a risk that a timing violation will occur and the operation limit will be reached.

  In order to avoid such a problem, it is effective to increase the number of data channels without increasing the clock frequency. However, an increase in the number of data channels corresponds to an increase in the number of pairs of LVDS transmitters and LVDS receivers, so that timing violations can be avoided by increasing the number of LVDS pairs. There is a problem that the size and cost of the integration) increase, and the cost increases due to an increase in the number of peripheral components such as harnesses and receptacles.

  In the LVDS interface, an LVDS transmission unit generates a dedicated clock for LVDS transfer, samples a parallel signal for each cycle of the LVDS transfer dedicated clock, converts it into a serial signal, and transfers the serial signal to the LVDS reception unit. Therefore, there is a problem that EMI becomes large.

  Here, an interface that does not require a dedicated clock is, for example, PCI express (Peripheral Component Interconnect), which is a serial interface standard used for PCs (Personal Computers). In PCI express, the clock is removed and only data is transmitted using a transmission line, thereby eliminating the skew restriction between the data and the clock and at the same time reducing the EMI. Specifically, in PCI express, a clock can be extracted from data on the receiving unit side by fixing the frequency at which the data is transmitted.

  However, the frequency of the video data input to the LVDS transmission unit and the video data output from the LVDS reception unit, such as a video display device such as a liquid crystal television, is greatly changed depending on the resolution of the video data. When applied to the presupposed interface, it is necessary to perform frequency conversion of the clock in each of the LVDS transmission unit and the LVDS reception unit, which may cause a problem that the circuit configuration becomes complicated. As a result, there has been a problem that it is difficult to apply PCI express to applications in which the frequency variable range of data is wide like a liquid crystal television.

  Note that the above Patent Documents 1 to 3 do not mention any problems related to the restriction of timing skew between data and clock and the frequency variable range of data in a high-speed serial interface.

  Therefore, the present invention has been made in order to solve the above-described problems, and an object of the present invention is to eliminate a restriction on timing skew between data and a clock with a simple configuration and to widen a frequency variable range of data. It is to provide a CDR circuit capable of

  According to one aspect of the present invention, a clock data recovery circuit that generates and outputs a clock signal for extracting data from a serially transmitted data signal, the clock data recovery circuit receiving a predetermined reference clock signal An input control voltage having a first mode for locking the clock signal to a desired frequency using and a second mode for phase-locking the clock signal to the data signal in the locked state of the clock signal. A voltage-controlled oscillation circuit that generates and outputs a clock signal, a smoothing circuit that generates a control voltage by smoothing the input signal and outputs the control voltage to the voltage-controlled oscillation circuit, During execution of mode 1, frequency comparison between the reference clock signal and the clock signal is performed, and a signal corresponding to the comparison result is generated. The phase comparison circuit that outputs the data to the smoothing circuit by performing the phase comparison between the data signal and the clock signal during the execution of the second mode and the frequency comparison circuit unit that outputs to the smoothing circuit. A circuit unit and a frequency detection circuit that counts the frequency of the reference clock signal during the execution of the first mode and adjusts the frequency range set in the voltage-controlled oscillation circuit according to the count value.

  According to the present invention, it is possible to eliminate the restriction of the timing skew between the clock and the data with a simple configuration, and to widen the frequency variable range of the data.

It is a figure explaining the outline | summary of the data transmission system to which the CDR circuit which concerns on Embodiment 1 of this invention is applied. It is a figure which shows the structure of the CDR circuit mounted in an LVDS receiving part. FIG. 3 is a diagram illustrating an internal configuration example of a VCO in FIG. 2. It is a figure which shows an example of a VCO control voltage characteristic. It is a figure which shows the structure of the CDR circuit which concerns on Embodiment 2 of this invention. It is the figure which showed the internal structural example of VCDL in FIG. It is a figure which shows the structure of the CDR circuit which concerns on Embodiment 3 of this invention. FIG. 8 is a timing chart showing an operation example of the CDR circuit of FIG. 7. FIG. It is a block diagram which shows the structural example of the data transmission system using an LVDS interface.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. It should be noted that the same or corresponding parts in the drawings are denoted by the same reference numerals and description thereof will not be repeated.

[Embodiment 1]
FIG. 1 is a diagram illustrating an outline of a data transmission system to which a CDR circuit according to Embodiment 1 of the present invention is applied. In the first to third embodiments described below, a configuration in which the CDR circuit 50 is mounted on the LVDS receiver 300 in the data transmission system including the LVDS interface illustrated in FIG. 8 will be described as an example of application of the CDR circuit.

  Referring to FIG. 1, LVDS transmission section 110 multiplexes a reference clock signal CLKr and a data signal DATA, which are signals transmitted between apparatuses, and converts them into a differential amplitude signal.

  The LVDS transmitter 110 and the LVDS receiver 300 are connected via two differential signal cables (not shown). A resistor for converting a differential amplitude signal output as a current from the LVDS transmission unit 110 into a voltage is connected between the two cables. The current signal is converted into a voltage signal by a resistor and input to the LVDS receiver 300. This voltage signal is interpreted as “1” or “0” depending on the direction of current flow through the resistor.

  The LVDS receiver 300 includes an LVDS receiver that receives the differential amplitude signal output from the LVDS transmitter 110. The LVDS receiver includes a CDR circuit 50. The CDR circuit 50 receives the differential amplitude signal and generates a clock signal CLK synchronized with the data signal DATA by an internal PLL (Phase Locked Loop) circuit. The CDR circuit 50 outputs the generated clock signal CLK together with the data signal DATA.

FIG. 2 is a diagram illustrating a configuration of the CDR circuit 50 mounted on the LVDS receiving unit 300.
Referring to FIG. 2, the CDR circuit 50 includes a frequency phase comparator (FPD) 60, a phase comparator (PD) 74, charge pump circuits (CP) 62 and 76, a selector 64, and a loop filter (LPF). ) 68, a voltage controlled oscillator (VCO) 70, frequency dividers 72, 80 and 82, and lock detection circuits (LD) 66 and 78.

  In the CDR circuit 50 of FIG. 2, a PLL is used to generate and output a clock signal for extracting data from the serially transmitted data signal. Specifically, the frequency phase comparator 60, the charge pump circuit (CP 1) 62, the loop filter 68, the VCO 70 and the frequency divider 72 are the reference clock signal CLKr from the LVDS transmission unit 110 and the output signal of the frequency divider 72. The “frequency loop 52” is configured to compare the phase and the frequency of the output clock signal CLK and adjust the frequency of the output clock signal CLK from the VCO 70 according to the comparison result. On the other hand, the phase comparator 74, the charge pump circuit CP2, the loop filter 68, the VCO 70, and the frequency divider 80 compare the phases of the data signal DATA and the output signal of the frequency divider 82, and according to the comparison result, the VCO 70. The “phase loop 54” is configured to adjust the phase of the output clock signal CLK from. The frequency loop 52 and the phase loop 54 are alternatively selected by the selector 64 according to the lock signal FLOCK from the lock detection circuit (LD1) 66.

  The data transmission system according to the first embodiment includes a “normal operation mode” for transmitting the data signal DATA serially transmitted through the LVDS interface to the flat panel display, and an LVDS interface before executing the normal operation mode. “Link-Training (LT) mode” for establishing communication using the. When the data transmission system starts to operate, the LVDS receiver 300 executes the LT mode in order to generate a clock signal CLK having a desired frequency. When the clock signal CLK is locked to a desired frequency by executing the LT mode, an LT mode end flag is transmitted from the LVDS receiver 300 to the LVDS transmitter 110. In response to receiving the LT mode end flag, when the LT mode is switched to the normal operation mode, the LVDS transmission unit 110 transmits the data signal DATA to the LVDS reception unit 300.

The operation of the CDR circuit in the LT mode and the normal operation mode will be described below.
1. LT Mode When the LT mode is executed, the LVDS transmitter 110 generates a predetermined reference clock signal CLKr and transmits it to the LVDS receiver 300. The reference clock signal CLK is composed of a clock pattern (for example, D10.2 pattern) in which “0” and “1” are alternately repeated, and the LVDS transmission unit 110 has a frequency that is ½ of the maximum operation clock frequency. Is generated as follows.

  In the LT mode, the CDR circuit 50 of the LVDS receiver 300 operates using the frequency loop 52. In the frequency loop 52, the PLL circuit can be locked to the normal operating frequency using the reference clock signal CLKr transmitted from the LVDS transmitter 110.

  Specifically, in the frequency loop 52, the frequency phase comparator 60 compares the phase and frequency of the reference clock signal CLKr from the LVDS transmission unit 110 and the output clock signal CLK of the VCO 70 divided by the frequency divider 72. Then, an error pulse signal with a duty corresponding to the frequency and phase difference of these signals is output. The error pulse signal includes an UP signal indicating a phase advance of the reference clock signal CLKr with respect to the clock signal CLK, and a DOWN signal indicating a phase delay of the reference clock signal CLKr with respect to the clock signal CLK. The UP signal becomes H (logic high) level when the phase of the reference clock signal CLKr is advanced with respect to the clock signal CLK, and becomes L (logic low) level when the phase is not advanced. The DOWN signal is at the H level when the phase of the reference clock signal CLKr is delayed with respect to the clock signal CLK, and is at the L level when not delayed.

  The charge pump circuit (CP1) 62 increases or decreases the voltage output to the loop filter 68 in accordance with the error pulse signal. Specifically, the charge pump circuit 62 flows current into the loop filter 68 when the UP signal from the frequency phase comparator 60 is at the H level. As a result, charges are accumulated in the loop filter 68. On the other hand, when the DOWN signal from the frequency phase comparator 60 is at the H level, the charge pump circuit 62 draws a current from the loop filter 68, thereby releasing the charge accumulated in the loop filter 68.

  The loop filter 68 is a circuit for stabilizing loop control, and removes a high-frequency component superimposed on a DC (Direct Current) voltage changed by the charge pump circuit 62 (or 76), thereby performing single-ended VCO control. The voltage is input to the VCO 70.

  The VCO 70 generates an oscillation frequency corresponding to the VCO control voltage from the loop filter 68. The VCO 70 outputs the generated clock signal CLK having the oscillation frequency to the outside and also to the frequency divider 72 by a single end.

  The frequency divider 72 multiplies the clock signal CLK from the VCO 70 by a factor of 1 / n (n is a natural number of 2 or more), and feeds back the multiplied clock signal CLK to the frequency phase comparator 60.

  The lock detection circuit (LD1) 66 monitors the error pulse signal (UP signal, DOWN signal) output from the frequency phase comparator 60, and determines whether the clock signal CLK is locked to a desired frequency based on the error pulse signal. To detect. When it is determined that the clock signal CLK is not locked to a desired frequency, the lock detection circuit 66 generates an L level lock signal FLOCK and outputs it to the selector 64. On the other hand, when it is determined that the clock signal CLK is locked to a desired frequency, an H level lock signal FLOCK is generated and output to the selector 64.

  The selector 64 is provided between the charge pump circuit (CP 1) 62 and the charge pump circuit (CP 2) 76 and the loop filter 68. The selector 64 selects one of the output voltage of the charge pump circuit (CP1) 62 and the output voltage of the charge pump circuit (CP2) 76 in accordance with the lock signal FLOCK input from the lock detection circuit 66 to select a loop filter. Output to 68. Specifically, the selector 64 selects the output voltage of the charge pump circuit (CP1) 62 to select a loop filter when the lock signal FLOCK is at L level, that is, when the clock signal CLK is not locked to a desired frequency. Output to 68. On the other hand, when the lock signal FLOCK is at the H level, that is, when the clock signal CLK is locked to a desired frequency, the output voltage of the charge pump circuit (CP2) 76 is selected and output to the loop filter 68.

  With this configuration, the CDR circuit 50 performs the pull-in operation so that the frequency loop 52 is exclusively active during execution of the LT mode and the output clock signal CLK of the VCO 70 has a desired frequency. . The lock detection circuit 66 keeps the lock signal FLOCK at L level until the output clock signal CLK reaches a desired frequency. Therefore, the oscillation frequency of the VCO 70 is adjusted according to the frequency difference between the reference clock signal CLKr from the LVDS transmission unit 110 and the clock signal CLK fed back.

  When detecting that the output clock signal CLK has reached a desired frequency, the lock detection circuit 66 raises the lock signal FLOCK from the L level to the H level. The lock detection circuit 66 outputs the lock signal FLOCK to the selector 64 and also outputs it to the LVDS transmitter 110 as an “LT mode end flag”. When receiving the LT mode end flag, the LVDS transmission unit 110 switches the data transmission system to the normal operation mode. In the normal operation mode, the LVDS transmission unit 110 transmits, instead of the reference clock signal CLKr, a data signal DATA generated by encoding actual video data to the LVDS reception unit 300 via the LVDS interface. In the CDR circuit 50, the phase loop 54 is exclusively active during execution of the normal operation mode. The operation of the CDR circuit 50 in the normal operation mode will be described later.

(VCO configuration)
FIG. 3 is a diagram showing an example of the internal configuration of the VCO 70 in FIG.

  Referring to FIG. 3, VCO 70 includes four current sources 701, four inverter circuits 702, four current sources 703, and control circuit 700.

  The four inverter circuits 702 are connected in series in a ring shape to constitute a ring oscillator. A corresponding current source 701 is connected between the power supply potential VCC line and the power supply terminal of each inverter circuit 702. A corresponding current source 703 is connected between each inverter circuit 702 and a ground potential line. Each inverter circuit 702 has a delay time determined by corresponding current sources 701 and 703. A clock signal CLK is output from the output node of the inverter circuit 702.

  The control circuit 700 adjusts the oscillation frequency of the ring oscillator by controlling the current values of the current sources 701 and 703 in accordance with the control voltage VCin from the loop filter 68 (FIG. 2).

  Here, it is assumed that the data transmission system according to the first embodiment is applied to a video display device such as a liquid crystal television. In this case, video data input from an external video source to the image processing apparatus has various formats. For example, in the case of a liquid crystal television, the format of video data ranges from a low resolution (480i) of SDTV (Standard Definition Television) system to a high resolution (1080P) of HDTV (High Definition Television) system. Therefore, in the CDR circuit 50, the VCO 70 needs to cover a wide range of oscillation frequencies in order to generate a clock signal CLK multiplied by a predetermined frequency from the frequency of video data of various formats.

  FIG. 4 is a diagram illustrating an example of VCO control voltage characteristics. In FIG. 4, the horizontal axis indicates the VCO control voltage VCin, and the vertical axis indicates the oscillation frequency of the VCO 70.

  Referring to FIG. 4, in the characteristic indicated by broken line 11, the oscillation frequency f changes sharply with respect to the VCO control voltage VCin, and a high gain is obtained as the VCO. As a result, the VCO can generate a wide range of oscillation frequencies. On the other hand, however, when the frequency of the input video data varies greatly depending on the resolution of the video data, such as a video display device such as a liquid crystal television, the VCO oscillations to cover the video data frequency range. A wide frequency range is not always easy in circuit design. Note that it is not preferable to perform clock frequency conversion like PCI express in terms of making the circuit configuration complicated.

  In order to avoid such problems and to realize a wide range of oscillation frequencies with a simple configuration, in the first embodiment, as shown by solid lines k1, k2, and k3 in FIG. 4, oscillation with respect to the same VCO control voltage is performed. A plurality of VCO control voltage characteristics having different frequency ranges are provided, and an optimum characteristic is selected from the plurality of characteristics according to the frequency of the input video data.

  Specifically, the frequency detection circuit (FD1) 84 counts the frequency of the reference clock signal CLKr divided by the frequency divider 82 and adjusts the frequency range set in the VCO 70 according to the count value. At this time, the system clock CLKsys is input to the frequency detection circuit 84 as a frequency counting pulse. The timing controller chip 30 including the CDR circuit 50 operates with this system clock CLKsys. The system clock CLKsys is higher than the oscillation frequency of the VCO 70 and is a known fixed frequency clock. The frequency detection circuit 84 detects the frequency of the reference clock signal CLKr by counting the reference clock signal CLKr divided by the frequency divider 82 with the system clock CLKsys. When the control circuit 700 receives the frequency of the reference clock signal CLKr detected by the frequency detection circuit 84, the control circuit 700 selects an appropriate frequency from the plurality of VCO control voltage characteristics (k1, k2, k3 in FIG. 4) stored in advance. One VCO control voltage characteristic is selected. Then, the control circuit 700 adjusts the oscillation frequency of the ring oscillator based on the selected VCO control voltage characteristic.

  Since the reference clock signal CLKr corresponds to ½ of the maximum operating clock frequency, the output clock signal CLK of the VCO 70 is transmitted to the LVDS transmission unit 110 by setting the frequency divider 82 to “2”. It can be locked to a frequency corresponding to the rate.

  With such a configuration, for example, in a liquid crystal television, a CDR circuit can be used in a wide frequency range corresponding to video data from low resolution (480i) 0.5 Gbps / lane to high resolution (1080P) 9 Gbps / lane. 50 can be locked. In order to facilitate the setting of the frequency range of the VCO 70, the control circuit 700 of the VCO 70 may include a 128 divider circuit.

2. Normal Operation Mode When the normal operation mode is executed, the LVDS transmission unit 110 transmits a data signal DATA generated by encoding actual video data to the LVDS reception unit 300. The CDR circuit 50 of the LVDS receiver 110 operates using the phase loop 54. In the phase loop 54, the phase of the output clock signal CLK of the VCO 70 can be adjusted using the data signal DATA transmitted from the LVDS transmission unit 110.

  In the normal operation mode, unlike the LT mode, a signal encoded with actual video data is transmitted instead of the D10.2 pattern corresponding to video data (a clock pattern in which “0” and “1” are alternately repeated). Is done. Therefore, feedback control of the clock signal CLK is executed when the timing at which the signal level of the data signal DATA changes, for example, when the rising edge from the L level to the H level is detected.

  In the data transmission system according to the first embodiment, since the 8B10B encoding system is adopted for the interface, data transition is always guaranteed once every six data. Therefore, the phase lock does not continue to be released, and the phase lock is periodically applied. Therefore, the phase relationship between the input data signal DATA and the clock signal CLK can be maintained.

  Specifically, referring to FIG. 2, in the phase loop 54, the phase comparator 74 compares the data signal DATA from the LVDS transmission unit 110 and the output clock signal CLK of the VCO 70 divided by the frequency divider 80. The phases are compared, and an error pulse signal with a duty corresponding to the phase difference between these signals is output. When the phase of the data signal DATA is advanced with respect to the clock signal CLK, an H level UP signal is output. On the other hand, when the phase of the data signal DATA is delayed with respect to the clock signal CLK, an H level DOWN signal is output.

  The charge pump circuit (CP2) 76 increases or decreases the voltage output to the loop filter 68 according to the error pulse signal. The selector 64 selects the output voltage of the charge pump circuit 76 according to the H level lock signal FLOCK input from the lock detection circuit 66 and outputs it to the loop filter 68. Therefore, charge pump circuit 76 feeds current into loop filter 68 when the UP signal from phase comparator 74 is at the H level. As a result, charges are accumulated in the loop filter 68. On the other hand, when the DOWN signal from the frequency phase comparator 60 is at the H level, the charge pump circuit 62 draws a current from the loop filter 68, thereby releasing the charge accumulated in the loop filter 68.

  The loop filter 68 removes a high-frequency component superimposed on the DC voltage changed by the charge pump circuit 76 and inputs it to the VCO 70 as a single-ended VCO control voltage.

  The VCO 70 generates an oscillation frequency corresponding to the VCO control voltage from the loop filter 68. The VCO 70 outputs the generated clock signal CLK having the oscillation frequency to the outside at a single end and also to the frequency divider 80.

  The frequency divider 80 multiplies the clock signal CLK from the VCO 70 by 1 / n times, and feeds back the multiplied clock signal CLK to the phase comparator 74.

  The lock detection circuit (LD2) 78 monitors the error pulse signal (UP signal, DOWN signal) output from the phase comparator 74, and whether the clock signal CLK is phase-synchronized with the data signal DATA based on the error pulse signal. Detect whether or not. When it is detected that the phase of the clock signal CLK is out of synchronization with the data signal DATA, the lock detection circuit 78 outputs an H level as an interrupt request (Interrupt Request: IRQ) for returning the operation mode to the LT mode described above. An activated control signal LDET_PLOOP is generated. This control signal LDET_PLOOP is transmitted to the LVDS transmission unit 110 via the LVDS interface. When receiving the control signal LDET_PLOOP, the LVDS transmission unit 110 switches to the LT mode and transmits the reference clock signal CLKr toward the LVDS reception unit 300 again.

  However, the CDR circuit 50 can be intentionally fixed to the phase loop 54 so that the CDR circuit 50 does not return to the frequency loop 52 when the phase of the clock signal CLK is not synchronized due to a sudden external factor such as noise. Specifically, in the configuration of FIG. 2, by inputting the signal FLOOP_OFF for inactivating the frequency loop 52 from the LVDS transmission unit 110 to the lock detection circuit 66, the phase loop 54 is activated in the normal operation mode. Can be fixed.

  In the normal operation mode, the frequency detection circuit (FD2) 86 can always detect whether or not the oscillation frequency of the VCO 70 is a desired frequency. The system clock CLKsys is input to the frequency detection circuit 86 as a frequency counting pulse. The frequency detection circuit 86 detects the frequency of the clock signal CLK by counting the output clock signal CLK of the VCO 70 with the system clock CLKsys. When it is determined that the frequency of the detected clock signal CLK is out of the desired frequency, the frequency detection circuit 86 transmits the determination result to the LVDS transmission unit 110. Thereby, the normal operation mode is switched to the LT mode.

3. Here, the resolution of video data is changed according to user settings in applications such as liquid crystal televisions. At this time, the transmission rate of the video data may be changed. When the transmission rate of the video data is changed, the LVDS transmission unit 110 temporarily stops data transmission and returns from the normal operation mode to the LT mode.

  The CDR circuit 50 of the LVDS receiver 300 may be configured to initialize the CDR circuit 50 when the frequency detection circuit 84 detects that data transmission from the LVDS transmitter 110 is stopped.

  However, when the sequence as described above is executed, it takes time until the image is output due to the re-execution of the LT mode, which may cause a problem in the system. Accordingly, when the resolution of the video data is changed, the frequency of the data signal DATA is changed by polling the data signal DATA while maintaining the normal operation mode while fixing the phase loop 54 without returning to the LT mode. By detecting and setting the oscillation frequency of the VCO 70 to the frequency of the data signal DATA after the change, the frequency of the clock signal CLK can follow the change in the resolution of the video data.

  In the first embodiment, the CDR circuit 50 shown in FIG. 2 has the charge loop circuits CP1 and CP2 and the lock detection circuits LD1 and LD2 provided in the frequency loop 52 and the phase loop 54, respectively. By configuring these two circuits to be shared between the frequency loop 52 and the phase loop 54, the circuit scale can be reduced.

  Further, in the CDR circuit 50 according to the first embodiment, it is possible to eliminate the crystal oscillation clock required for PCI express or the like.

  As described above, according to the CDR circuit according to the first embodiment of the present invention, the serially transmitted data is input to the frequency loop and the phase loop, and the input data is detected by detecting the frequency of the input data. The VCO range can be automatically adjusted to the optimum frequency range according to the data frequency. As a result, the restriction on the timing skew between the clock and data can be eliminated and the frequency variable range can be widened. As a result, the number of differential pairs required for high-speed transmission can be reduced, so that the number of peripheral components can be reduced to achieve downsizing and cost reduction. In addition, since the clock line can be eliminated, EMI can be reduced.

[Embodiment 2]
FIG. 5 is a diagram showing a configuration of a CDR circuit according to the second embodiment of the present invention.

  Referring to FIG. 5, CDR circuit 50A according to the second embodiment includes VCO 70 in the oscillation circuit section of the frequency loop and the phase loop as compared with CDR circuit 50 according to the first embodiment shown in FIG. The difference is that a DLL (Delay Locked Loop) circuit is used for the phase loop 56 instead of the commonly used circuit configuration. Note that the DLL circuit has advantages such as that the accumulation jitter is smaller than that of the PLL circuit, and that the stability is better than that of the PLL circuit, so that it is easy to design.

  Similar to the data transmission system according to the first embodiment, the data transmission system according to the second embodiment includes a normal operation mode and an LT mode. The operation of the CDR circuit in the LT mode and the normal operation mode will be described below.

1. LT Mode When the LT mode is executed, the LVDS transmitter 110 generates a predetermined reference clock signal CLKr and transmits it to the LVDS receiver 300. The CDR circuit 50 </ b> A of the LVDS receiver 300 operates using the frequency loop 52. In the frequency loop 52, the PLL circuit can be locked to the normal operation frequency using the reference clock signal CLK transmitted from the LVDS transmission unit 110.

  Specifically, in the frequency loop 52, the frequency phase comparator 60 compares the phase and frequency of the reference clock signal CLKr from the LVDS transmission unit 110 and the output clock signal CLK of the VCO 70 divided by the frequency divider 72. Then, an error pulse signal (UP signal, DOWN signal) with a duty corresponding to the frequency and phase difference of these signals is output.

  The charge pump circuit (CP1) 62 increases or decreases the voltage output to the loop filter 680 according to the error pulse signal. The loop filter 680 removes a high-frequency component superimposed on the DC voltage changed by the charge pump circuit 62 and inputs it to the VCO 70 as a single-ended VCO control voltage.

  The VCO 70 generates an oscillation frequency corresponding to the VCO control voltage from the loop filter 68. The VCO 70 outputs the generated clock signal CLK having the oscillation frequency to the outside and also to the frequency divider 72 by a single end.

  The frequency divider 72 multiplies the clock signal CLK from the VCO 70 by a factor of 1 / n, and feeds back the multiplied clock signal CLK to the frequency phase comparator 60.

  The lock detection circuit (LD1) 66 monitors the error pulse signal (UP signal, DOWN signal) output from the frequency phase comparator 60, and the output clock signal CLK is locked to a desired frequency based on the error pulse signal. Detect whether or not. When it is determined that the output clock signal CLK is not locked to a desired frequency, the lock detection circuit 66 generates an L level lock signal FLOCK and outputs it to the LVDS transmitter 110.

  When detecting that the output clock signal CLK has reached a desired frequency, the lock detection circuit 66 raises the lock signal FLOCK from the L level to the H level. The lock detection circuit 66 outputs the lock signal FLOCK to the LVDS transmission unit 110 as an LT mode end flag. When receiving the LT mode end flag, the LVDS transmission unit 110 switches the data transmission system to the normal operation mode. In the normal operation mode, the LVDS transmission unit 110 transmits, instead of the reference clock signal CLKr, a data signal DATA generated by encoding actual video data to the LVDS reception unit 300 via the LVDS interface.

2. Normal Operation Mode When the normal operation mode is executed, the LVDS transmission unit 110 transmits a data signal DATA generated by encoding actual video data to the LVDS reception unit 300. The CDR circuit 50 </ b> A of the LVDS receiver 300 operates using the phase loop 56. In the phase loop 54, the phase of the output clock signal CLK can be adjusted using the data signal DATA transmitted from the LVDS transmitter 110.

  Specifically, referring to FIG. 5, in phase loop 56, phase comparator 74 compares data signal DATA from LVDS transmitter 110 and output clock signal CLK of VCO 70 that has been frequency-divided by frequency divider 80. The phases are compared, and an error pulse signal (UP signal, DOWN signal) with a duty corresponding to the phase difference between these signals is output.

  The charge pump circuit (CP2) 76 increases or decreases the voltage output to the loop filter 682 in accordance with the error pulse signal. The loop filter 682 removes a high-frequency component superimposed on the DC voltage changed by the charge pump circuit 76 and inputs the high-frequency component to a VCDL (Voltage Controlled Delay Line) 88.

  The VCDL 88 delays the output clock signal CLK of the VCO 70 in accordance with the control voltage from the loop filter 682 and outputs the delayed output clock signal CLK to the frequency divider 80. FIG. 6 is a diagram showing an example of the internal configuration of the VCDL 88 in FIG.

  Referring to FIG. 6, VCDL 88 includes five current sources 801, five buffer circuits 802, five current sources 803, and control circuit 800.

  Five buffer circuits 802 are connected in series to delay the clock signal CLK from the VCO 70. A corresponding current source 801 is connected between the power supply potential VCC line and the power supply terminal of each buffer circuit 802. A corresponding current source 803 is connected between each buffer circuit 802 and a ground potential line. Each buffer circuit 802 has a delay time determined by the corresponding current sources 801 and 803. A delayed clock signal CLK is output from the output node of the buffer circuit 802.

  The control circuit 800 adjusts the delay time by controlling the current values of the current sources 801 and 803 in accordance with the control voltage VCin from the loop filter 682 (FIG. 5).

  The frequency divider 80 multiplies the clock signal CLK from the VCDL 88 by 1 / n times, and feeds back the multiplied clock signal CLK to the phase comparator 74.

  The lock detection circuit (LD2) 78 monitors the error pulse signal (UP signal, DOWN signal) output from the phase comparator 74, and whether the clock signal CLK is phase-synchronized with the data signal DATA based on the error pulse signal. Detect whether or not. When it is detected that the phase of the clock signal CLK is not synchronized with the data signal DATA, the lock detection circuit 78 is activated to the H level as an interrupt request IRQ for returning the operation mode to the LT mode described above. A signal LDET_PLOOP is generated. This control signal LDET_PLOOP is transmitted to the LVDS transmission unit 110 via the LVDS interface. When receiving the control signal LDET_PLOOP, the LVDS transmission unit 110 switches to the LT mode and transmits the reference clock signal CLKr again to the LVDS reception unit.

  However, it can be intentionally fixed to the phase loop 54 so that it does not return to the frequency loop 52 when the phase of the clock signal CLK is not synchronized due to sudden external factors such as noise. In the configuration of FIG. 5, by inputting the signal FLOOP_OFF for inactivating the frequency loop 52 from the LVDS transmission unit 110 to the lock detection circuit 66, the phase loop 56 can be fixed to the active state in the normal operation mode. it can.

  The frequency detection circuit (FD2) 86 always detects whether or not the oscillation frequency of the VCO 70 is a desired frequency. When it is determined that the frequency of the detected clock signal CLK is out of the desired frequency, the frequency detection circuit 86 transmits the determination result to the LVDS transmission unit 110. Thereby, the normal operation mode is switched to the LT mode.

3. As described in the first embodiment, when the video data transmission rate is changed by changing the resolution of the video data according to the user setting, the LVDS transmission unit 110 receives the data. The transmission is temporarily stopped and the normal operation mode is returned to the LT mode.

  Alternatively, the frequency detection circuit 84 may detect that the data transmission from the LVDS transmission unit 110 is stopped and reset the CDR circuit 50A. Alternatively, when the resolution of the video data is changed, the frequency of the data signal DATA is changed by polling the data signal DATA while maintaining the normal operation mode without fixing the LT mode and returning to the phase loop 56. By detecting and setting the oscillation frequency of the VCO 70 to the frequency of the data signal DATA after the change, the frequency of the clock signal CLK can follow the change in the resolution of the video data.

  As described above, according to the CDR circuit according to the second embodiment of the present invention, the serially transmitted data is input to the frequency loop and the phase loop, and the input data is detected by detecting the frequency of the input data. The VCO range can be automatically adjusted to the optimum frequency range according to the data frequency. As a result, the restriction on the timing skew between the clock and data can be eliminated and the frequency variable range can be widened. As a result, the number of differential pairs required for high-speed transmission can be reduced, so that the number of peripheral components can be reduced to achieve downsizing and cost reduction. In addition, since the clock line can be eliminated, EMI can be reduced.

[Embodiment 3]
FIG. 7 is a diagram showing a configuration of a CDR circuit according to the third embodiment of the present invention.

  Referring to FIG. 7, the CDR circuit 50B according to the third embodiment has a frequency instead of the frequency loop 52 and the phase loop 54 as compared with the CDR circuit 50 according to the first embodiment shown in FIG. The difference is that only the loop 58 is provided.

  The CDR circuit 50B includes a frequency phase comparator (FPD) 60, a charge pump circuit (CP) 92, a loop filter (LPF) 94, a VCO 70, frequency dividers 72 and 82, and a lock detection circuit (LD1) 66. And frequency detection circuits (FD) 84 and 86.

  In the CDR circuit 50B of FIG. 7, a PLL is used to generate and output a clock signal for extracting data from the serially transmitted data signal. The frequency phase comparator 60, the charge pump circuit 92, the loop filter 94, the VCO 70, and the frequency divider 72 compare the phase and frequency of the reference clock signal CLKr from the LVDS transmitter 110 and the output signal of the frequency divider 72. The “frequency loop 58” is configured to adjust the frequency of the output clock signal CLK from the VCO 70 in accordance with the comparison result.

  Similar to the data transmission system according to the first embodiment, the data transmission system according to the third embodiment includes a normal operation mode and an LT mode. The operation of the CDR circuit in the LT mode and the normal operation mode will be described below.

1. LT Mode When the LT mode is executed, the LVDS transmitter 110 generates a predetermined reference clock signal CLKr and transmits it to the LVDS receiver 300. The CDR circuit 50B of the LVDS receiver 300 operates using the frequency loop 58. In the frequency loop 58, the PLL circuit can be locked to the normal operating frequency using the reference clock signal CLKr transmitted from the LVDS transmitter 110.

  Specifically, the frequency phase comparator 60 compares the phase and frequency of the reference clock signal CLKr from the LVDS transmission unit 110 and the output clock signal CLK of the VCO 70 divided by the frequency divider 72, and these signals. An error pulse signal (UP signal, DOWN signal) with a duty corresponding to the frequency and phase difference is output.

  The charge pump circuit (CP) 92 increases or decreases the voltage output to the loop filter 94 according to the error pulse signal. The loop filter 94 removes a high-frequency component superimposed on the DC voltage changed by the charge pump circuit 92 and inputs the high-frequency component to the VCO 70 as a single-ended VCO control voltage.

  The VCO 70 generates an oscillation frequency corresponding to the VCO control voltage from the loop filter 94. The VCO 70 outputs the generated clock signal CLK having the oscillation frequency to the outside and also to the frequency divider 72 by a single end.

  The frequency divider 72 multiplies the clock signal CLK from the VCO 70 by a factor of 1 / n, and feeds back the multiplied clock signal CLK to the frequency phase comparator 60.

  The lock detection circuit (LD1) 66 monitors the error pulse signal (UP signal, DOWN signal) output from the frequency phase comparator 60, and the output clock signal CLK is locked to a desired frequency based on the error pulse signal. Detect whether or not. When it is determined that the output clock signal CLK is not locked to a desired frequency, the lock detection circuit 66 generates an L level lock signal FLOCK and outputs it to the LVDS transmitter 110.

  When detecting that the output clock signal CLK has reached a desired frequency, the lock detection circuit 66 raises the lock signal FLOCK from the L level to the H level. The lock detection circuit 66 outputs the lock signal FLOCK to the LVDS transmission unit 110 as an LT mode end flag. When receiving the LT mode end flag, the LVDS transmission unit 110 switches the data transmission system to the normal operation mode.

2. Normal Operation Mode When the normal operation mode is executed, the LVDS transmission unit 110 transmits a data signal DATA generated by encoding actual video data to the LVDS reception unit 300 instead of the reference clock signal CLKr.

  Here, the data signal DATA is not a clock pattern in which “0” and “1” are alternately repeated like the reference clock signal CLKr, but may include continuous “0” or continuous “1”. Therefore, the PLL circuit may be unlocked in the frequency loop 58 described above.

  The CDR circuit 50B according to the third embodiment includes a change point at which the signal level of the input data signal DATA changes, for example, an edge detection circuit (ED) that detects a rising edge of the data signal DATA from the L level to the H level. 90 is included. When the rising edge of the data signal DATA is detected, the edge detection circuit 90 generates an edge detection signal for enabling the frequency phase comparator 60 and inputs the edge detection signal to the frequency phase comparator 60.

FIG. 8 is a timing chart showing an operation example of the CDR circuit 50B of FIG.
Referring to FIG. 8, in the LT mode, the reference clock signal CLKr in which “0” and “1” are alternately repeated and the frequency of the clock signal CLK divided by the frequency divider 72 are compared. By controlling the VCO 70 according to the frequency difference, the output clock signal CLK of the VCO 70 can be locked to the normal operating frequency.

  On the other hand, in the normal operation mode, a random data signal DATA as shown in FIG. 8 is input to the frequency phase comparator 60. When the edge detection circuit 90 detects the rising edge of the data signal DATA (timing t11, t12 in the drawing), the edge detection circuit 90 outputs the edge detection signal activated to the H level to the frequency phase comparator 60.

  The frequency phase comparator 60 is enabled when the edge detection signal becomes H level, compares the phase of the data signal DATA and the clock signal CLK divided by the frequency divider 72, and compares the levels of these signals. An error pulse signal (UP signal, DOWN signal) with a duty corresponding to the phase difference is output.

  Note that, in the data transmission system according to the third embodiment, as in the data transmission systems according to the first and second embodiments, the 8B10B encoding system is used for the interface. Data transition is always guaranteed. Therefore, the phase lock does not continue to be released, and the phase lock is periodically applied. Therefore, the phase relationship between the input data signal DATA and the clock signal CLK can be maintained. Further, since the PLL circuit operates with the rising edge of the data signal DATA as a trigger, it is possible to prevent the phase lock from being released even if the data signal DATA is a signal in which “1” or “0” continues.

  The frequency detection circuit (FD2) 86 detects whether or not the oscillation frequency of the VCO 70 is a desired frequency. When it is determined that the frequency of the detected clock signal CLK is out of the desired frequency, the frequency detection circuit 86 transmits the determination result to the LVDS transmission unit 110. Thereby, the normal operation mode is switched to the LT mode.

3. As described in the first embodiment, when the video data transmission rate is changed by changing the resolution of the video data according to the user setting, the LVDS transmission unit 110 receives the data. The transmission is temporarily stopped and the normal operation mode is returned to the LT mode.

  Alternatively, the CDR circuit 50B may be configured to detect that the data transmission from the LVDS transmission unit 110 is stopped by the frequency detection circuit 84 and reset the CDR circuit. Alternatively, when the resolution of the video data is changed, a change in the frequency of the data signal DATA is detected by polling the data signal DATA while maintaining the normal operation mode without returning to the LT mode, and the VCO 70 oscillates. By setting the frequency to the frequency of the data signal DATA after the change, the frequency of the clock signal CLK can follow the change in the resolution of the video data.

  As described above, according to the CDR circuit of the third embodiment of the present invention, serially transmitted data is input to the frequency loop, and the frequency phase comparator is enabled when the rising edge of the data is detected. Thus, phase synchronization can be maintained by comparing the phase of the data and the clock. Further, by detecting the frequency of the input data, the VCO range can be automatically adjusted to the optimum frequency range according to the frequency of the input data. As a result, the restriction on the timing skew between the clock and data can be eliminated and the frequency variable range can be widened. As a result, the number of differential pairs required for high-speed transmission can be reduced, so that the number of peripheral components can be reduced to achieve downsizing and cost reduction. In addition, since the clock line can be eliminated, EMI can be reduced.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description of the embodiments but by the scope of claims for patent, and is intended to include meanings equivalent to the scope of claims for patent and all modifications within the scope.

  10 image processing apparatus, 20 LVDS interface, 30 timing controller chip, 40 flat panel display, 50, 50A, 50B CDR circuit, 52, 58 frequency loop, 54, 56 phase loop, 60 frequency phase comparator, 62, 76, 92 Charge pump circuit, 64 selector, 66, 78 lock detection circuit, 68, 94, 680, 682 loop filter, 72, 80, 82 frequency divider, 74 phase comparator, 84, 86 frequency detection circuit, 90 edge detection circuit, 108 DTV Engine, 110-116, 310 LVDS Transmitter, 300-306,400 LVDS Receiver, 308 Timing Controller, 402 Liquid Crystal Panel, 700,800 Control Circuit, 701, 703, 801, 803 Current Source, 702 In Over-capacitor circuit.

Claims (4)

A clock data recovery circuit that generates and outputs a clock signal for extracting data from a serially transmitted data signal,
The clock data recovery circuit uses a predetermined reference clock signal to lock the clock signal to a desired frequency, and the clock signal is phase-synchronized with the data signal in the locked state of the clock signal. A second mode for
An oscillation operation is controlled according to an input control voltage, and a voltage controlled oscillation circuit that generates and outputs the clock signal;
A smoothing circuit that smoothes an input signal to generate the control voltage and outputs the control voltage to the voltage controlled oscillation circuit;
A frequency comparison circuit unit that performs frequency comparison between the reference clock signal and the clock signal during execution of the first mode, generates a signal according to the comparison result, and outputs the signal to the smoothing circuit;
A phase comparison circuit unit that performs phase comparison between the data signal and the clock signal during execution of the second mode, generates a signal according to the comparison result, and outputs the signal to the smoothing circuit;
A clock data recovery circuit comprising: a frequency detection circuit that counts a frequency of the reference clock signal and adjusts a frequency range set in the voltage-controlled oscillation circuit according to the count value during execution of the first mode; . A clock data recovery circuit that generates and outputs a clock signal for extracting data from a serially transmitted data signal,
The clock data recovery circuit uses a predetermined reference clock signal to lock the clock signal to a desired frequency, and the clock signal is phase-synchronized with the data signal in the locked state of the clock signal. A second mode for
An oscillation operation controlled according to the input first control voltage, and a voltage controlled oscillation circuit that generates and outputs the clock signal;
A first smoothing circuit that smoothes an input signal to generate the first control voltage and outputs the first control voltage to the voltage controlled oscillation circuit;
A delay circuit whose delay time is controlled in accordance with the input second control voltage and delays the clock signal;
A second smoothing circuit that smoothes an input signal to generate the second control voltage and outputs the second control voltage to the delay circuit;
A frequency comparison circuit unit that performs frequency comparison between the reference clock signal and the clock signal during the execution of the first mode, generates a signal according to the comparison result, and outputs the signal to the first smoothing circuit; ,
A phase comparison circuit unit that performs phase comparison between the data signal and the clock signal during execution of the second mode, generates a signal according to the comparison result, and outputs the signal to the second smoothing circuit;
A clock data recovery circuit comprising: a frequency detection circuit that counts a frequency of the reference clock signal and adjusts a frequency range set in the voltage-controlled oscillation circuit according to the count value during execution of the first mode; . A clock data recovery circuit that generates and outputs a clock signal for extracting data from a serially transmitted data signal,
The clock data recovery circuit uses a predetermined reference clock signal to lock the clock signal to a desired frequency, and the clock signal is phase-synchronized with the data signal in the locked state of the clock signal. A second mode for
An oscillation operation is controlled according to an input control voltage, and a voltage controlled oscillation circuit that generates and outputs the clock signal;
A smoothing circuit that smoothes an input signal to generate the control voltage and outputs the control voltage to the voltage controlled oscillation circuit;
A frequency phase comparison circuit unit that performs a frequency comparison between the reference clock signal and the clock signal during the execution of the first mode, generates a signal according to the comparison result, and outputs the signal to the smoothing circuit;
A frequency detection circuit that counts the frequency of the reference clock signal during the execution of the first mode and adjusts a frequency range set in the voltage controlled oscillation circuit according to the count value;
An edge detection circuit for detecting that the data signal has changed to a predetermined signal level during execution of the second mode;
The frequency phase comparison circuit unit performs phase comparison between the data signal and the clock signal when the data signal changes to the predetermined signal level during execution of the second mode, and the comparison result A clock data recovery circuit that generates a signal according to the output and outputs the signal to the smoothing circuit. The voltage controlled oscillation circuit has a plurality of characteristics set such that oscillation frequencies generated by the same control voltage are different from each other,
4. The clock data recovery circuit according to claim 1, wherein the frequency detection circuit adjusts the frequency range so as to have one characteristic selected from the plurality of characteristics according to the count value. 5. .

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