JP2008219216A - Clock supply unit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To match clock phases between an active system and a standby system of a clock supply unit for supplying clocks being phase-coherent with a clock from an upper level. <P>SOLUTION: A clock supply unit includes: an active system clock supply unit 1a for outputting an active system clock being phase-coherent with a system clock; and a standby system clock supply unit 1b for outputting a standby system clock, and also includes: DPLL sections 2a, 2b for outputting clocks being phase-coherent with the system clock; variable delay circuits 4a, 4b for controlling the delay of the clocks from the above DPLL sections 2a, 2b; phase comparators 7a, 7b for comparing the phase of the active system clock for outputting via the above variable delay circuits 4a, 4b with the phase of the standby system clock; and phase comparison decision sections 5a, 5b for controlling the delay amount of the variable delay circuits 4a, 4b, based on the result of phase comparison between the active system and standby system clocks by means of the phase comparators 7a, 7b. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a clock supply apparatus having an active system clock supply apparatus and a standby system clock supply apparatus.

  A communication device that performs communication via a network executes transmission / reception processing in synchronization with a system clock. For this purpose, a system clock supply device is provided for receiving the system clock from the host device, reproducing the clock phase-synchronized with the system clock, and supplying the clock to each part in the device. In that case, in order to improve the reliability, it is common to apply a duplex configuration of the active system and the standby system.

  FIG. 12 shows a conventional clock supply apparatus to which a duplex configuration is applied. 101a and 101b are system clock supply apparatuses for the N system (active system) and E system (standby system), and 102a and 102b are DPLL units (phase synchronization). ), 103a and 103b are phase matching units, 104a and 104b are CLK (clock) distribution units, and 105a, 105b, 106a, 106b, 107a and 107b are buffers. A system clock from a host device (not shown) is input to the system clock supply devices 101a and 102b for the active system and the standby system, and a clock whose phase is synchronized with the system clock is reproduced by the DPLL units 102a and 102b, and the CLK distribution unit The active and standby clocks distributed and output from 104a and 104b are switched by the active standby switching means (not shown) to be used as operation clocks for each part in the apparatus.

  The buffer corresponds to a buffer amplifier in which the input impedance does not affect the output characteristics. The DPLL units 102a and 102b receive the system clock from the host device and the buffers 106a, 106b, 107a and 107b by the phase matching units 103a and 103b so that the output clock phases of the active system and the standby system are the same. The phase of the output clock is controlled so that the phases match, and the frequency of the system clock and the output clock are not the same. The phase matching units 103a and 103b have a configuration for performing phase comparison by dividing the output clock so as to have the same frequency as the system clock.

In the switching circuit for switching the clock between the active system and the standby system, the clock phases of the active system and the standby system are compared in advance, the phase difference and the phase advance / delay are detected, and the active system and the standby system are detected. There has been proposed means for preventing a change in the clock phase when the clock amount between the active system and the standby system is switched by setting a delay amount with respect to each clock (see, for example, Patent Document 1). Also, the clock from the host device is input to the clock receiver of the active system and the standby system, and the clock receiver splits into two, one is the own system and the other is the clock distribution between the active system and the standby system. The active clock is input to the selector as it is, the standby clock is input to the selector via the delay element, the clock selected by the selector is input to the phase control oscillator, and the selector is Means has been proposed for processing so that the phases of the clocks of the active system and the standby system that are input to the phase-controlled oscillator are the same (see, for example, Patent Document 2).
Japanese Patent Laid-Open No. 5-2438 JP-A-5-244132

  In a clock supply device that has a redundant configuration of the active system and the standby system and requires high-accuracy frequency stability, when either one of the redundant configurations is used as an active system, clock stop or abnormal frequency output When this occurs, the system is switched to the other standby system. At this time, the clock phase before switching and the clock phase after switching often change. For example, in a mobile phone base station, when a sudden clock phase change occurs due to a clock switch between the active system and the standby system, a voice interruption occurs in the case of a voice call, and in the case of data communication Data loss occurs. In particular, there is a problem that the amount of missing data increases with an increase in data communication speed. In addition, when data is lost in packet communication, retransmission processing can be performed, but data loss in videophone and other real-time video distribution services results in an abnormal state in which mosaic block noise appears on the display screen. There is a problem that the influence of a sudden change in the clock phase becomes larger than in the case of only voice call.

  The clock supply device generally uses a PLL circuit that synchronizes the output clock phase with the reference phase clock by comparing the phase of the reference phase clock with the generated clock. Although the phase fluctuation can be reduced by lowering the cut-off frequency, in this case, there is a problem that the operation start time becomes longer because the phase synchronization pull-in time increases. In the conventional clock supply device as shown in FIG. 12, the phase adjustment is performed on the input side of the system clock, but the delay time of various electronic circuit elements to the output side varies, and the temperature Since there are fluctuations in device characteristics due to fluctuations, operating voltage fluctuations, aging, etc., considering these factors, even when designing a circuit so that it is not affected by fluctuation factors, it becomes very complicated and the circuit design fails. In addition, the circuit design using inexpensive circuit elements becomes almost impossible. Although a design method using a statistical distribution method such as a mean square hull can be used, it has poor feasibility due to an increase in the defect rate for mass-produced consumer devices.

  Also, in various communication devices, it is common to configure by mounting various functional units of structural units such as units, packages, boards, etc., and a clock is distributed from a clock supply device to a plurality of device structural units. Therefore, providing a phase matching means for switching between the active and standby clocks for each device configuration unit of each clock distribution destination has a problem of increasing the system cost.

  The present invention solves the above-mentioned conventional problems, and in the clock generating means with the working and spare redundant configuration, the working and spare clock phases are made to coincide on the clock output end side, and the working is used. An object is to maintain a constant phase at the time of standby switching.

  The clock supply device of the present invention has an active system clock supply device that outputs an active clock that is phase-synchronized with a system clock from a host device, and a standby system clock supply device that outputs a standby clock, The system clock supply device for the active system and the standby system includes a DPLL unit that outputs a clock that is phase-synchronized with the system clock, a variable delay circuit that delay-controls the clock from the DPLL unit, and an output via the variable delay circuit. A phase comparator for comparing phases of the active clock and the standby clock, and a phase comparison result of the active clock and the standby clock by the phase comparator to control a delay amount of the variable delay circuit And a phase comparison / determination unit.

  The phase comparison unit inputs an integration circuit that outputs a voltage value corresponding to the phase difference between the active clock and the standby clock, and inputs the active clock to the data terminal and the standby clock to the clock terminal, A standby system advance detection signal is provided with a flip-flop that outputs a standby system delay detection signal, and a flip-flop that outputs the standby system advance detection signal by inputting the active system clock to the clock terminal and the standby system clock to the data terminal. And a latch circuit that holds a standby system delay detection signal, and the other can be reset by holding one of the detection signals.

  The phase comparator includes a counter circuit that samples the phase difference between the active clock and the standby clock using a high-speed sampling clock to obtain a count value corresponding to the phase difference, and outputs the phase difference amount as a digital value. .

  The variable delay circuit has a configuration in which a plurality of delay lines having different delay amounts and a bypass line having a delay amount of zero are selected by a selector and connected in series. The delay amount is controlled by the step amount of the delay line.

  The phase comparison / determination unit for controlling the delay amount of the variable delay circuit uses a delay amount intermediate between the minimum delay amount and the maximum delay amount of the variable delay circuit as a reference delay amount, and this reference delay amount is used as the active system clock. This is selected when the phase difference between the standby clock and the standby clock is zero. When the standby phase of the standby clock is detected, the delay with respect to the standby clock is increased from the reference delay amount. When the delayed phase of the standby clock is detected, the reference delay amount is detected. It is possible to provide a control configuration for further reducing the delay amount with respect to the standby system clock.

  An active system clock and a standby system clock that are phase-synchronized with the system clock from the host apparatus are generated, and when active, the active system clock is supplied to each part in the apparatus. The output terminal of the active system clock supply apparatus 1a The variable delay circuit is configured so that the phases of the active clock from the CLK distribution unit 6a and the standby system clock from the CLK distribution unit 6b at the output end of the standby system clock supply device 1b are compared, and the phases match. 4a and 4b for controlling the phase of the active clock at the output end of the system clock supply device 1a and the standby clock at the output end of the system clock supply device 1b, and the temperature change of the characteristics of the circuit elements constituting each part It is possible to match regardless of the secular change and therefore no phase fluctuation occurs when the active clock and the standby clock are switched. Et al, it is possible to stabilize the operation of the apparatus in each section.

  Referring to FIG. 1, the clock supply apparatus according to the present invention includes an active system clock supply apparatus 1a that outputs a working clock that is phase-synchronized with a system clock from a host apparatus, and a standby system clock that outputs a standby clock. The system clock supply devices 1a and 1b of the active system and the standby system include a DPLL unit 2a and 2b that outputs a clock that is phase-synchronized with the system clock, and a clock from the DPLL unit 2a and 2b. Variable delay circuits 4a and 4b for delay control, phase comparison units 7a and 7b for comparing the phases of the active clock and the standby clock output via the variable delay circuits 4a and 4b, and the phase comparison unit 7a , 7b controls the delay amount of the variable delay circuits 4a, 4b based on the phase comparison result between the active clock and the standby clock. It includes phase comparison determination unit 5a, and 5b, respectively.

  FIG. 1 is an explanatory diagram of a first embodiment of the present invention, wherein 1a is an N-system (active system) system clock supply device, 1b is an E-system (standby system) system clock supply device, and 2a and 2b are DPLL units. (Phase synchronization unit), 3a and 3b are phase matching units, 4a and 4b are variable delay circuits, 5a and 5b are phase determination units, 6a and 6b are CLK distribution units that distribute the clock to each unit in the apparatus, 7a and 7b Denotes a phase comparison unit, and 8a, 8b, 9a, 9b, 10a, 10b denote buffers for removing the influence of impedance on the signal input side.

  The active and standby system clock supply devices 1a and 1b have the same configuration, and a system clock is input to the DPLL units 2a and 2b from a host system (not shown), and the output of one DPLL unit 2a. The clock is input to the other DPLL unit 2b, the output clock of this other DPLL unit 2b is input to one DPLL unit 2a, the clock synchronized in phase with the system clock is recovered, and the recovered output clock is variable The clocks of the active system and the standby system, which are input to the CLK distribution units 6a and 6b via the delay circuits 4a and 4b, and are distributed and output, are input to the phase comparison units 7a and 7b of one and the other, respectively. The phases of the clocks distributed and output to the system are compared, and the variable delay circuits 4a and 4b are compared by the phase comparison determination units 5a and 5b based on the phase difference and the phase advance / delay. And your, always match the clock phase of the working system and the protection system. Therefore, the phase of the active clock distributed and output from the CLK distribution unit 6a of the active system clock supply device 1a and the phase of the standby clock output from the CLK distribution unit 6b of the standby system clock supply device 1b are always set. It is possible to match, and it is possible to eliminate the influence of the phase variation factor due to the circuit elements and the like from the system clock input terminal to the clock distribution units 6a and 6b.

  The buffers 8a to 10a and 8b to 10b correspond to buffer amplifiers whose input impedance does not affect the output characteristics, and the DPLL units 2a and 2b have output clock phases of the active system and the standby system. The phase matching units 3a and 3b perform phase comparison between the system clock from the host device and the output clock from the other DPLL unit via the buffers 6a, 6b, 7a, and 7b so that the phase is the same. When the phase of the output clock is controlled so as to match, and the frequencies of the system clock and the output clock are not the same, the phase matching units 3a and 3b have the same frequency as the system clock. The output clock is divided to perform phase comparison, and the DPLL units 2a and 2b are already known. It is also possible to apply the type of arrangement.

  FIG. 2 is an explanatory diagram of the phase comparison unit, and shows an example of the configuration of the phase comparison units 7a and 7b in FIG. In the figure, 11 is a phase comparator, 12 is an integrating circuit, 13 and 15 are flip-flops (FF), and 14 and 16 are latch circuits. The phase comparator 11 shows a case of an exclusive OR circuit configuration, and the phase comparator 11 shows a case of an exclusive OR configuration, and is used for distribution output from the CLK distribution units 6a and 6b (see FIG. 1). An output signal having a pulse width corresponding to the rising timing difference between the clock and the standby clock is input to the integrating circuit 12. The integration circuit 12 integrates the phase comparison output signal corresponding to the phase difference to obtain a phase difference voltage signal.

  The flip-flop 13 inputs the active clock to the data terminal D and the standby clock to the clock terminal clk. When the standby clock rises behind the rising timing of the active clock, the flip-flop 13 sets the output terminal Q to “ 1 ", latched by the latch circuit 14, and used as a standby system delay detection signal. The flip-flop 15 inputs the standby system clock to the data terminal D and the active system clock to the clock terminal clk, respectively. When the rising timing of the standby system clock is advanced from the rising timing of the active system clock, the output terminal Q is set to “ 1 ", latched by the latch circuit 16, and outputs a standby system advance detection signal. In addition, only one of the latch circuits 14 and 16 is in a state of being latched. When one of the latch circuits is latched, the other is reset by a reset signal, and a standby system delay detection signal and a standby system advance detection signal are set. Both are configured so that they are not output simultaneously. The phase difference voltage signal, the standby system delay detection signal, and the standby system advance detection signal are input to the phase comparison determination units 5a and 5b in FIG.

  The phase comparison / determination units 5a and 5b (see FIG. 1) use the above-described phase difference voltage signal from the phase comparison units 7a and 7b, the standby system delay detection signal, and the standby system advance detection signal to change the variable delay circuit 4a, By controlling the delay amount of 4b, the phases of the active clock and the standby clock input to the CLK distributors 6a and 6b are matched. Therefore, the phases of the active clock and the standby clock distributed and output from the CLK distributors 6a and 6b can be controlled so as to always coincide with each other except for the influence of the characteristics of the internal circuit elements. Further, the case where the delay and advance of the standby system clock with respect to the working system clock are detected is shown. Based on the detection result, the standby system variable delay circuit 4b (see FIG. 1) is controlled. For example, 4a (see FIG. 1) can maintain a zero delay state. When the clock from the standby CLK distribution unit 6b is selected and operated, it is possible to invert the relationship between the standby system and the active system so as to match the clock phases to be distributed and output.

  FIG. 3 is an explanatory diagram of phase difference measurement by high-speed sampling, (A) is an operation explanatory diagram, and shows an example of each of a working clock, a standby clock, a phase difference, and a high-speed sampling clock. It is circuit structure explanatory drawing. The case where the frequency of the active clock and the standby clock is n MHz and the high-speed sampling clock is 10 times that of n × 10 MHz is shown. The circuit configuration includes a gate circuit 21 for inputting an active clock and a standby clock, and a flip-flop (FF) 22 for inputting an output signal of the gate circuit to the data terminal D and a high-speed sampling clock to the clock terminal clk, respectively. The case of a configuration including a counter circuit 23 for inputting an output signal from the output terminal Q of the flip-flop 22 and a high-speed sampling clock is shown.

  When the phase difference between the active clock and the standby clock is shown in FIG. 3A, the output signal of the gate circuit 21 is obtained by inputting the standby clock to the inhibit terminal of the gate circuit 21 to obtain the active clock. The time from the rising edge to the rising edge of the standby clock is shown as a phase difference. The flip-flop 22 holds the time length, that is, the phase difference of the output signal of the gate circuit 21 with the high-speed sampling clock, and the counter circuit 23 counts the number of high-speed sampling clocks within the output holding period. As a result, the count value of the counter circuit 23 indicates the phase difference between the active clock and the standby clock. In this case, in the timing relationship shown in (A), the standby clock has a delay of a high-speed sampling clock period of two pulses from the rise of the active clock, and therefore the high-speed sampling clock at the timings t1 and t2. Is counted up by the counter circuit 23. If the active clock is input to the inhibit terminal of the gate circuit 21, the count value when the standby clock is in the lead phase is advanced and the phase difference is indicated. Further, by making the high-speed sampling clock faster, the phase difference can be detected with a finer resolution.

  FIG. 4 shows the waveforms of the active system clock, the standby system clock, the output of the phase comparator, the standby system advance detection signal, and the standby system when (A) the standby system phase lag is detected and (B) the standby system phase advance is detected. FIG. 2 shows a system delay detection signal, which will be described with reference to the configuration shown in FIG. 2. The output signal of the phase comparator 11 is the phase difference between the active clock and the standby clock regardless of the advance / delay of the standby clock phase. During this period, it becomes “1”. That is, if there is a phase difference between the active clock and the standby clock shown in FIGS. 4A and 4B, the phase difference period is “1”. When the standby clock is delayed with respect to the active clock, the output signal of the flip-flop 13 is “1” because the standby clock becomes “1” after the active clock becomes “1”. It becomes. That is, the latch circuit 14 latches and outputs a standby system delay detection signal. The output signal of the flip-flop 15 is “0” when the active clock is “1”, so the output signal of the flip-flop 15 continues to be “0”. On the other hand, when the standby system clock is ahead of the working system clock, the output signal of the flip-flop 13 continues “0”, the output signal of the flip-flop 15 becomes “1”, and the standby system advance detection signal is output. Is done.

  FIG. 5 is an explanatory diagram of output characteristics of the phase comparison unit. The vertical axis indicates voltage, the horizontal axis indicates phase difference, and the integration circuit 12 (see FIG. 2) of the phase comparison units 7a and 7b (see FIG. 1). An outline of the output characteristics is shown. That is, the phase difference signal from the phase comparator 11 is integrated by the integrating circuit 12, and the phase difference voltage is proportional to the phase difference between the active clock output from the DPLL unit 2a and the standby clock output from the DPLL unit 2b. Indicates the case of output. Actually, as shown in the characteristic curve in the figure, it is shown that a ripple component is included, although it is slight.

  FIG. 6 shows an example in which the jitter / wander of the DPLL units 2a and 2b shown in FIG. 1 affects the output characteristics of the phase comparison units 7a and 7b. A phase difference component including an instantaneous error is expressed as a voltage. By converting, the output characteristics of the phase comparison units 7a and 7b include a phase error as shown.

  FIG. 7 is an explanatory diagram of the phase comparison / determination unit, showing the configuration of the phase comparison / determination units 5a and 5b in FIG. 1, wherein 31 is an A / D conversion unit, 32 is a CPU (processor), 33 is a memory, Reference numeral 34 denotes a conversion table. Further, the phase difference voltage signal from phase comparison unit indicates the phase difference voltage signal from the integration circuit 12 of the phase comparison unit shown in FIG. 2, and this phase difference voltage is input to the A / D conversion unit 31 and from the latch circuit 14. The standby system delay detection signal and the standby system advance detection signal from the latch circuit 16 are input to the CPU 32, and the phase difference data converted by the A / D converter 31 is input to the CPU 32. For example, the CPU 32 stores the input measurement data for a plurality of times in the memory 33, calculates an average value, obtains a variable step signal for the variable delay circuits 4a and 4b (see FIG. 1) by the conversion table 34, As shown as the variable step signal to variable delay circuit, the variable step signal is input to the variable delay circuits 4a and 4b (see FIG. 1). Further, the CPU 32 accumulates the phase difference measurement results in the memory 33 a plurality of times and calculates the average value, thereby ripples of the phase difference voltage signal including the ripple shown in FIG. 5 and the phase difference voltage signal including the jitter shown in FIG. And the influence of jitter / wander can be eliminated.

  FIG. 8 is an explanatory diagram of the contents of the memory. For example, when the CPU 32 obtains an average value of 10 phase difference comparison results, the standby system advance detection signal, the standby system delay detection signal, and the phase difference conversion are illustrated. Data is stored 10 times. In the case shown in the figure, the standby system advance detection signal is “1”, the standby system delay detection signal is “0”, and the phase difference conversion data indicated by the 3-bit configuration is “110”, “111”, “110”, Hold as “101”. Note that the phase difference conversion data is not limited to the three-pit configuration, but can have a desired bit configuration. Further, the logical configuration of the standby system advance detection signal and the standby system delay detection signal can be a logical configuration capable of being discriminated.

  9A is an explanatory diagram of a variable delay circuit, and FIG. 9B is an explanatory diagram of a conversion table. As shown in FIG. 9A, the variable delay circuits 4a and 4b in FIG. A case in which a delay line having different delay amounts and a bypass line having a delay amount of zero are selectively switched by a selector is shown as a four-stage configuration, and the selectors at each stage are controlled by D0 to D3. In this case, the delay amount of each stage delay line is set to 100 ps, 200 ps, 400 ps, and 800 ps, and if all the delay lines are selectively connected by the selector of each stage, the maximum delay amount is 1500 ps. When all bypass lines are selectively connected, the delay amount becomes zero. If only the first delay line is selectively connected, the delay amount is 100 ps. If the first and third delay lines are selectively connected, the delay amount is 500 ps. Therefore, the variable delay circuit can be combined with a plurality of delay lines having different delay amounts, so that a variety of delay amounts can be obtained. If a delay line having a smaller delay amount is selected, the delay amount can be reduced. It is also possible to reduce the amount of change and change the delay amount relatively smoothly. The clock input toDPLL side Buffer corresponds to the buffers 9a and 9b in FIG. 1, and the clock output toCLK distribution unit corresponds to the CLK distribution units 6a and 6b in FIG.

  The conversion table shown in FIG. 9B corresponds to the conversion table 34 in FIG. 7, and the addresses D0 to D3 designate the selectors in the first to fourth stages in FIG. 9A, respectively. This indicates that the delay line corresponding to the addresses D0 to D3 of “1” is selectively connected by the selector. Further, the delay amount can be selected and controlled in 16 steps from 0 to 15. For example, in Step 10, since the addresses D1 and D3 are “1”, the 200 ps delay line by the second stage selector and the 800 ps delay line by the fourth stage selector are selectively connected, resulting in a total of 1000 ps. This is the amount of delay.

  FIG. 10 is an explanatory diagram of the conversion table. In the case of the variable delay circuit having the configuration shown in FIG. 9A, the conversion table shown in FIG. Since the system advance detection signal cannot be dealt with, the relationship between steps 0 to 15 of the conversion table and the delay amount is changed, and step 8 in the middle of steps 1 to 15 is changed to the clock phase difference between the active system and the standby system. This is a reference step when the average result is zero. That is, with respect to the active clock and the standby clock by the variable delay circuits 4a and 4b in FIG. 1, a delay of 800 ps is set as an offset value in advance, and the clock from the DPLL units 2a and 2b is used as the variable delay circuits 4a and 4b. Thus, a delay of 800 ps of the offset value is given and distributed by the CLK distribution units 6a and 6b.

  Also, steps 9 to 15 of the conversion table shown in FIG. 9B are changed to steps 7-1 to FIG. 10 respectively, and steps 1 to 7 of the conversion table shown in FIG. Steps 15 to 9 shown in FIG. Accordingly, when the standby system delay detection signal is “1” and the phase difference average result is “011”, the standby system phase difference indicates a delay of 300 ps, so step 5 (step 11 in FIG. 9B) is performed. A delay amount of 1100 ps in total is obtained by selectively connecting the delay lines of the first, second, and fourth stages by a selector. In this case, as described above, the delay amount of 800 ps is used as the offset value, which corresponds to giving a delay of 300 ps. When the standby system advance detection signal is “1” and the phase difference average result is “011”, the standby system phase difference indicates 300 ps advance, and step 11 (step 5 in FIG. 9B) is performed. The delay amount of 500 ps is obtained by selectively connecting the 100 ps and 400 ps delay lines of the first and third stages by a selector. In this case, since the offset value is set to 800 ps, the advance is 800− (100 + 400) = 300 (ps), and the standby clock phase can be matched with the active clock phase.

  11A and 11B are explanatory diagrams of the clock phase control operation, in which FIG. 11A shows before and after adjustment when the standby clock phase is delayed, and FIG. 11B shows before and after adjustment when the standby clock phase is advanced. After adjustment. In FIG. 11A, the standby clock phase is set to the active clock phase by adjusting the delay amount of the delay line of the variable delay circuit with respect to the standby clock by the standby clock delay detection signal before adjustment. Match. In FIG. 11B, the amount of delay by the delay line of the variable delay circuit is increased by the standby clock advance detection signal before adjustment, and the standby clock phase is adjusted to the active clock phase. Therefore, even when the standby clock phase is a leading phase or a lagging phase with respect to the working clock phase, the clock phase can be matched on the clock output end side to prevent the clock phase from changing due to the switching of the working standby phase.

(Supplementary Note 1) In a clock supply device having an active system clock supply device that outputs an active clock that is phase-synchronized with a system clock from a host device, and a standby system clock supply device that outputs a standby clock The system clock supply device for the active system and the standby system includes a DPLL unit that outputs a clock phase-synchronized with the system clock, a variable delay circuit that delay-controls a clock from the DPLL unit, and the variable delay circuit. A phase comparison unit that compares the phases of the active clock and the standby clock output via the phase comparison unit, and a delay of the variable delay circuit according to a phase comparison result between the active clock and the standby clock by the phase comparison unit. A clock supply device comprising a phase comparison / determination unit for controlling the amount.
(Supplementary Note 2) The phase comparison unit includes an integration circuit that outputs a voltage value corresponding to a phase difference between the active clock and the standby clock, the active clock as a data terminal, and the standby clock as a clock. A flip-flop for inputting a standby system delay detection signal to each of the terminals, and a flip-flop for outputting the standby system advance detection signal by inputting the active system clock to the clock terminal and the standby system clock to the data terminal, respectively. The clock supply device according to appendix 1, wherein:
(Supplementary Note 3) The phase comparison unit includes a counter circuit that samples a phase difference between the active clock and the standby clock with a high-speed sampling clock to obtain a count value corresponding to the phase difference. The clock supply device according to appendix 1.

(Additional remark 4) The said phase comparison determination part contains the means to average the phase difference voltage signal from the said phase comparison part, The structure which controls the said variable delay circuit based on the signal which averaged the said phase difference voltage signal The clock supply device according to appendix 1, characterized by comprising:
(Supplementary note 5) The clock according to Supplementary note 1, wherein the variable delay circuit has a configuration in which a plurality of delay lines having different delay amounts and a bypass line having zero delay amount are selected by a selector and connected in series. Feeding device.
(Appendix 6) The phase comparison / determination unit that controls the delay amount of the variable delay circuit uses a delay amount intermediate between the minimum delay amount and the maximum delay amount of the variable delay circuit as a reference delay amount, and the reference delay amount It is selected when a phase difference of zero between the active clock and the standby clock is detected, and when the advance phase of the standby clock is detected, a delay amount with respect to the standby clock is increased from the reference delay amount. 2. The clock supply apparatus according to claim 1, further comprising a control configuration for reducing a delay amount with respect to the standby system clock from the reference delay amount when a delay phase is detected.
(Additional remark 7) The said phase comparison determination part converts the phase difference voltage signal from the said phase comparison part into a digital signal, and hold | maintains the spare system delay detection signal and spare system advance detection signal from the said phase comparison part in multiple times A delay time of the variable delay circuit based on the phase difference averaged by the means and the standby system delay detection signal or the standby system advance detection signal The clock supply device according to appendix 1 or appendix 6, characterized in that it comprises a conversion table that holds the steps of increasing and decreasing.

It is explanatory drawing of Example 1 of this invention. It is explanatory drawing of a phase comparison part. It is explanatory drawing of the phase difference measurement by high-speed sampling. It is explanatory drawing at the time of protection system phase delay detection, and the time of protection system phase advance detection. It is explanatory drawing of the output characteristic of a phase comparison part. It is output characteristic explanatory drawing of the phase comparison part containing a jitter / wander. It is explanatory drawing of a phase comparison determination part. It is explanatory drawing of the memory content. It is explanatory drawing of a variable delay circuit and a conversion table. It is explanatory drawing of a conversion table. It is explanatory drawing of a clock phase control operation | movement. It is explanatory drawing of a prior art example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1a N system (active system) system clock supply apparatus 1b E system (standby system) system clock supply apparatus 2a, 2b DPLL part 3a, 3b Phase adjustment part 4a, 4b Variable delay circuit 5a, 5b Phase comparison judgment part 6a, 6b CLK Distribution unit 7a, 7b Phase comparison unit

Claims (5)

In a clock supply device having an active system clock supply device that outputs an active clock that is phase-synchronized with a system clock from a host device and a standby system clock supply device that outputs a standby clock,
The system clock supply device for the active system and the standby system includes a DPLL unit that outputs a clock phase-synchronized with the system clock;
A variable delay circuit for delay-controlling the clock from the DPLL unit;
A phase comparator for comparing the phases of the active clock and the standby clock output via the variable delay circuit;
A clock supply apparatus comprising: a phase comparison determination unit that controls a delay amount of the variable delay circuit based on a phase comparison result between the active clock and the standby clock by the phase comparison unit.   The phase comparison unit inputs an integration circuit that outputs a voltage value corresponding to a phase difference between the active clock and the standby clock, and inputs the active clock to a data terminal and the standby clock to a clock terminal. And a flip-flop for outputting a standby system advance detection signal by inputting the active system clock to a clock terminal and the standby system clock to a data terminal. The clock supply apparatus according to claim 1, wherein:   The phase comparison unit includes a counter circuit that samples a phase difference between the active clock and the standby clock with a high-speed sampling clock to obtain a count value corresponding to the phase difference. 1. The clock supply device according to 1.   2. The clock supply device according to claim 1, wherein the variable delay circuit has a configuration in which a plurality of delay lines having different delay amounts and a bypass line having a zero delay amount are selected by a selector and connected in series.   The phase comparison / determination unit that controls the delay amount of the variable delay circuit uses a delay amount intermediate between the minimum delay amount and the maximum delay amount of the variable delay circuit as a reference delay amount, and the reference delay amount is used as the working system clock. Selected when the phase difference between the standby clock and the standby clock is detected, the delay amount relative to the standby clock is increased from the reference delay amount when the advance phase of the standby clock is detected, and the delayed phase of the standby clock is detected 2. The clock supply device according to claim 1, further comprising a control configuration for reducing a delay amount with respect to the standby clock from the reference delay amount.

Images