CN101515850B - Network signal processing device - Google Patents
Network signal processing device Download PDFInfo
- Publication number
- CN101515850B CN101515850B CN2008100807833A CN200810080783A CN101515850B CN 101515850 B CN101515850 B CN 101515850B CN 2008100807833 A CN2008100807833 A CN 2008100807833A CN 200810080783 A CN200810080783 A CN 200810080783A CN 101515850 B CN101515850 B CN 101515850B
- Authority
- CN
- China
- Prior art keywords
- signal
- sampling frequency
- signal processing
- frequency converter
- signals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
The invention provides a network signal processing device, which comprises a first signal processing module, a first sampling frequency converter, a second signal processing module, a second sampling frequency converter, and a time sequence controller, wherein the first signal processing module is used for processing a network signal to output a first processing signal; the first sampling frequency converter is used for performing signal frequency conversion on the first processing signal according to a first time sequence adjusting signal and outputting a first conversion signal; the second signal processing module is used for processing the first conversion signal to output a second processing signal; the second sampling frequency converter is used for performing signal frequency conversion on the second processing signal according to a second time sequence adjusting signal and outputting a second conversion signal; and the time sequence controller is used for generating the first and second time sequence adjusting signals.
Description
Technical field
The invention relates to network signal processing device, especially refer to a kind of have first sampling frequency converter, second sampling frequency converter and time schedule controller, and this first, second sampling frequency converter comes the signal in asynchronous domain and the synchronization field is carried out the signal frequency conversion according to first, second time sequence adjusting signals that this time schedule controller produced respectively, so that the signal in asynchronous domain and the synchronization field has the network signal processing device of same operation frequency respectively.
Background technology
In general, conveyer (the Transmitter of communication system, TX) transmitting signal and receiver (Receiver, RX) when received signal, conveyer and receiver can carry out the transmission of signal in a synchronous manner, and on real the work, make that conveyer and receiver are synchronous, in receiver, need clock generator of design to produce a clock signal, and analyze the phase place adjustment that received signal carries out clock signal, pin up to this clock signal till the clock signal of conveyer end, to finish the operation of clock synchronization.
Yet,, go to follow the trail of the clock signal of conveyer because the clock signal of receiver need constantly be adjusted phase place, therefore, under the situation of phase-unstable, can make the numerical value that partial circuit has generated, may do the operation of convergence again, and cause performance of entire system to reduce.
Summary of the invention
Therefore, one of purpose of the present invention is to provide a kind of network signal processing device, by first sampling frequency converter and second sampling frequency converter, make signal be converted to synchronization field and also can be converted to asynchronous domain, come the device in the asynchronous domain is controlled to utilize the signal in the synchronization field by asynchronous domain by synchronization field.
According to embodiments of the invention, it is to disclose a kind of network signal processing device.This network signal processing device includes first signal processing module, first sampling frequency converter, secondary signal processing module, second sampling frequency converter and time schedule controller.This first signal processing module operates in the asynchronous domain, is used to handle network signal to export first processing signals; This first sampling frequency converter is coupled to this first signal processing module, is used for according to first time sequence adjusting signals this first processing signals being carried out signal frequency conversion, and exports first switching signal; This secondary signal processing module operates in the synchronization field, and is coupled to this first sampling frequency converter, is used to handle this first switching signal to export second processing signals; This second sampling frequency converter is coupled between this first signal processing module and this secondary signal processing module, be used for according to second time sequence adjusting signals this second processing signals being carried out signal frequency conversion, and export second switching signal to this first signal processing module; And this time schedule controller, be coupled to this first, second sampling frequency converter, be used to produce this first time sequence adjusting signals to this first sampling frequency converter, and produce this second time sequence adjusting signals to this second sampling frequency converter, to adjust the sequential of this first, second switching signal.
According to embodiments of the invention, it also discloses a kind of network signal processing device.This network signal processing device includes first signal processing module, sampling frequency converter, secondary signal processing module and time schedule controller.This first signal processing module operates in the asynchronous domain, is used to handle network signal to export first processing signals; This sampling frequency converter is coupled to this first signal processing module, is used for according to time sequence adjusting signals this first processing signals being carried out signal frequency conversion, and the output switching signal; This secondary signal processing module operates in the synchronization field, and is coupled to this sampling frequency converter, is used to handle this switching signal to export second processing signals; And this time schedule controller is coupled to this secondary signal processing module, is used for according to this second processing signals to produce this time sequence adjusting signals, to adjust the sequential of this switching signal.
Description of drawings
Fig. 1 is the schematic diagram of a preferred embodiment of network signal processing device of the present invention.
Fig. 2 is the relative time interval schematic diagram of first processing signals, first switching signal, second processing signals and second switching signal.
[main element label declaration]
100 network signal processing devices
110,120 signal processing modules
112 adc
114 feed forward equalizers
122 cutters
124 adders
130,140 sampling frequency converters
150 time schedule controllers
Embodiment
In the middle of specification and above-mentioned claim, used some vocabulary to censure specific element.Those skilled in the art should understand, and hardware manufacturer may be called same element with different nouns.This specification and above-mentioned claim are not used as distinguishing the mode of element with the difference of title, but the criterion that is used as distinguishing with the difference of element on function.Be open term mentioned " comprising " in the middle of specification and the above-mentioned request item in the whole text, so should be construed to " comprise but be not limited to ".In addition, " coupling " speech is to comprise any indirect means that are electrically connected that directly reach at this.Therefore, be coupled to second device, then represent this first device can directly be electrically connected in this second device, or be electrically connected to this second device indirectly by other device or connection means if describe first device in the literary composition.
Below will cooperate graphic different characteristic of the present invention to be described, and identical part will be represented so that explanation with same label in each diagram.
See also Fig. 1, Fig. 1 is the schematic diagram of a preferred embodiment of network signal processing device 100 of the present invention.As shown in Figure 1, network signal processing device 100 includes first signal processing module 110, operates in (Asynchronous domain) in the asynchronous domain; Secondary signal processing module 120 operates in (Synchronous domain) in the synchronization field; First sampling frequency converter 130; Second sampling frequency converter 140 and time schedule controller 150.The disclosed technical characterictic of the present invention for convenience of explanation, in the present embodiment, suppose that network signal processing device 100 is to be arranged in the receiver of 10G Base-T Ethernet network (Ethernet), and in the standard of 10G Base-T Ethernet network, the symbol-rate (symbol rate) of signal transmission is 800MHz, yet this only is the usefulness as the example explanation, be not to be restriction of the present invention, that is the disclosed circuit framework of the present invention also can be implemented into according to demand in other application apparatus.First signal processing module 110 in the network signal processing device 100 is that running is in asynchronous domain, its frequency of operation is 1GHz, yet, this frequency of operation only is the usefulness as the example explanation, be not to be restriction of the present invention, other any frequency of operation greater than symbol-rate (800MHz) also is feasible, for example 900Hz or 950Hz; Secondary signal processing module 120 and 150 runnings of time schedule controller are in synchronization field, and its frequency of operation then is 800MHz (that is symbol-rate).Below will further specify the function mode of network signal processing device 100, yet this only being the usefulness as the example explanation, is not to be restriction of the present invention.
At first, please refer to first signal processing module 110, first signal processing module 110 is according to one embodiment of the invention, include adc (analog-to-digital converter, ADC) 112 and feed forward equalizer (feed-forward equalizer, FFE) 114, wherein, feed forward equalizer 114 is to be coupled to adc 112, first sampling frequency converter 130 and second sampling frequency converter 140.Adc 112 can be carried out the analog digital conversion with network signal Shet with the sampling frequency of 1GHz, with output digital signal Sd, feed forward equalizer 114 then carries out equilibrium treatment producing the first processing signals Sp1 to digital signal Sd, and exports the first processing signals Sp1 to first sampling frequency converter 130.
As shown in Figure 1, first sampling frequency converter 130 is to be coupled between first signal processing module 110 and the secondary signal processing module 120, and come the first processing signals Sp1 is carried out the signal frequency conversion according to the first time sequence adjusting signals Sadj1 that time schedule controller 150 is produced, to produce the first switching signal Sc1.Because first signal processing module 110 is that running is in asynchronous domain (symbol-rate is 1GHz), but secondary signal processing module 120 is that running is in synchronization field (symbol-rate is 800MHz), therefore, frequency is that secondary signal processing module 120 can be handled the first switching signal Sc1 after the first processing signals Sp1 of 1GHz must be converted to the first switching signal Sc 1 that frequency is 800MHz through first sampling frequency converter 130.According to an embodiment, first sampling frequency converter 130 can be realized by interpolater, interpolater can come according to the first time sequence adjusting signals Sadj1 that time schedule controller 150 is produced the first processing signals Sp1 is carried out interpolation, to produce the first switching signal Sc1 to secondary signal processing module 120.
Refer again to the secondary signal processing module 120 among Fig. 1, secondary signal processing module 120 is according to one embodiment of the invention, include cutter (slicer) 122 and adder 124, wherein cutter 122 can cut back signal Sout to produce by the cutting first switching signal Sc1, and output cutting back signal Sout to the next stage circuit to carry out subsequent treatment, in addition, adder 124 can be carried out computing to the input of cutter 122 and output signal (that is the first switching signal Sc1 and cutting back signal Sout) and be adjusted the running of feed forward equalizer 114 to produce the second processing signals Sp2, for example, adder 124 is to carry out subtraction to calculate the difference of the first switching signal Sc1 and cutting back signal Sout to produce the second processing signals Sp2.With present embodiment, the second processing signals Sp2 is error signal (error signal), that is the input of cutter 122 and output signal subtract each other the value that can calculate error signal, and feeds back in the feed forward equalizer 114.Thus, feed forward equalizer 114 can carry out equilibrium treatment to digital signal Sd according to this error signal, to export the first processing signals Sp1.
As shown in Figure 1, second sampling frequency converter 140 is to be coupled between first signal processing module 110 and the secondary signal processing module 120, and come the second processing signals Sp2 is carried out the signal frequency conversion according to the second time sequence adjusting signals Sadj2 that time schedule controller 150 is produced, to produce the second switching signal Sc2.Similarly, because secondary signal processing module 120 is that running is in synchronization field (symbol-rate is 800MHz), but the feed forward equalizer 114 in first signal processing module 110 is that running is in asynchronous domain (symbol-rate is 1GHz), therefore frequency is that feed forward equalizer 114 could be adjusted its running according to the second switching signal Sc2 after the second processing signals Sp2 of 800MHz must convert the second switching signal Sc2 that frequency is 1GHz to via second sampling frequency converter 140.According to an embodiment, second sampling frequency converter 140 can be realized by interpolater, interpolater can come according to the second time sequence adjusting signals Sadj2 that time schedule controller 150 is produced the second processing signals Sp2 is carried out interpolation, to produce in second switching signal Sc2 to the first signal processing module 110.
Please consult Fig. 1 once more, time schedule controller 150 is to be coupled to first sampling frequency converter 130, between second sampling frequency converter 140 and the secondary signal processing module 120, time schedule controller 150 produces the first time sequence adjusting signals Sadj1 and the second time sequence adjusting signals Sadj2 according to the second processing signals Sp2 in the secondary signal processing module 120, first sampling frequency converter 130 decides the time interval (time step) of the first processing signals Sp1 being carried out interpolation according to the first time sequence adjusting signals Sadj1, and second sampling frequency converter 140 decides the time interval of the second processing signals Sp2 being carried out interpolation according to the second time sequence adjusting signals Sadj2.
See also Fig. 2, Fig. 2 is the relative time interval schematic diagram of the first processing signals Sp1, the first switching signal Sc1, the second processing signals Sp2 and the second switching signal Sc2.Because the signal frequency of the first processing signals Sp1, the second switching signal Sc2 is 1GHz; The first switching signal Sc1, the signal frequency of the second processing signals Sp2 is 800MHz, therefore, if when being used as 1 unit with the time interval of the first processing signals Sp1, the first processing signals Sp1 should be 1.25 units via the time interval of the first switching signal Sc1 that 130 conversions of first sampling frequency converter are come out, because frequency can not change after the processing of signal process secondary signal processing module 120, therefore the time interval of the second processing signals Sp2 still remains 1.25 units, and the time interval that the second processing signals Sp2 changes the second switching signal Sc2 that comes out via second sampling frequency converter 140 should be reduced to 1 unit.Please note, because those skilled in the art should know first sampling frequency converter 130 and how signal frequency are converted to 1GHz by 800MHz, and second sampling frequency converter 140 how signal frequency is converted to the detailed operation mode of 800MHz by 1GHz, therefore for ask description for purpose of brevity its relevant detailed description just in this omission.
Please note, the foregoing description is not all considered the problem of frequency shift (FS) (frequency offset) or phase deviation (phase offset), if when considering the problem of frequency shift (FS) or phase deviation, then time schedule controller 150 will dynamically compensate sampling frequency converter by the time sequence adjusting signals amount of affording redress; Suppose that first sampling frequency converter 130 and second sampling frequency converter 140 are interpolater, and the mode by interpolation is carried out frequency inverted, then time schedule controller 150 is to provide a compensation rate offset by the first time sequence adjusting signals Sadj1, controls 130 couples first processing signals Sp1 of first sampling frequency converter and carries out the time interval of interpolation with dynamic compensation first sampling frequency converter 130; In the same manner, time schedule controller 150 is also by the second time sequence adjusting signals Sadj2 amount of the affording redress offset, control the time interval that 140 couples second processing signals Sp2 of second sampling frequency converter carry out interpolation, with dynamic compensation second sampling frequency converter 140, make the sequential of the second switching signal Sc2 be equal to the sequential of the first processing signals Sp1 in fact.For instance, when not considering the problem of frequency shift (FS) or phase deviation, the time interval that first sampling frequency converter 130 carries out interpolation all is fixed as 1.25 units, under the situation of considering frequency shift (FS) or phase deviation, the time interval that first sampling frequency converter 130 carries out interpolation will become (1.25+offset) individual unit.In addition, the method of dynamic compensation also can be subdivided into phase-locked loop (phase-locked loop, PLL) and voltage controlled oscillator (voltage controlled oscillator, VCO) two kinds, when utilizing the mode of PLL to compensate, only have part-time to be spaced apart (1.25+offset) individual unit, all the other time intervals still remain on 1.25 units, and wherein compensation rate offset is a certain value; If when utilizing the mode of VCO to compensate, each time interval is (1.25+offset) unit, and the size of the each compensation rate offset of time schedule controller 150 continuous updatings.Note that because those skilled in the art should know and how utilize PLL and VCO to come the detailed device and the How It Works in the dynamic compensation time interval, therefore for asking description its relevant detailed description in detail for purpose of brevity just in this omission.
The above only is preferred embodiment of the present invention, and all equalizations of being done according to claim scope of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (9)
1. network signal processing device comprises:
First signal processing module operates in the asynchronous domain, is used to handle network signal to export first processing signals;
First sampling frequency converter is coupled to this first signal processing module, is used for according to first time sequence adjusting signals this first processing signals being carried out signal frequency conversion, and exports first switching signal;
The secondary signal processing module operates in the synchronization field, and is coupled to this first sampling frequency converter, is used to handle this first switching signal to export second processing signals;
Second sampling frequency converter, be coupled between this first signal processing module and this secondary signal processing module, be used for according to second time sequence adjusting signals this second processing signals being carried out signal frequency conversion, and export second switching signal to this first signal processing module; And
Time schedule controller, be coupled to this first, second sampling frequency converter, be used to produce this first time sequence adjusting signals to this first sampling frequency converter, and produce this second time sequence adjusting signals, to adjust the sequential of this first, second switching signal to this second sampling frequency converter.
2. network signal processing device according to claim 1, this first signal processing module wherein comprises:
Analog-digital converter is in order to this network signal is carried out the analog digital conversion, with the output digital signal; And
Feed forward equalizer is coupled to this analog-digital converter, in order to this digital signal is carried out equilibrium treatment, to export this first processing signals.
3. network signal processing device according to claim 1, wherein this secondary signal is handled processing module, comprises:
Cutter is in order to cut this first switching signal, with the output cutoff signal; And
Arithmetic element is coupled to this cutter, in order to this first switching signal and this cutoff signal are carried out computing, to export this second processing signals.
4. network signal processing device according to claim 1, wherein this time schedule controller is to export this first, second time sequence adjusting signals according to this second processing signals.
5. network signal processing device according to claim 1, wherein this second processing signals is an error signal.
6. network signal processing device according to claim 1, wherein this first, second sampling frequency converter is an interpolater.
7. network signal processing device according to claim 6, wherein this first sampling frequency converter decides the time interval of this first processing signals being carried out interpolation according to this first time sequence adjusting signals, and this second sampling frequency converter decides the time interval of this second processing signals being carried out interpolation according to this second time sequence adjusting signals.
8. network signal processing device according to claim 6, wherein this time schedule controller dynamically compensates each time interval that this first sampling frequency converter carries out interpolation, and dynamically compensates each time interval that this second sampling frequency converter carries out interpolation.
9. network signal processing device according to claim 1, it is to be arranged in the Ethernet system.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100807833A CN101515850B (en) | 2008-02-18 | 2008-02-18 | Network signal processing device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100807833A CN101515850B (en) | 2008-02-18 | 2008-02-18 | Network signal processing device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101515850A CN101515850A (en) | 2009-08-26 |
| CN101515850B true CN101515850B (en) | 2011-08-31 |
Family
ID=41040160
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2008100807833A Active CN101515850B (en) | 2008-02-18 | 2008-02-18 | Network signal processing device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101515850B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8879585B2 (en) | 2010-05-13 | 2014-11-04 | Mediatek Inc. | Frame timing controller and frame timing control method for triggering at least receiver in mobile station to start receiving transmitted information of base station by referring to at least frame pointer |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103455009A (en) * | 2013-09-10 | 2013-12-18 | 昆山奥德鲁自动化技术有限公司 | Long-distance Ethernet frequency converter |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1161830A (en) * | 1997-01-16 | 1997-10-15 | 何景平 | Luminous nail polish |
| CN1161831A (en) * | 1996-04-08 | 1997-10-15 | 冯展 | Farinfrared ginseng hair cream |
-
2008
- 2008-02-18 CN CN2008100807833A patent/CN101515850B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1161831A (en) * | 1996-04-08 | 1997-10-15 | 冯展 | Farinfrared ginseng hair cream |
| CN1161830A (en) * | 1997-01-16 | 1997-10-15 | 何景平 | Luminous nail polish |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8879585B2 (en) | 2010-05-13 | 2014-11-04 | Mediatek Inc. | Frame timing controller and frame timing control method for triggering at least receiver in mobile station to start receiving transmitted information of base station by referring to at least frame pointer |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101515850A (en) | 2009-08-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102347763B (en) | Calibrating apparatus, calibrating method and clock forming apparatus | |
| JP3303036B2 (en) | Channel training for multi-channel receiver systems | |
| US9450788B1 (en) | Equalizer for high speed serial data links and method of initialization | |
| US9660846B2 (en) | High-speed serial data signal receiver circuitry | |
| US8912934B2 (en) | Systems with bias offset and gain mismatch removal from parallel transmitted signals | |
| JP4994315B2 (en) | Analog signal processing system, parallel analog / digital converter system, and mismatch elimination method | |
| CN101515850B (en) | Network signal processing device | |
| US8166333B2 (en) | Network signal processing apparatus | |
| CN101471765B (en) | Network device and method for processing network signal | |
| WO2019192300A1 (en) | Clock phase recovery apparatus and method, and chip | |
| CN110492964A (en) | One kind being based on CLOCK BUFF clock source synchronizing device and method | |
| US20040052221A1 (en) | Transceiver for echo and near-end crosstalk cancellation without loop timing configuration | |
| CN101515811B (en) | Signal processing device | |
| CN208986921U (en) | A kind of synchronization system applied to multi-channel high-speed digital analog converter | |
| US7262645B2 (en) | System and method for adjusting the phase of a frequency-locked clock | |
| US7453288B2 (en) | Clock translator and parallel to serial converter | |
| US9252994B2 (en) | Network apparatus and network signal processing method | |
| US20080267277A1 (en) | Digitally synchronized receiving device and associated signal processing method | |
| JP2016163117A (en) | Signal distortion compensation circuit | |
| GB2102255A (en) | Two-wire line for digital communication | |
| CN109194334A (en) | A kind of synchronization system applied to multi-channel high-speed digital analog converter | |
| CN103095445B (en) | R-T unit of adjustment transmission clock and associated method | |
| JP2008219216A (en) | Clock supply unit | |
| CN102480339A (en) | Communication system and method for cancelling time correlation of signals | |
| JP3178864B2 (en) | Jitter compensation device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |