CN101515850B - Network signal processing device - Google Patents

Abstract

A network signal processing device comprises a first signal processing module, a first sampling frequency converter, a second signal processing module, a second sampling frequency converter and a time schedule controller. The first signal processing module is used for processing the network signal to output a first processing signal; the first sampling frequency converter is used for carrying out signal frequency conversion on the first processing signal according to a first timing adjusting signal and outputting a first conversion signal; the second signal processing module is used for processing the first conversion signal to output a second processing signal; the second sampling frequency converter is used for carrying out signal frequency conversion on the second processing signal according to a second timing adjusting signal and outputting a second conversion signal; and the time sequence controller is used for generating the first and the second time sequence adjusting signals.

Description

Network Signal Processing Device

technical field

The present invention relates to a network signal processing device, especially a device with a first sampling frequency converter, a second sampling frequency converter and a timing controller, and the first and second sampling frequency converters are respectively based on the timing controller The generated first and second timing adjustment signals are used to convert the signal frequency of the signals in the asynchronous domain and the synchronous domain, so that the signals in the asynchronous domain and the synchronous domain respectively have the same operating frequency of the network signal processing device.

Background technique

Generally speaking, when the transmitter (TX) of the communication system transmits the signal and the receiver (RX) receives the signal, the transmitter and the receiver will transmit the signal in a synchronous manner, but in practice , to synchronize the transmitter and the receiver, a clock generator needs to be designed in the receiver to generate a clock signal, and analyze the received signal to adjust the phase of the clock signal until the clock signal is locked to the clock at the transmitter signal to complete the operation of clock synchronization.

However, since the clock signal of the receiver needs to constantly adjust the phase to track the clock signal of the transmitter, therefore, in the case of unstable phase, the calculated value of some circuits may need to be re-converged. As a result, the performance of the overall system is reduced.

Contents of the invention

Therefore, one of the objectives of the present invention is to provide a network signal processing device, through the first sampling frequency converter and the second sampling frequency converter, the signal can be converted from the asynchronous domain to the synchronous domain and also from the synchronous domain to the asynchronous domain. , to use signals in the synchronous domain to control devices in the asynchronous domain.

According to an embodiment of the present invention, a network signal processing device is disclosed. The network signal processing device includes a first signal processing module, a first sampling frequency converter, a second signal processing module, a second sampling frequency converter and a timing controller. The first signal processing module operates in an asynchronous domain, and is used to process network signals to output a first processed signal; the first sampling frequency converter is coupled to the first signal processing module, and is used to adjust signals according to a first timing sequence to output a first processed signal. performing signal frequency conversion on the first processed signal, and outputting a first converted signal; the second signal processing module operates in a synchronous domain, and is coupled to the first sampling frequency converter for processing the first converted signal to output a second processed signal; the second sampling frequency converter is coupled between the first signal processing module and the second signal processing module, and is used to adjust the signal according to the second timing to signal the second processed signal frequency conversion, and output a second conversion signal to the first signal processing module; and the timing controller, coupled to the first and second sampling frequency converters, is used to generate the first timing adjustment signal to the first signal processing module A sampling frequency converter, and generating the second timing adjustment signal to the second sampling frequency converter to adjust the timing of the first and second conversion signals.

According to the embodiment of the present invention, it also discloses a network signal processing device. The network signal processing device includes a first signal processing module, a sampling frequency converter, a second signal processing module and a timing controller. The first signal processing module operates in an asynchronous domain, and is used to process network signals to output a first processed signal; the sampling frequency converter is coupled to the first signal processing module, and is used to adjust signals according to timing to the first signal processing module. The processed signal performs signal frequency conversion and outputs the converted signal; the second signal processing module operates in the synchronous domain and is coupled to the sampling frequency converter for processing the converted signal to output a second processed signal; and the timing The controller is coupled to the second signal processing module, and is used for generating the timing adjustment signal according to the second processing signal, so as to adjust the timing of the conversion signal.

Description of drawings

FIG. 1 is a schematic diagram of a preferred embodiment of the network signal processing device of the present invention.

FIG. 2 is a schematic diagram of relative time intervals of a first processed signal, a first converted signal, a second processed signal, and a second converted signal.

[Description of main component labels]

100 Network signal processing device

110, 120 signal processing module

112 Analog to Digital Converter

114 feedforward equalizer

122 cutter

124 adder

130, 140 sampling frequency converter

150 timing controller

Detailed ways

Certain terms are used in the specification and claims above to refer to particular elements. Those skilled in the art should understand that hardware manufacturers may use different terms to refer to the same component. This specification and the above-mentioned scope of patent application do not use the difference in name as a way to distinguish components, but use the difference in function of components as a criterion for distinguishing. The "comprising" mentioned in the entire specification and the above-mentioned claims is an open term, so it should be interpreted as "including but not limited to". In addition, the term "coupled" herein includes any direct and indirect means of electrical connection. Therefore, if it is described that a first device is coupled to a second device, it means that the first device may be directly electrically connected to the second device, or indirectly electrically connected to the second device through other devices or connection means.

The different features of the present invention will be described below with reference to the drawings, and the same parts will be denoted by the same reference numerals in each drawing for convenience of description.

Please refer to FIG. 1 . FIG. 1 is a schematic diagram of a preferred embodiment of a network signal processing device 100 of the present invention. As shown in Figure 1, the network signal processing device 100 includes a first signal processing module 110, operating in an asynchronous domain (Asynchronous domain); a second signal processing module 120, operating in a synchronous domain (Synchronous domain); the first sampling a frequency converter 130 ; a second sampling frequency converter 140 and a timing controller 150 . In order to facilitate the description of the technical features disclosed in the present invention, in this embodiment, it is assumed that the network signal processing device 100 is set in a receiver of 10G Base-T Ethernet (Ethernet), and in the specification of 10G Base-T Ethernet Among them, the symbol rate of signal transmission is 800MHz, however, this is only used as an example for illustration, and is not a limitation of the present invention, that is, the circuit structure disclosed in the present invention can also be implemented on demand in other applications. The first signal processing module 110 in the network signal processing device 100 operates in an asynchronous domain, and its operating frequency is 1 GHz. However, this operating frequency is only used as an example for illustration and is not a limitation of the present invention. Any other The operating frequency of the symbol rate (800MHz) is also feasible, such as 900Hz or 950Hz; the second signal processing module 120 and the timing controller 150 operate in the synchronous domain, and their operating frequencies are both 800MHz (that is, the symbol rate ). The operation of the network signal processing device 100 will be further described below, however, this is only for illustrative purposes and not a limitation of the present invention.

First, please refer to the first signal processing module 110. According to an embodiment of the present invention, the first signal processing module 110 includes an analog-to-digital converter (analog-to-digital converter, ADC) 112 and a feedforward equalizer ( feed-forward equalizer (FFE) 114 , wherein the feed-forward equalizer 114 is coupled to the analog-to-digital converter 112 , the first sampling frequency converter 130 and the second sampling frequency converter 140 . The analog-to-digital converter 112 performs analog-to-digital conversion on the network signal Shet at a sampling frequency of 1 GHz to output a digital signal Sd, and the feedforward equalizer 114 then performs equalization processing on the digital signal Sd to generate a first processed signal Sp1, and The first processed signal Sp1 is output to the first sampling frequency converter 130 .

As shown in FIG. 1, the first sampling frequency converter 130 is coupled between the first signal processing module 110 and the second signal processing module 120, and adjusts the signal according to the first timing adjustment signal Sadj1 generated by the timing controller 150. The first processed signal Sp1 undergoes signal frequency conversion to generate a first converted signal Sc1. Since the first signal processing module 110 operates in the asynchronous domain (the symbol rate is 1 GHz), but the second signal processing module 120 operates in the synchronous domain (the symbol rate is 800 MHz), therefore, the first signal with a frequency of 1 GHz The processed signal Sp1 must be converted into the first converted signal Sc1 with a frequency of 800 MHz by the first sampling frequency converter 130 before the second signal processing module 120 can process the first converted signal Sc1. According to an embodiment, the first sampling frequency converter 130 may be implemented by an interpolator, and the interpolator may interpolate the first processed signal Sp1 according to the first timing adjustment signal Sadj1 generated by the timing controller 150 to generate The first conversion signal Sc1 is sent to the second signal processing module 120 .

Please refer to the second signal processing module 120 in FIG. 1 again. According to an embodiment of the present invention, the second signal processing module 120 includes a slicer 122 and an adder 124, wherein the slicer 122 slices the first conversion Signal Sc1 to generate the signal Sout after cutting, and output the signal Sout after cutting to the next stage circuit for subsequent processing. In addition, the adder 124 will input and output signals of the cutter 122 (that is, the first conversion signal Sc1 and cutting After signal Sout) to generate the second processed signal Sp2 to adjust the operation of the feedforward equalizer 114, for example, the adder 124 is to perform subtraction to calculate the difference between the first conversion signal Sc1 and the cut signal Sout to generate the second Two processes the signal Sp2. In this embodiment, the second processed signal Sp2 is an error signal, that is, the value of the error signal can be calculated by subtracting the input and output signals of the cutter 122, and fed back to the feedforward equalizer 114. . In this way, the feedforward equalizer 114 can equalize the digital signal Sd according to the error signal to output the first processed signal Sp1.

As shown in FIG. 1, the second sampling frequency converter 140 is coupled between the first signal processing module 110 and the second signal processing module 120, and adjusts the signal according to the second timing adjustment signal Sadj2 generated by the timing controller 150. The second processed signal Sp2 undergoes signal frequency conversion to generate a second converted signal Sc2. Similarly, since the second signal processing module 120 operates in the synchronous domain (the symbol rate is 800MHz), but the feedforward equalizer 114 in the first signal processing module 110 operates in the asynchronous domain (the symbol rate is 1GHz ), so the second processed signal Sp2 with a frequency of 800 MHz must be converted into a second converted signal Sc2 with a frequency of 1 GHz by the second sampling frequency converter 140, and then the feedforward equalizer 114 can adjust its operation according to the second converted signal Sc2 . According to an embodiment, the second sampling frequency converter 140 may be implemented by an interpolator, and the interpolator may interpolate the second processed signal Sp2 according to the second timing adjustment signal Sadj2 generated by the timing controller 150 to generate The second conversion signal Sc2 is sent to the first signal processing module 110 .

Please refer to FIG. 1 again, the timing controller 150 is coupled between the first sampling frequency converter 130 , the second sampling frequency converter 140 and the second signal processing module 120 , the timing controller 150 according to the second signal processing module 120 The first timing adjustment signal Sadj1 and the second timing adjustment signal Sadj2 are generated by the second processing signal Sp2 in the first sampling frequency converter 130 to determine the interpolation time for the first processing signal Sp1 according to the first timing adjustment signal Sadj1 The second sampling frequency converter 140 determines the time interval for interpolating the second processed signal Sp2 according to the second timing adjustment signal Sadj2.

Please refer to FIG. 2 . FIG. 2 is a schematic diagram of relative time intervals of the first processed signal Sp1 , the first converted signal Sc1 , the second processed signal Sp2 , and the second converted signal Sc2 . Since the signal frequency of the first processed signal Sp1 and the second converted signal Sc2 is 1 GHz; the signal frequency of the first converted signal Sc1 and the second processed signal Sp2 is 800 MHz, therefore, if the time interval of the first processed signal Sp1 is regarded as 1 When 1 unit, the time interval of the first converted signal Sc1 converted from the first processed signal Sp1 through the first sampling frequency converter 130 should be 1.25 units, because the frequency of the signal will not change after the signal is processed by the second signal processing module 120 , so the time interval of the second processed signal Sp2 remains at 1.25 units, and the time interval of the second converted signal Sc2 converted from the second processed signal Sp2 through the second sampling frequency converter 140 should be restored to 1 unit. Please note that those skilled in the art should be familiar with how the first sampling frequency converter 130 converts the signal frequency from 800MHz to 1GHz, and how the second sampling frequency converter 140 converts the signal frequency from 1GHz to 800MHz. For the sake of brevity and brevity, the relevant detailed descriptions are omitted here.

Please note that none of the above-mentioned embodiments considers the frequency offset (frequency offset) or phase offset (phase offset). If the frequency offset or phase offset is considered, the timing controller 150 will adjust the signal by timing Provide a compensation amount to dynamically compensate the sampling frequency converter; assuming that the first sampling frequency converter 130 and the second sampling frequency converter 140 are both interpolators, and the frequency conversion is performed by interpolation, the timing controller 150 A compensation amount offset is provided by the first timing adjustment signal Sadj1 to control the time interval for the first sampling frequency converter 130 to interpolate the first processed signal Sp1 to dynamically compensate the first sampling frequency converter 130; similarly, the timing The controller 150 also provides the compensation amount offset through the second timing adjustment signal Sadj2 to control the time interval for the second sampling frequency converter 140 to interpolate the second processing signal Sp2, so as to dynamically compensate the second sampling frequency converter 140, so that The timing of the second switching signal Sc2 is substantially equal to the timing of the first processing signal Sp1. For example, when frequency offset or phase offset is not considered, the interpolation time interval of the first sampling frequency converter 130 is fixed at 1.25 units, and when frequency offset or phase offset is considered , the time interval for the first sampling frequency converter 130 to perform interpolation will become (1.25+offset) units. In addition, dynamic compensation methods can be subdivided into phase-locked loop (phase-locked loop, PLL) and voltage-controlled oscillator (voltage controlled oscillator, VCO). The interval is (1.25+offset) units, and the remaining time intervals are still maintained at 1.25 units, where the compensation amount offset is a certain value; if VCO is used for compensation, each time interval is (1.25+offset) units, And the timing controller 150 continuously updates the magnitude of the compensation amount offset each time. Please note that since those skilled in the art should be familiar with the detailed device and operation method of how to use the PLL and VCO to dynamically compensate the time gap, the relevant detailed description is omitted here for the sake of brevity.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims (9)

1. A network signal processing device, comprising: A first signal processing module, operating in an asynchronous domain, for processing network signals to output a first processed signal; A first sampling frequency converter, coupled to the first signal processing module, is used to adjust the signal according to the first timing sequence to perform signal frequency conversion on the first processed signal, and output a first converted signal; a second signal processing module, operating in a synchronous domain and coupled to the first sampling frequency converter, for processing the first converted signal to output a second processed signal; The second sampling frequency converter is coupled between the first signal processing module and the second signal processing module, and is used to adjust the signal according to the second timing to perform signal frequency conversion on the second processed signal, and output a second converting signals into the first signal processing module; and a timing controller, coupled to the first and second sampling frequency converters, for generating the first timing adjustment signal to the first sampling frequency converter, and generating the second timing adjustment signal to the second sampling frequency The converter is used to adjust the timing of the first and second conversion signals. 2. The network signal processing device according to claim 1, wherein the first signal processing module comprises: an analog-to-digital converter for performing analog-to-digital conversion on the network signal to output a digital signal; and The feed-forward equalizer is coupled to the analog-to-digital converter and used for equalizing the digital signal to output the first processed signal. 3. The network signal processing device according to claim 1, wherein the second signal processing module comprises: a cutter, configured to cut the first converted signal to output a cutting signal; and The computing unit is coupled to the cutter, and is used for computing the first converted signal and the cutting signal to output the second processed signal. 4. The network signal processing device according to claim 1, wherein the timing controller outputs the first and second timing adjustment signals according to the second processing signal. 5. The network signal processing device according to claim 1, wherein the second processed signal is an error signal. 6. The network signal processing device according to claim 1, wherein the first and second sampling rate converters are interpolators. 7. The network signal processing device according to claim 6, wherein the first sampling frequency converter determines a time interval for interpolating the first processed signal according to the first timing adjustment signal, and the second sampling frequency The converter determines a time interval for interpolating the second processed signal according to the second timing adjustment signal. 8. The network signal processing device according to claim 6, wherein the timing controller dynamically compensates for each time interval that the first SFC performs interpolation, and dynamically compensates that the second SFC performs interpolation. Interpolate each time interval. 9. The network signal processing device according to claim 1, which is installed in an Ethernet system.

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