CN101860362B - Dual-loop tuning method for low-vibration high frequency difference frequency and phase locking and electrical architecture thereof - Google Patents
Dual-loop tuning method for low-vibration high frequency difference frequency and phase locking and electrical architecture thereof Download PDFInfo
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- CN101860362B CN101860362B CN2010102045935A CN201010204593A CN101860362B CN 101860362 B CN101860362 B CN 101860362B CN 2010102045935 A CN2010102045935 A CN 2010102045935A CN 201010204593 A CN201010204593 A CN 201010204593A CN 101860362 B CN101860362 B CN 101860362B
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Abstract
The invention discloses a dual-loop tuning method for realizing low-vibration high frequency difference frequency and phase locking and an electrical architecture thereof. The electrical architecture comprises dual loops used for respectively tuning frequency and phase. The method comprises the steps of: determining a total real-time phase error between a reference clock and a feedback clock by an interpolator and a phase and frequency detector; separating and extracting the total real-time phase error into a real-time phase error with two frequency components, namely static/low frequency offset and modulation frequency offset, by a low-pass filter; tracking the static/low frequency offset through a frequency locking loop by the real-time phase error of the static/low frequency offset; and tracking whether the phase between the reference clock and the feedback clock is aligned or not through a phase locking loop by using the real-time phase error of the modulation frequency offset and the clock phase outputted by the frequency locking loop. The dual-loop frequency and phase locking architecture can effectively avoid the increase of high-frequency vibration without increasing loop gain or bandwidth.
Description
Technical field
The present invention relates to the clock and data recovery technology in a kind of data communication field; Be particularly related in a kind of data communication fixing or the modulating frequency imbalance is serious keeps phase locking down and slow down dicyclo frequency locking and the phase-lock technique and the electricity structure thereof of significantly shake, belong to electricity field.
Background technology
The design of Modern High-Speed data communication system has extensively been adopted in original data stream to embed the clock timing information and carry out clock recovery.It provides higher data transfer rate, and better reliability reduces generation of noise, improves noise robustness and reduces the power consumption cost.In order further to reduce electromagnetic interference (EMI), clock spread spectrum (SSC) technology is used in Energy distribution to the limited frequency range.Clock frequency is transferred on the lower frequency, as being 30kHz～33kHz in the PCI-Express agreement, has defined the shape and the amplitude of envelope simultaneously, and like the sawtooth waveforms shape, amplitude is 5000ppm.
As a rule, the clock frequency of the clock frequency of receiver and transmitter is unequal.On this static frequency misalignment, the modulation of clock spread spectrum can further increase the frequency misalignment between transmitter and receiver.Such as, in the PCI-Express interface, the static frequency imbalance can reach 600ppm, and dynamically maximum simultaneously peak-peak modulating frequency imbalance can reach 10000ppm.
In the conventional method, reach the big like this real-time frequency imbalance of tracking through gain or the bandwidth that increases clock recovery loop.But higher clock recovery bandwidth causes loop gain excessive, thereby has increased the high dither of recovered clock.Therefore need seek a kind of in the method that is not increasing the big frequency misalignment follow-up control of acquisition under the recovered clock jitter conditions.
Summary of the invention
In view of the defective and the active demand of above-mentioned prior art, the objective of the invention is to propose a kind of dicyclo control method and electrical architecture thereof of low jitter high frequency difference frequency frequency locking lock phase, even solve a difficult problem of following the tracks of big frequency misalignment in the clock recovery loop.
First purpose of the present invention will be achieved through following technical scheme:
The dicyclo control method of low jitter high frequency difference frequency frequency locking lock phase is characterized in that comprising the double loop that is used for difference tuned frequency and phase place, the steps include: I, frequency locked loop and phased lock loop are set; II, confirm the total instant phase error between reference clock and the feedback clock through interpolation device and phase frequency detector; III, utilize low pass filter, total instant phase error separation and Extraction is become the lack of proper care instant phase error of two frequency components of static state/low frequency frequency misalignment and modulating frequency; IV, utilize the instant phase error of static state/low frequency frequency misalignment, follow the tracks of and regulate static state/low frequency frequency misalignment through frequency locked loop; Whether V, the instant phase error of utilizing modulating frequency to lack of proper care reach from the clock phase of frequency locked loop output, aim at through the phase place that phased lock loop is followed the tracks of and regulated between reference clock and the feedback clock.
Further; The dicyclo control method of above-mentioned low jitter high frequency difference frequency frequency locking lock phase; Wherein this dicyclo frequency locking and phase-lock technique are through computer run; The instant phase frequency error and the filtering bandwidth of static state/low frequency frequency misalignment and two components of modulating frequency imbalance all are stored in the computer-readable recording medium of computer, search for calling.
Further, the dicyclo control method of above-mentioned low jitter high frequency difference frequency frequency locking lock phase wherein in this step II before or after the instant phase error of two frequency components of separation and Extraction, also comprises instant phase error is carried out the process that loop filters.
Second purpose of the present invention, its technological means that is achieved is:
The electrical architecture that low jitter high frequency difference frequency frequency locking lock phase dicyclo is regulated, it is characterized in that: said Two-ring lock electrical architecture comprises phase frequency detector, loop filter, low pass filter, local clock generator and phase place delay unit; Reference clock and feedback clock are imported phase frequency detector respectively; And phase frequency detector is exported linkloop filter and low pass filter in order; The static state of said low pass filter/low frequency component output is connected directly to local clock generator; And the modulating frequency component output terminal subtracts through a phase place and adds device and be connected to the phase place delay unit, and feedback exports phase frequency detector to; Wherein the high fdrequency component output of low pass filter and phase place delay unit and phase frequency detector constitute phase-locked loop; And the static state/low frequency component of said low pass filter exports local clock generator to, and constitutes frequency locked loop in the lump with phase place delay unit, phase frequency detector and loop filter.
Further, the electrical architecture that aforementioned low jitter high frequency difference frequency frequency locking lock phase dicyclo is regulated, wherein phase frequency detector comprises the frequency plot detector that produces numeral, simulation or the instant phase error signal of mixed type.
Further, the electrical architecture that aforementioned low jitter high frequency difference frequency frequency locking lock phase dicyclo is regulated, wherein this frequency locked loop is an analog form, comprises the phase place delay unit of local clock generator and the aanalogvoltage or the Current Control of aanalogvoltage or Current Control; Perhaps this frequency locked loop is a digital form, comprises the phase place delay unit of local clock generator and the digital voltage or the Current Control of digital voltage or Current Control.
Further, the electrical architecture that aforementioned low jitter high frequency difference frequency frequency locking lock phase dicyclo is regulated, wherein this phase-locked loop is an analog form, comprises the phase place delay unit of aanalogvoltage or Current Control; Perhaps this phase-locked loop is a digital form, comprises the phase place delay unit of digital voltage or Current Control.
Further, the electrical architecture that aforementioned low jitter high frequency difference frequency frequency locking lock phase dicyclo is regulated, wherein in this frequency locked loop or the phase-locked loop, loop filter is located at the rear end of the front end or the low pass filter of low pass filter.
Further; The electrical architecture that aforementioned low jitter high frequency difference frequency frequency locking lock phase dicyclo is regulated; Wherein when this loop filter is located at the low pass filter front end; Between the phase frequency detector of simulation and digital loop filter, be provided with the analog to digital converter of N bit, or between the loop filter of the phase frequency detector of numeral and simulation, be provided with the digital to analog converter of N bit.
Further; The electrical architecture that aforementioned low jitter high frequency difference frequency frequency locking lock phase dicyclo is regulated; Wherein when this loop filter is located at the low pass filter rear end; Between the phase frequency detector of simulation and digital low pass filter, be provided with the analog to digital converter of N bit, or between the low pass filter of the phase frequency detector of numeral and simulation, be provided with the digital to analog converter of N bit.
After the technical scheme application implementation of the present invention, compare to the outstanding technique effect of prior art and be:
This frequency locking lock phase dicyclo control method and electrical architecture thereof; Output separation through filtering out from phase frequency detector obtains phase error; And utilize the instant phase error signal driving frequency locked loop of static state/low frequency frequency misalignment, follow the tracks of static state/low frequency frequency misalignment with this.This dicyclo framework need not to increase loop gain or bandwidth, can effectively avoid the increase of high dither.
Description of drawings
Fig. 1 is based on the clock and data recovery module of interpolation device in the data communication;
Fig. 2 is the situation of the real-time frequency imbalance under static state and the frequency hopping modulation;
Fig. 3 is the dicyclo configuration diagram of FLL of the present invention and phase-locked loop.
Embodiment
Following constipation closes the embodiment accompanying drawing, and specific embodiments of the invention is done further to detail, so that the details of technical scheme of the present invention is able to more fully show that its inner characteristic is easier to understand, grasp.What need point out is: following narration about embodiment is not restrictive, and the same creation that those skilled in the art use other approach to accomplish though do not explain wherein particularly, is included within the protection range of patent application of the present invention equally.Method of the present invention is I, confirms the total instant phase error between reference clock and feedback clock through interpolation device and phase frequency detector; II, adopt the low pass filter separation and Extraction to become the instant phase error of static state/low frequency frequency misalignment and two frequency components of modulating frequency imbalance total instant phase error; III, utilize the instant phase error of static state/low frequency frequency misalignment, follow the tracks of static state/low frequency frequency misalignment through frequency locked loop; Whether IV, the instant phase error of utilizing modulating frequency to lack of proper care reach from the clock phase of frequency locked loop output, aim at through the phase place between phase-locked loop track reference clock and feedback clock.
In general, the phase-frequency detector comparison be phase place and the frequency between local clock (feedback clock) and a reference clock (being also referred to as reference clock) signal, this reference clock signal possibly be to be embedded in the data or clock that receive.Shown in Figure 1 is in the data communication based on the clock and data recovery module of interpolation device.As shown in Figure 1, phase frequency detector 100 is used to detect instant phase place and frequency error signal, and through an interpolation device 120 postpone or in advance local clock with recovered clock and the alignment of data that receives.Phase frequency detector 100 is according to instant phase frequency difference output pulse up or down, then by filter 110 filtering.Filtered signal is used to control the frequency and the phase place of the clock signal of being sent here by interpolation device 120.The multipath clock phase place that interpolation device uses can be realized by the local clock generator very easily.
As shown in Figure 2, description be the example of frequency shift (FS) between transmitter and the receiver.Usually between transmitter and receiver, there is a fixing frequency departure fsos, equals 600ppm such as fsos in PCI-Express.On the basis of static frequency difference, the frequency of transmitter and receiver is also simultaneously modulated.Modulating frequency is generally lower, in the PCI-Express agreement, is 30kHz～33kHz.Modulation signal is the cycle, such as triangular wave etc.Modulation between transmitter and receiver can be asynchronous.Therefore can be more than the twice of modulating frequency at the real-time frequency deviation fmos of the maximum between transmitter and receiver, such as in PCI-Express, reaching 10000ppm.Total real-time frequency deviation is static frequency deviation and modulating frequency deviation sum, and in order to follow the tracks of so big frequency departure, the bandwidth of typical second order clock recovery loop needs to increase.But this has increased the shake of clock loop simultaneously; Because phase frequency detector is delayed time, and loop bandwidth also is subject to the requirement of loop stability, therefore increasing bandwidth is not a good method at this simultaneously.
The FLL of the present invention as shown in Figure 3 and the dicyclo framework of phase-locked loop.This Two-ring lock electrical architecture comprises phase frequency detector 300, loop filter 310, low pass filter 320, local clock generator 330 and phase place delay unit 340; Reference clock and feedback clock are imported phase frequency detector respectively; And phase frequency detector is exported linkloop filter and low pass filter in order; The static state of said low pass filter/low frequency component output is connected directly to local clock generator; And the modulating frequency component output terminal subtracts through a phase place and adds device and be connected to the phase place delay unit, and feedback exports phase frequency detector to; Wherein the high fdrequency component output of low pass filter and phase place delay unit and phase frequency detector constitute phase-locked loop; And the static state/low frequency component of said low pass filter exports local clock generator to, and constitutes frequency locked loop in the lump with phase place delay unit, phase frequency detector and loop filter.Wherein, phase frequency detector 300 is through comparing the instant phase difference of timing sequence generating between reference clock and the feedback clock.The instant phase error Errorlf that is caused by static state or low frequency frequency misalignment is extracted by low pass filter 320.The instant phase error composition of other high frequency Errorhf can obtain through Errorlf is deducted from total phase error.Errorlf is used in advance or delays the clock of local clock generator 330, so the frequency of the local clock frequency that will come the track reference clock with the static of 0ppm or low frequency frequency departure.Errorhf is used for postponing or the phase place of the clock that comes out from frequency locked loop in advance through a delay cell 340 (for example interpolation device), come between track reference clock and feedback clock instant phase alignment whether.Frequency locked loop can be followed the tracks of frequency departure static or low frequency fully.It is because phase-locked loop need not followed the tracks of big static state or low frequency frequency departure that the bandwidth of phase-locked loop need not very high this.
The preferred version of the foregoing description also comprises; This dicyclo frequency locking and phase-lock technique are through computer run; The instant phase frequency error and the filtering bandwidth of static state/low frequency frequency misalignment and two components of modulating frequency imbalance all are stored in the computer-readable recording medium of computer, search for calling.
Before or after the instant phase error of two frequency components of above-mentioned separation and Extraction, also comprise instant phase error is carried out the process that loop filters.
This frequency locked loop is an analog form, comprises the phase place delay unit of local clock generator and the aanalogvoltage or the Current Control of aanalogvoltage or Current Control; Perhaps this frequency locked loop is a digital form, comprises the phase place delay unit of local clock generator and the digital voltage or the Current Control of digital voltage or Current Control; This phase-locked loop is an analog form, comprises the phase place delay unit of aanalogvoltage or Current Control; Perhaps this phase-locked loop is a digital form, comprises the phase place delay unit of digital voltage or Current Control.
Further, in this frequency locked loop or the phase-locked loop, loop filter is located at the rear end of the front end or the low pass filter of low pass filter.When loop filter is located at the low pass filter front end, between the phase frequency detector of simulation and digital loop filter, is provided with the analog to digital converter of N bit, or between the loop filter of the phase frequency detector of numeral and simulation, is provided with the digital to analog converter of N bit; When loop filter is located at the low pass filter rear end, between the phase frequency detector of simulation and digital low pass filter, is provided with the analog to digital converter of N bit, or between the low pass filter of the phase frequency detector of numeral and simulation, is provided with the digital to analog converter of N bit.
The present invention is applicable to clock recovery or phase-locked loop, and some other application that possibly comprise are presented as the filter of non-adjustable bandwidth under the low frequency frequency deviation condition etc.In sum, the technical characterstic of low jitter high frequency difference frequency frequency locking of the present invention lock phase dicyclo control method and electrical architecture thereof is detail comprehensively, and this dicyclo framework need not to increase loop gain or bandwidth, can effectively avoid the increase of high dither.
Claims (11)
1. the dicyclo control method of low jitter high frequency difference frequency frequency locking lock phase is characterized in that comprising the double loop that is used for difference tuned frequency and phase place, the steps include:
I, frequency locked loop and phased lock loop are set;
II, confirm the total instant phase error between reference clock and the feedback clock through interpolation device and phase frequency detector;
III, utilize low pass filter, total instant phase error separation and Extraction is become the lack of proper care instant phase error of two frequency components of static state/low frequency frequency misalignment and modulating frequency;
IV, utilize the instant phase error of static state/low frequency frequency misalignment, follow the tracks of and regulate static state/low frequency frequency misalignment through frequency locked loop;
Whether V, the instant phase error of utilizing modulating frequency to lack of proper care reach from the clock phase of frequency locked loop output, aim at through the phase place that phased lock loop is followed the tracks of and regulated between reference clock and the feedback clock.
2. the dicyclo control method of low jitter high frequency difference frequency frequency locking lock phase according to claim 1; It is characterized in that: said frequency locking and lock phase dicyclo control method are through computer run; The instant phase frequency error and the filtering bandwidth of static state/low frequency frequency misalignment and two components of modulating frequency imbalance all are stored in the computer-readable recording medium of computer, search for calling.
3. the dicyclo control method of low jitter high frequency difference frequency frequency locking lock phase according to claim 1; It is characterized in that: before or after the instant phase error of two frequency components of separation and Extraction, also comprise instant phase error is carried out the process that loop filters in the step III.
4. the electrical architecture that low jitter high frequency difference frequency frequency locking lock phase dicyclo is regulated is characterized in that: comprise phase frequency detector, loop filter, low pass filter, local clock generator and phase place delay unit; Reference clock and feedback clock are imported phase frequency detector respectively; And phase frequency detector is exported linkloop filter and low pass filter in order; The static state of said low pass filter/low frequency component output is connected directly to local clock generator; And the modulating frequency component output terminal subtracts through a phase place and adds device and be connected to the phase place delay unit, and feedback exports phase frequency detector to; Wherein loop filter and phase place subtract and add device, phase place delay unit and phase frequency detector constitutes phase-locked loop; And the static state/low frequency component of said low pass filter exports local clock generator to, and constitutes frequency locked loop in the lump with phase place delay unit, phase frequency detector and loop filter.
5. the electrical architecture that low jitter high frequency difference frequency frequency locking lock phase dicyclo according to claim 4 is regulated, it is characterized in that: said phase frequency detector comprises the frequency plot detector that produces numeral, simulation or the instant phase error signal of mixed type.
6. the electrical architecture that low jitter high frequency difference frequency frequency locking lock phase dicyclo according to claim 4 is regulated; It is characterized in that: said frequency locked loop is an analog form, comprises the phase place delay unit of local clock generator and the aanalogvoltage or the Current Control of aanalogvoltage or Current Control.
7. the electrical architecture that low jitter high frequency difference frequency frequency locking lock phase dicyclo according to claim 4 is regulated; It is characterized in that: said frequency locked loop is a digital form, comprises the phase place delay unit of local clock generator and the digital voltage or the Current Control of digital voltage or Current Control.
8. the electrical architecture that low jitter high frequency difference frequency frequency locking lock phase dicyclo according to claim 4 is regulated, it is characterized in that: said phase-locked loop is an analog form, comprises the phase place delay unit of aanalogvoltage or Current Control.
9. the electrical architecture that low jitter high frequency difference frequency frequency locking lock phase dicyclo according to claim 4 is regulated, it is characterized in that: said phase-locked loop is a digital form, comprises the phase place delay unit of digital voltage or Current Control.
10. the electrical architecture that low jitter high frequency difference frequency frequency locking lock phase dicyclo according to claim 4 is regulated, it is characterized in that: in the said frequency locked loop, loop filter is located at the front end of low pass filter.
11. the electrical architecture that low jitter high frequency difference frequency frequency locking lock phase dicyclo according to claim 10 is regulated; It is characterized in that: when loop filter is located at the low pass filter front end; Between the phase frequency detector of simulation and digital loop filter, be provided with the analog to digital converter of N bit, or between the loop filter of the phase frequency detector of numeral and simulation, be provided with the digital to analog converter of N bit.
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| CN102882518A (en) * | 2012-10-24 | 2013-01-16 | 四川和芯微电子股份有限公司 | Phase-locked loop system and implementation method for same |
| CN104639158B (en) * | 2014-12-30 | 2018-08-14 | 广东大普通信技术有限公司 | Synchronous two phase-locked loop adjusting method |
| US10057051B2 (en) * | 2015-05-29 | 2018-08-21 | Silicon Laboratories Inc. | Dual path timing wander removal |
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| CN1650523A (en) * | 2002-03-12 | 2005-08-03 | 高通股份有限公司 | Sigma-delta modulator controlled phase locked loop with a noise shaped dither |
| CN101729066A (en) * | 2008-10-31 | 2010-06-09 | 中芯国际集成电路制造(上海)有限公司 | Sigma-Delta modulation circuit and method as well as corresponding phase-locked loop |
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| US6563389B1 (en) * | 2001-10-24 | 2003-05-13 | Northrop Grumman Corporation | Phase locked loop with charge injection cancellation |
| KR100733471B1 (en) * | 2005-02-28 | 2007-06-28 | 주식회사 하이닉스반도체 | Delay locked loop circuit in semiductor and its control method |
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| CN1650523A (en) * | 2002-03-12 | 2005-08-03 | 高通股份有限公司 | Sigma-delta modulator controlled phase locked loop with a noise shaped dither |
| CN101729066A (en) * | 2008-10-31 | 2010-06-09 | 中芯国际集成电路制造(上海)有限公司 | Sigma-Delta modulation circuit and method as well as corresponding phase-locked loop |
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