JP2010225726A - Multi-pattern wiring board, wiring board, package for housing electronic components, and electronic apparatus - Google Patents

Multi-pattern wiring board, wiring board, package for housing electronic components, and electronic apparatus Download PDF

Info

Publication number
JP2010225726A
JP2010225726A JP2009069520A JP2009069520A JP2010225726A JP 2010225726 A JP2010225726 A JP 2010225726A JP 2009069520 A JP2009069520 A JP 2009069520A JP 2009069520 A JP2009069520 A JP 2009069520A JP 2010225726 A JP2010225726 A JP 2010225726A
Authority
JP
Japan
Prior art keywords
wiring board
dividing
odd
groove
divided
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2009069520A
Other languages
Japanese (ja)
Other versions
JP5178595B2 (en
Inventor
Tetsuya Tojo
哲也 東條
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2009069520A priority Critical patent/JP5178595B2/en
Publication of JP2010225726A publication Critical patent/JP2010225726A/en
Application granted granted Critical
Publication of JP5178595B2 publication Critical patent/JP5178595B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Structure Of Printed Boards (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multi-pattern wiring board that is divided along the dividing groove with high accuracy, and to provide a wiring board, a package for housing electronic components, and an electronic apparatus. <P>SOLUTION: In a multi-pattern wiring board 1, a plurality of insulating layers 11-15 are laminated, and a plurality of board areas E<SB>11</SB>-E<SB>55</SB>to be divided as a wiring board is formed in a matrix. Dividing grooves S<SB>odd</SB>and S<SB>even</SB>are formed in a boarder part between the board areas E<SB>11</SB>-E<SB>55</SB>to each of the insulating layers 11-15. The dividing grooves S<SB>odd</SB>and S<SB>even</SB>have a first diving groove S<SB>odd</SB>formed in odd-numbered insulating layers 11, 13 and 15, and a second dividing groove S<SB>even</SB>formed in even-numbered insulating layers 12 and 14 and formed not to be overlapped with the first dividing groove S<SB>odd</SB>in a planar view. In the planar view, the first dividing groove S<SB>odd</SB>and the second dividing groove S<SB>even</SB>are adjacent to each other along a dividing direction. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、配線基板として分割されるべき基板領域が、縦横の並びに複数配列形成された多数個取り配線基板、配線基板、電子部品収納用パッケージ、および電子装置に関する。   The present invention relates to a multi-piece wiring board, a wiring board, an electronic component storage package, and an electronic device in which a plurality of board regions to be divided as wiring boards are formed in a vertical and horizontal arrangement.

圧電振動子、半導体素子、水晶振動子等の電子部品を装着するための配線基板は、一般に、多数個取り配線基板を個片化することによって製造される。すなわち、この多数個取り配線基板は、複数の絶縁層が積層されており、配線基板として分割されるべき基板領域が、縦横の並びに複数配列形成されている(例えば、特許文献1参照)。また、この多数個取り配線基板には、隣接する基板領域の境界部分において、分割溝が形成されている。つまり、この分割溝に沿って基板領域を分割することにより、複数の配線基板を取り出すことができる。なお、従来では、分割のし易さ等を考慮して、多数個取り配線基板の表面だけでなく、内層の絶縁層のうち一部の絶縁層にも分割溝を形成することが行われていた(例えば、特許文献2参照)。   A wiring board for mounting electronic parts such as a piezoelectric vibrator, a semiconductor element, and a crystal vibrator is generally manufactured by separating a multi-piece wiring board. That is, this multi-cavity wiring board has a plurality of insulating layers laminated, and a plurality of substrate regions to be divided as a wiring board are formed in a vertical and horizontal arrangement (see, for example, Patent Document 1). In addition, the multi-cavity wiring substrate is formed with a dividing groove at a boundary portion between adjacent substrate regions. That is, a plurality of wiring boards can be taken out by dividing the substrate region along the dividing grooves. Conventionally, in consideration of easiness of division and the like, dividing grooves are formed not only on the surface of the multi-layer wiring substrate but also on some of the inner insulating layers. (For example, see Patent Document 2).

特開2006−41269号公報JP 2006-41269 A 特開2007−294797号公報JP 2007-294797 A

しかしながら、上記従来の多数個取り配線基板では、その表面と、内層の絶縁層のうち一部の絶縁層とに分割溝が形成されていたので、次のような問題が生じる可能性があった。すなわち、内層の絶縁層のうち分割溝が形成されていない絶縁層が存在しているので、基板領域を分割する際に、分割溝に沿って正確に(真っ直ぐに)分割することができないという問題である。分割溝に沿って正確に分割することができないので、分割した配線基板のそれぞれは、形や大きさ等が異なることがあった。   However, since the conventional multi-cavity wiring board has split grooves formed on the surface and some of the inner insulating layers, the following problems may occur. . That is, since there is an insulating layer in which the dividing groove is not formed among the insulating layers of the inner layer, when dividing the substrate region, it is impossible to accurately (straightly) divide along the dividing groove. It is. Since it cannot be accurately divided along the dividing groove, the divided wiring boards may have different shapes and sizes.

本発明は、上記の問題点に鑑みてなされたものであり、その目的は、分割溝に沿って正確に分割することができる多数個取り配線基板、配線基板、電子部品収納用パッケージ、および電子装置に関する。   The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a multi-piece wiring board, a wiring board, an electronic component storage package, and an electronic device that can be accurately divided along the dividing groove. Relates to the device.

上記目的を達成するために本発明における多数個取り配線基板は、複数の絶縁層が積層されており、配線基板として分割されるべき基板領域が、複数配列形成された多数個取り配線基板であって、複数の前記絶縁層のそれぞれには、前記基板領域同士の境界部分に分割溝が形成されており、前記分割溝は、奇数番目の絶縁層に形成された第1分割溝と、偶数番目の絶縁層に形成されており、かつ前記第1分割溝と平面視において重ならないようにして形成された第2分割溝とを有し、平面視において、前記第1分割溝と前記第2分割溝とが、分割する方向に沿って、互いに隣り合っている。   In order to achieve the above object, the multi-cavity wiring board according to the present invention is a multi-cavity wiring board in which a plurality of insulating layers are laminated and a substrate region to be divided as a wiring board is formed in a plurality of arrays. In each of the plurality of insulating layers, a dividing groove is formed at a boundary portion between the substrate regions, and the dividing groove includes an even-numbered first dividing groove formed in an odd-numbered insulating layer. And a second divided groove formed so as not to overlap the first divided groove in a plan view, and the first divided groove and the second divided groove in a plan view. The grooves are adjacent to each other along the dividing direction.

上記目的を達成するために本発明における配線基板は、本発明に係る多数個取り配線基板における、前記基板領域を分割することによって得られる。   In order to achieve the above object, the wiring board according to the present invention is obtained by dividing the substrate region in the multi-cavity wiring board according to the present invention.

上記目的を達成するために本発明における電子部品収納用パッケージは、本発明に係る配線基板を用いる。   In order to achieve the above object, a wiring board according to the present invention is used in an electronic component storage package according to the present invention.

上記目的を達成するために本発明における電子装置は、本発明に係る電子部品収納用パッケージと、前記電子部品収納用パッケージに収納された電子部品とを備える。   In order to achieve the above object, an electronic device according to the present invention includes an electronic component storage package according to the present invention and an electronic component stored in the electronic component storage package.

本発明の多数個取り配線基板、配線基板、電子部品収納用パッケージ、および電子装置は、分割溝に沿って正確に分割することがきるという効果を奏する。   The multi-cavity wiring board, the wiring board, the electronic component storage package, and the electronic device according to the present invention have an effect that they can be accurately divided along the dividing groove.

図1は、本発明の一実施形態に係る多数個取り配線基板の一例を示す平面図である。FIG. 1 is a plan view showing an example of a multi-piece wiring board according to an embodiment of the present invention. 図2は、図1中に示した切断線A−A´に沿って切断した断面図である。2 is a cross-sectional view taken along the cutting line AA ′ shown in FIG. 図3は、本発明の一実施形態に係る多数個取り配線基板の他の例を示す拡大平面図である。FIG. 3 is an enlarged plan view showing another example of the multi-piece wiring board according to the embodiment of the present invention. 図4は、本発明の一実施形態に係る多数個取り配線基板のさらに他の例を示す断面図である。FIG. 4 is a cross-sectional view showing still another example of the multi-piece wiring board according to the embodiment of the present invention. 図5は、本発明の一実施形態に係る電子装置の一例を示す断面図である。FIG. 5 is a cross-sectional view showing an example of an electronic device according to an embodiment of the present invention.

以下、本発明の実施形態について、図面を参照しながら説明する。   Hereinafter, embodiments of the present invention will be described with reference to the drawings.

但し、以下で参照する各図は、説明の便宜上、本発明の一実施形態の構成部材のうち、本発明を説明するために必要な主要部材のみを簡略化して示したものである。したがって、本発明に係る多数個取り配線基板、配線基板、電子部品収納用パッケージ、および電子装置は、本明細書が参照する各図に示されていない任意の構成部材を備え得る。また、各図中の部材の寸法は、実際の構成部材の寸法および各部材の寸法比率等を忠実に表したものではない。   However, in the drawings referred to below, for the convenience of explanation, among the constituent members of one embodiment of the present invention, only the main members necessary for explaining the present invention are shown in a simplified manner. Therefore, the multi-cavity wiring board, the wiring board, the electronic component storage package, and the electronic device according to the present invention can include arbitrary components not shown in the drawings referred to in this specification. Moreover, the dimension of the member in each figure does not represent the dimension of an actual structural member, the dimension ratio of each member, etc. faithfully.

図1は、本発明の一実施形態に係る多数個取り配線基板1の一例を示す平面図である。図2は、図1中に示した切断線A−A´に沿って切断した断面図である。   FIG. 1 is a plan view showing an example of a multi-piece wiring board 1 according to an embodiment of the present invention. 2 is a cross-sectional view taken along the cutting line AA ′ shown in FIG.

図1に示すように、本実施形態に係る多数個取り配線基板1は、配線基板として分割されるべき基板領域E11〜E55が、縦横の並びに複数配列形成されている。具体的には、基板領域E11〜E55は、平面視において多数個取り配線基板1の略中央部Pに形成されている。また、基板領域E11〜E55のそれぞれには、電子部品を装着するための装着部(図示せず)が設けられている。さらに、装着部には、タングステン、モリブデン、銅、銀等の金属メタライズからなる配線導体(図示せず)が形成されている。 As shown in FIG. 1, in the multi-piece wiring board 1 according to the present embodiment, a plurality of board regions E 11 to E 55 to be divided as wiring boards are arranged in a vertical and horizontal arrangement. Specifically, the board regions E 11 to E 55 are formed in a substantially central portion P of the multi-piece wiring board 1 in plan view. Each of the board regions E 11 to E 55 is provided with a mounting portion (not shown) for mounting electronic components. Furthermore, a wiring conductor (not shown) made of metal metallization such as tungsten, molybdenum, copper, silver or the like is formed on the mounting portion.

なお、図1では、多数個取り配線基板1に基板領域E11〜E55が25個形成されている例について図示したが、これに限定されない。すなわち、多数個取り配線基板1に形成されるべき基板領域の数については、任意である。 Although FIG. 1 illustrates an example in which 25 substrate regions E 11 to E 55 are formed on the multi-cavity wiring substrate 1, the present invention is not limited to this. That is, the number of substrate regions to be formed on the multi-piece wiring board 1 is arbitrary.

また、図2に示すように、本実施形態に係る多数個取り配線基板1は、複数の絶縁層11〜15が積層されることによって構成される。ここで、絶縁層11〜15は、セラミックス、シリコン、ガラス等の絶縁性材料からなるが、特に、セラミックスからなるのが好ましい。セラミックスは、例えば、酸化アルミニウム質焼結体、窒化アルミニウム質焼結体、ムライト質焼結体、炭化珪素質焼結体、窒化珪素質焼結体、ガラスセラミックス焼結体等である。   As shown in FIG. 2, the multi-piece wiring board 1 according to the present embodiment is configured by laminating a plurality of insulating layers 11 to 15. Here, the insulating layers 11 to 15 are made of an insulating material such as ceramics, silicon, or glass, but are particularly preferably made of ceramics. Examples of the ceramic include an aluminum oxide sintered body, an aluminum nitride sintered body, a mullite sintered body, a silicon carbide sintered body, a silicon nitride sintered body, and a glass ceramic sintered body.

なお、図2では、多数個取り配線基板1は、5つの絶縁層11〜15から構成されている例について図示したが、これに限定されない。すなわち、多数個取り配線基板1は、任意の数の絶縁層から構成されていてもよい。   In FIG. 2, an example in which the multi-piece wiring board 1 is configured by five insulating layers 11 to 15 is illustrated, but the invention is not limited thereto. That is, the multi-cavity wiring board 1 may be composed of an arbitrary number of insulating layers.

ここで、絶縁層11〜15がセラミックスからなる場合、当該絶縁層11〜15は、例えば、次のような方法にて製造される。すなわち、アルミナ、シリカ、マグネシア、カルシア等の原料粉末に、バインダおよび溶剤を添加混合して泥漿状とする。そして、これを従来周知のドクターブレード法を用いることによりシート状に形成し、打ち抜き金型を用いて打ち抜き加工を施すことによって複数のセラミックグリーンシートを生成する。そして、生成したセラミックグリーンシートに、配線導体用のペーストを、従来周知のスクリーン印刷法を用いることにより所定のパターンに印刷塗布する。そして、セラミックグリーンシートを複数枚上下に積層してセラミックグリーンシート積層体を形成するとともに、このセラミックグリーンシート積層体を還元雰囲気中約1600℃の温度で焼成する。このような工程を経ることによって、絶縁層11〜15が製造される。   Here, when the insulating layers 11-15 consist of ceramics, the said insulating layers 11-15 are manufactured by the following methods, for example. That is, a binder and a solvent are added to and mixed with raw material powders such as alumina, silica, magnesia, and calcia to form a slurry. Then, this is formed into a sheet shape by using a conventionally known doctor blade method, and a plurality of ceramic green sheets are generated by punching using a punching die. Then, a paste for wiring conductor is printed and applied to the generated ceramic green sheet in a predetermined pattern by using a conventionally known screen printing method. Then, a plurality of ceramic green sheets are laminated on top and bottom to form a ceramic green sheet laminate, and the ceramic green sheet laminate is fired at a temperature of about 1600 ° C. in a reducing atmosphere. The insulating layers 11 to 15 are manufactured through such steps.

また、基板領域E11〜E55同士の境界部分において、奇数番目の絶縁層11,13,15には、奇数側の分割溝(第1分割溝)Soddが形成されている。また、基板領域E11〜E55同士の境界部分において、偶数番目の絶縁層12,14には、奇数側の分割溝Soddと平面視において重ならないようにして偶数側の分割溝(第2分割溝)Sevenが形成されている。すなわち、平面視において、奇数側の分割溝Soddと偶数側の分割溝Sevenとが、分割する方向に沿って、互いに隣り合っている。 Further, in the boundary portion between the substrate regions E 11 to E 55 , the odd-numbered insulating layers 11, 13, 15 are formed with odd- numbered dividing grooves (first dividing grooves) S odd . Further, in the boundary portion between the substrate regions E 11 to E 55 , the even-numbered insulating layers 12 and 14 are not evenly divided with the odd-numbered dividing grooves S odd in plan view (second grooves) Dividing grooves) S even are formed. That is, in the plan view, the odd-numbered dividing grooves S odd and the even-numbered dividing grooves S even are adjacent to each other along the dividing direction.

また、本実施形態においては、分割溝Sodd,Sevenに沿って基板領域E11〜E55を分割することにより、25個の配線基板を取り出すことができる。なお、分割溝Sodd,Sevenは、例えば、金型、カッター刃、レーザ等を用いて焼成前のセラミックグリーンシートに形成され、その開口幅は、多数個取り配線基板1の厚さや材質等によって異なるが、おおよそ0.01〜0.3mmであることが好ましい。 In the present embodiment, 25 wiring boards can be taken out by dividing the substrate regions E 11 to E 55 along the dividing grooves S odd and S even . The dividing grooves S odd , S even are formed in the ceramic green sheet before firing using, for example, a mold, a cutter blade, a laser, etc., and the opening width is the thickness, material, etc. of the multi-piece wiring board 1. Depending on the case, it is preferably approximately 0.01 to 0.3 mm.

すなわち、奇数番目の絶縁層11,13,15および偶数番目の絶縁層12,14双方に分割溝Sodd,Sevenが形成されているので、基板領域E11〜E55を分割する際、分割溝Sodd,Sevenに沿って正確に分割することができる。このため、分割した配線基板のそれぞれは、形や大きさ等が略同じようになる。 That is, since the dividing grooves S odd and S even are formed in both the odd-numbered insulating layers 11, 13 and 15 and the even-numbered insulating layers 12 and 14, the dividing is performed when the substrate regions E 11 to E 55 are divided. It is possible to accurately divide along the grooves S odd and S even . For this reason, each of the divided wiring boards has substantially the same shape and size.

ここで、図1に示すように、多数個取り配線基板1は、平面視において、奇数側の分割溝Soddと偶数側の分割溝Sevenとが、基板領域E11〜E55毎に交互に形成されていることが好ましい。すなわち、言い換えるならば、平面視において、奇数側の分割溝Soddと偶数側の分割溝Sevenとが、基板領域E11〜E55毎にいわゆる千鳥状に形成されていることが好ましい。これにより、基板領域E11〜E55を分割する際、分割溝Sodd,Sevenに沿って正確に分割することができる。また、基板領域E11〜E55を分割することによって配線基板を取り出した場合に、当該配線基板の側面が分割溝Sodd,Sevenとなるため、分割によって当該配線基板の側面に不要な凸状が形成され、かつ不要な割れが生じることを抑制できる。すなわち、品質の高い配線基板を得ることができる。 Here, as shown in FIG. 1, in the multi-piece wiring board 1, the odd-numbered divided grooves S odd and the even-numbered divided grooves S even are alternately arranged for each of the substrate regions E 11 to E 55 in plan view. It is preferable to be formed. That is, in other words, it is preferable that the odd-numbered dividing grooves S odd and the even-numbered dividing grooves S even are formed in a so-called staggered pattern for each of the substrate regions E 11 to E 55 in plan view. Accordingly, when dividing a substrate region E 11 to E 55, the dividing groove S odd, can be accurately divided along the S the even. Further, when the wiring board is taken out by dividing the substrate regions E 11 to E 55 , the side surface of the wiring board becomes the division grooves S odd , S even , so that unnecessary projections are not formed on the side surface of the wiring board by the division. It can suppress that a shape is formed and an unnecessary crack arises. That is, a high-quality wiring board can be obtained.

また、図3に示すように、平面視において、奇数側の分割溝Soddと偶数側の分割溝Sevenとが、連続して形成されていることが好ましい。なお、図3は、本発明の一実施形態に係る多数個取り配線基板1の他の例を示す拡大平面図である。 Further, as shown in FIG. 3, it is preferable that the odd- numbered dividing grooves S odd and the even-numbered dividing grooves S even are continuously formed in a plan view. FIG. 3 is an enlarged plan view showing another example of the multi-piece wiring board 1 according to an embodiment of the present invention.

すなわち、平面視において、奇数側の分割溝Soddと偶数側の分割溝Sevenとが連続している連続部Cをそれぞれ有しているので、基板領域E11〜E55を分割する際、分割溝Sodd,Sevenに沿ってより正確に分割することができる。 That is, in the plan view, each of the odd-numbered dividing grooves S odd and the even-numbered dividing grooves S even has continuous portions C. Therefore, when dividing the substrate regions E 11 to E 55 , It is possible to more accurately divide along the dividing grooves S odd and S even .

さらに、図4に示すように、奇数側の分割溝Soddおよび偶数側の分割溝Sevenには、埋設部材2が設けられていることが好ましい。なお、図4は、本発明の一実施形態に係る多数個取り配線基板1のさらに他の例を示す断面図である。 Further, as shown in FIG. 4, it is preferable that an embedded member 2 is provided in the odd- numbered dividing groove S odd and the even-numbered dividing groove S even . FIG. 4 is a cross-sectional view showing still another example of the multi-piece wiring board 1 according to an embodiment of the present invention.

ここで、基板領域E11〜E55の装着部に電子部品を装着した後に、基板領域E11〜E55を分割することが一般的である。基板領域E11〜E55の装着部に電子部品を装着した際に、装着時の圧力によって、多数個取り配線基板1が分割溝Sodd,Sevenに沿って割れることがあった。しかしながら、図4に示すように、奇数側の分割溝Soddおよび偶数側の分割溝Sevenに埋設部材2が設けられていれば、基板領域E11〜E55の装着部に電子部品を装着した場合であっても、装着時の圧力によって、多数個取り配線基板1が分割溝Sodd,Sevenに沿って割れることを抑制できる。 Here, after mounting the electronic component on the mounting portion of the substrate region E 11 to E 55, it is common to divide the substrate region E 11 to E 55. When electronic components are mounted on the mounting portions of the board regions E 11 to E 55 , the multi-cavity wiring board 1 may be cracked along the divided grooves S odd , S even due to the pressure at the time of mounting. However, as shown in FIG. 4, if the embedded member 2 is provided in the odd- numbered dividing groove S odd and the even-numbered dividing groove S even , electronic components are mounted on the mounting portions of the board regions E 11 to E 55. Even in this case, the multi-cavity wiring board 1 can be prevented from cracking along the divided grooves S odd and S even due to the pressure at the time of mounting.

また、奇数側の分割溝Soddおよび偶数側の分割溝Sevenに埋設部材2が設けられているので、次のような効果もある。すなわち、絶縁層11〜15がセラミックスからなる場合、上記セラミックグリーンシート積層体の分割溝Sodd,Sevenに埋設部材2が設けられていれば、セラミックグリーンシート積層体の焼成時における、絶縁層11〜15のデラミネーション(層間はく離)を抑制できる。 In addition, since the embedded members 2 are provided in the odd- numbered dividing grooves S odd and the even-numbered dividing grooves S even , the following effects are also obtained. That is, when the insulating layers 11 to 15 are made of ceramics, if the embedded member 2 is provided in the dividing grooves S odd and Seven of the ceramic green sheet laminate, the insulating layer at the time of firing the ceramic green sheet laminate The delamination (delamination) of 11 to 15 can be suppressed.

なお、埋設部材2は、分割溝Sodd,Sevenに沿って基板領域E11〜E55を分割した後に、分割溝Sodd,Sevenから除去される。このため、絶縁層11〜15がセラミックスからなる場合、埋設部材2は、次の材料からなることが好ましい。すなわち、上記セラミックグリーンシート積層体が含有するバインダの質量よりも大きい質量を有するバインダと、上記セラミックグリーンシート積層体が含有するフィラーの質量よりも大きい質量を有するフィラーとを含むセラミックスである。埋設部材2にこのようなセラミックスを用いると、分割溝Sodd,Sevenから容易に埋設部材2を除去できる。 Incidentally, embedded member 2, dividing grooves S odd, after dividing the substrate region E 11 to E 55 along the S the even, the dividing groove S odd, is removed from S the even. For this reason, when the insulating layers 11 to 15 are made of ceramics, the embedded member 2 is preferably made of the following material. That is, the ceramic includes a binder having a mass larger than that of the binder contained in the ceramic green sheet laminate and a filler having a mass larger than that of the filler contained in the ceramic green sheet laminate. When such ceramics are used for the embedded member 2, the embedded member 2 can be easily removed from the dividing grooves S odd and S even .

以上のように、本実施形態に係る多数個取り配線基板1によれば、分割溝Sodd,Sevenに沿って正確に分割することができる。 As described above, according to the multi-cavity wiring board 1 according to the present embodiment, it is possible to accurately divide along the dividing grooves S odd and S even .

なお、本実施形態においては、分割溝Sodd,Sevenに沿って基板領域E11〜E55を分割することにより、25個の配線基板を取り出すことができる。ここで、このようにして取り出した配線基板は、例えば、電子部品収納用パッケージまたは電子装置に用いることができる。図5は、本発明の一実施形態に係る電子装置50の一例を示す断面図である。図5に示すように、本実施形態に係る電子装置50は、基体51、電子部品52、枠体53、および蓋体54を備えている。ここで、基体51および枠体53が、本発明に係る電子部品収納用パッケージの一実施形態となる。 In the present embodiment, 25 wiring boards can be taken out by dividing the substrate regions E 11 to E 55 along the dividing grooves S odd and S even . Here, the wiring board thus taken out can be used, for example, in an electronic component storage package or an electronic device. FIG. 5 is a cross-sectional view showing an example of an electronic device 50 according to an embodiment of the present invention. As shown in FIG. 5, the electronic device 50 according to the present embodiment includes a base 51, an electronic component 52, a frame 53, and a lid 54. Here, the base | substrate 51 and the frame 53 become one Embodiment of the electronic component storage package which concerns on this invention.

基体51は、上面に電子部品52を装着するための装着部51aを有している。すなわち、装着部51a上に、電子部品52が装着される。ここで、本実施形態においては、分割溝Sodd,Sevenに沿って基板領域E11〜E55を分割することにより得られた任意の一の配線基板が、基体51となる。 The base 51 has a mounting portion 51a for mounting the electronic component 52 on the upper surface. That is, the electronic component 52 is mounted on the mounting portion 51a. Here, in the present embodiment, any one wiring substrate obtained by dividing the substrate regions E 11 to E 55 along the dividing grooves S odd and S even becomes the base 51.

枠体53は、基体51の上面であって、かつ電子部品52を囲むようにして設けられている。なお、枠体53は、基体51と一体的に形成されていてもよいし、基体51と別個独立に形成されていてもよい。基体51と枠体53とが別個独立に形成された場合、基体51と枠体53とは、例えば、半田やロウ材等の接続部材を介して接合される。   The frame 53 is provided on the upper surface of the base 51 so as to surround the electronic component 52. Note that the frame 53 may be formed integrally with the base body 51 or may be formed separately from the base body 51. When the base body 51 and the frame body 53 are formed separately and independently, the base body 51 and the frame body 53 are joined via a connecting member such as solder or brazing material, for example.

蓋体54は、枠体53の上面に設けられ、かつ装着部51aに装着された電子部品52を封止するための役割を担う部材である。すなわち、蓋体54は、枠体53によって形成される電子部品52が収容された収容空間を、例えば、真空状態で密閉するように、枠体53の上面に、例えば、半田やロウ材等の接続部材を介して接合される。   The lid body 54 is a member that is provided on the upper surface of the frame body 53 and plays a role for sealing the electronic component 52 mounted on the mounting portion 51a. That is, the lid body 54 is formed on the upper surface of the frame body 53 such as solder or brazing material so that the housing space in which the electronic component 52 formed by the frame body 53 is housed is sealed in a vacuum state, for example. It joins via a connection member.

以上のように、本発明は、分割溝に沿って正確に分割することができる多数個取り配線基板、配線基板、電子部品収納用パッケージ、または電子装置として有用である。   As described above, the present invention is useful as a multi-piece wiring board, a wiring board, an electronic component storage package, or an electronic device that can be accurately divided along the dividing groove.

1 多数個取り配線基板
2 埋設部材
11〜15 絶縁層
50 電子装置
52 電子部品
odd 奇数側の分割溝(第1分割溝)
even 偶数側の分割溝(第2分割溝)
11〜E55 基板領域(配線基板)
DESCRIPTION OF SYMBOLS 1 Multiple wiring board 2 Embedded member 11-15 Insulation layer 50 Electronic device 52 Electronic component S odd Divided groove (first divided groove)
Seven even- numbered dividing groove (second dividing groove)
E 11 to E 55 substrate region (wiring substrate)

Claims (8)

複数の絶縁層が積層されており、配線基板として分割されるべき基板領域が、複数配列形成された多数個取り配線基板であって、
複数の前記絶縁層のそれぞれには、前記基板領域同士の境界部分に分割溝が形成されており、
前記分割溝は、奇数番目の絶縁層に形成された第1分割溝と、偶数番目の絶縁層に形成されており、かつ前記第1分割溝と平面視において重ならないようにして形成された第2分割溝とを有し、
平面視において、前記第1分割溝と前記第2分割溝とが、分割する方向に沿って、互いに隣り合っている、多数個取り配線基板。
A plurality of insulating layers are stacked, and a substrate area to be divided as a wiring board is a multi-cavity wiring board in which a plurality of arrays are formed,
Each of the plurality of insulating layers is formed with a dividing groove at a boundary portion between the substrate regions,
The dividing groove is formed in the first dividing groove formed in the odd-numbered insulating layer and in the even-numbered insulating layer, and is formed so as not to overlap the first dividing groove in plan view. Having two split grooves,
A multi-piece wiring board in which the first dividing groove and the second dividing groove are adjacent to each other along a dividing direction in a plan view.
平面視において、前記第1分割溝と前記第2分割溝とが、前記基板領域毎に交互に形成されている、請求項1に記載の多数個取り配線基板。   The multi-piece wiring board according to claim 1, wherein the first divided grooves and the second divided grooves are alternately formed for each of the substrate regions in a plan view. 平面視において、前記第1分割溝と前記第2分割溝とが、連続して形成されている、請求項1または2に記載の多数個取り配線基板。   The multi-piece wiring board according to claim 1 or 2, wherein the first divided groove and the second divided groove are formed continuously in a plan view. 前記第1分割溝および前記第2分割溝には、埋設部材が設けられている、請求項1〜3のいずれか一項に記載の多数個取り配線基板。   The multi-piece wiring board according to any one of claims 1 to 3, wherein an embedded member is provided in the first divided groove and the second divided groove. 前記絶縁層は、セラミックスからなる、請求項1〜4のいずれか一項に記載の多数個取り配線基板。   The multi-piece wiring board according to claim 1, wherein the insulating layer is made of ceramics. 請求項1〜5のいずれか一項に記載の多数個取り配線基板における、前記基板領域を分割することによって得られる、配線基板。   The wiring board obtained by dividing | segmenting the said board | substrate area | region in the multi-cavity wiring board as described in any one of Claims 1-5. 請求項6に記載の配線基板を用いた、電子部品収納用パッケージ。   An electronic component storage package using the wiring board according to claim 6. 請求項7に記載の電子部品収納用パッケージと、
前記電子部品収納用パッケージに収納された電子部品とを備えた、電子装置。

The electronic component storage package according to claim 7;
An electronic device comprising: an electronic component housed in the electronic component housing package.

JP2009069520A 2009-03-23 2009-03-23 Multi-cavity wiring board, wiring board, electronic component storage package, and electronic device Expired - Fee Related JP5178595B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009069520A JP5178595B2 (en) 2009-03-23 2009-03-23 Multi-cavity wiring board, wiring board, electronic component storage package, and electronic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009069520A JP5178595B2 (en) 2009-03-23 2009-03-23 Multi-cavity wiring board, wiring board, electronic component storage package, and electronic device

Publications (2)

Publication Number Publication Date
JP2010225726A true JP2010225726A (en) 2010-10-07
JP5178595B2 JP5178595B2 (en) 2013-04-10

Family

ID=43042634

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009069520A Expired - Fee Related JP5178595B2 (en) 2009-03-23 2009-03-23 Multi-cavity wiring board, wiring board, electronic component storage package, and electronic device

Country Status (1)

Country Link
JP (1) JP5178595B2 (en)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0376295A (en) * 1989-08-18 1991-04-02 Showa Denko Kk Circuit board aggregate
JPH11112112A (en) * 1997-09-30 1999-04-23 Rohm Co Ltd Sheet for printed substrate
JP2004063803A (en) * 2002-07-29 2004-02-26 Ngk Spark Plug Co Ltd Method of manufacturing printed wiring board, metallic sheet for printed wiring board, and connected printed wiring board
JP2005032773A (en) * 2003-07-07 2005-02-03 Seiko Epson Corp Board divided after mounting
JP2005217099A (en) * 2004-01-29 2005-08-11 Kyocera Corp Multicavity wiring board
JP2007043061A (en) * 2005-06-28 2007-02-15 Kyocera Corp Multi-pattern wiring board
JP2007294797A (en) * 2006-04-27 2007-11-08 Kyocera Corp Ceramic substrate, package for housing electronic component, electronic apparatus, and manufacturing method for them

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0376295A (en) * 1989-08-18 1991-04-02 Showa Denko Kk Circuit board aggregate
JPH11112112A (en) * 1997-09-30 1999-04-23 Rohm Co Ltd Sheet for printed substrate
JP2004063803A (en) * 2002-07-29 2004-02-26 Ngk Spark Plug Co Ltd Method of manufacturing printed wiring board, metallic sheet for printed wiring board, and connected printed wiring board
JP2005032773A (en) * 2003-07-07 2005-02-03 Seiko Epson Corp Board divided after mounting
JP2005217099A (en) * 2004-01-29 2005-08-11 Kyocera Corp Multicavity wiring board
JP2007043061A (en) * 2005-06-28 2007-02-15 Kyocera Corp Multi-pattern wiring board
JP2007294797A (en) * 2006-04-27 2007-11-08 Kyocera Corp Ceramic substrate, package for housing electronic component, electronic apparatus, and manufacturing method for them

Also Published As

Publication number Publication date
JP5178595B2 (en) 2013-04-10

Similar Documents

Publication Publication Date Title
JP6276040B2 (en) Manufacturing method of component mounting package
JP2003092437A (en) Laminated piezoelectric element and its manufacturing method as well as piezoelectric actuator
JP2017098494A (en) Package for mounting optical element, mother board for mounting optical element and electronic device
JP2023091083A (en) Substrate for mounting electronic element, electronic device, and electronic module
JP5178595B2 (en) Multi-cavity wiring board, wiring board, electronic component storage package, and electronic device
JP4277012B2 (en) Multiple wiring board
JP5738109B2 (en) Multiple wiring board
JP6121860B2 (en) Wiring board and electronic device
US20220078909A1 (en) Electronic component mounting substrate and electronic device
JP2007243088A (en) Multilayer ceramic substrate and its manufacturing method
JPWO2019107298A1 (en) Sheet substrate and sheet substrate manufacturing method
JP2007059443A (en) Wiring board for taking a plurality of boards
JP2006041269A (en) Multi-pattern wiring board
US20210362372A1 (en) Method for manufacturing ceramic substrate and ceramic substrate
JP4772730B2 (en) Multiple wiring board, wiring board, and electronic device
JP6955460B2 (en) Electronic element mounting board, electronic element mounting mother board, electronic device and electronic module
JP2010056498A (en) Multi-piece wiring substrate
JP2007234662A (en) Multipiece wiring board
JP2007043061A (en) Multi-pattern wiring board
JP2007318034A (en) Multiple-formed wiring substrate, package for holding electronic component, and electronic device
JP2017174944A (en) Package for housing electronic component, electronic device and electronic module
JP4392138B2 (en) Multi-cavity ceramic wiring board manufacturing method
JP2017055056A (en) Package for mounting optical element and electronic device
JP2005340562A (en) Multiple patterning substrate
JP4550525B2 (en) Multiple wiring board

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20110915

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20121115

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20121211

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20130108

R150 Certificate of patent or registration of utility model

Ref document number: 5178595

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

LAPS Cancellation because of no payment of annual fees