JP2010212640A - Integrated circuit, and device and method for supporting the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an integrated circuit with a power saving isolation cell inserted therein. <P>SOLUTION: This integrated circuit includes: a plurality of electronic circuits formed on a semiconductor chip; a power circuit for supplying power to the respective electronic circuits; and a plurality of selection circuits for which one-side inputs are connected to the power circuit, the other-side inputs are connected to the other electronic circuits, and outputs are connected to the respective electronic circuits; wherein the selection circuit executes, by control from a control part, either of selective control to supply power to the electronic circuit and selective control to input a signal of the other electronic circuit. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an integrated circuit, an integrated circuit support device, and an integrated circuit manufacturing method.

  In recent years, semiconductor integrated circuit devices have become large-scale and highly integrated, and circuit operations have become complicated. Further, as the process of the semiconductor integrated circuit device is miniaturized, the leakage current in the transistor increases, and it is a big problem that the leakage current consumes extra power even when the semiconductor integrated circuit is not operating. ing.

  For this reason, in each functional circuit block level composed of a plurality of related functional circuits formed in the semiconductor integrated circuit device, the power is supplied or cut off, and the functional circuit block that is not used is used. A power gating (power cutoff) technique for suppressing power consumption due to leakage current is disclosed.

  For example, a semiconductor integrated circuit device that reduces power consumption due to leakage current by collectively supplying power to and shutting off power supply to a functional circuit block in which functional circuits such as a logic circuit and a memory circuit are integrated, and a driving method thereof A technique relating to (power supply method) is disclosed (for example, Patent Document 1).

  With such a driving method, power consumption to a circuit that is not used in the semiconductor integrated circuit device can be cut off for each functional circuit block, so that excessive power consumption due to leakage current can be suppressed.

  Specifically, a conventional power gating (power cutoff) technique will be described with reference to FIG. FIG. 1 shows a configuration of an integrated circuit having a power domain capable of shutting off power.

  As shown in the figure, this circuit has a power supply domain A211 that can be turned off, and inputs the output signal 1 and the output signal 2 from the power supply domain A211 to the isolation cell 212, respectively. . In this example, an AND circuit is used as an example of the isolation cell 212, but an isolation cell such as an OR circuit may be used.

  The isolation cell 212 is supplied with power from a power domain B (not shown) different from the power domain A 211. In this state, when the power supply domain A211 shuts off the power supply, the output signal 1 and the output signal 2 from the power supply domain A are in a Hi-Z (high impedance) state. Since the isolation cell 212 is not broken by the through current even in the Hi-Z state, the Hi-Z state can be cut off by providing the isolation cell 212, and the subsequent stage of the isolation cell 212. In the logic circuit 213, gate breakdown due to cell through current can be prevented.

  The isolation cell 212 is controlled by the power management unit 214. Specifically, when the power domain A211 is shut off, the power management unit 214 outputs an L state isolation enable signal iso-enb, and the isolation cell 212 shuts off the Hi-Z state. Then, the output from the isolation cell 212 is set to the L state. In this example, the case of low active has been described, but control is also possible in the case of high active. In this case, the isolation cell 212 is not an AND circuit but an OR circuit. The isolation enable signal iso-enb is generated in the power management unit 214, which is a power cutoff control block, and is input to each isolation cell 212.

  By the way, in the configuration of the integrated circuit as shown in FIG. 1, due to the insertion of the isolation cell, the congestion of the wiring increases due to the deterioration of the timing of the inserted path and the increase in the number of wirings. The area (area) occupied by etc. expands, and the power consumption increases.

  The present invention has been made in view of the above, and provides an integrated circuit, an integrated circuit support device, and an integrated circuit manufacturing method in which an isolation cell capable of saving power in a small area is inserted in a power gating technique. To do.

  The present invention provides a plurality of electronic circuits formed on a semiconductor chip, a power supply circuit that supplies power to each electronic circuit, one input connected to the power supply circuit, and the other input connected to the other A plurality of selection circuits connected to the electronic circuit and having an output connected to each of the electronic circuits, and the selection circuit supplies power to the electronic circuit under the control of a control unit Or a signal input from the other electronic circuit is selected.

  Further, according to the present invention, the selection circuit includes one OR circuit and two AND circuits, the input of one AND circuit is connected to the power supply circuit, and the input of the other AND circuit is the above-mentioned The output of the two AND circuits is connected to the input of the OR circuit, and the output of the OR circuit becomes the output of the selection circuit. .

  In the present invention, one logic circuit corresponding to the control unit is provided, and the logic circuit is an AND circuit or an OR circuit, and an output from the control unit is input to the logic circuit. And the output of the logic circuit is input to the selection circuit to perform the selection control.

  Further, the present invention provides a plurality of electronic circuits formed on a semiconductor chip, a power supply circuit that supplies power to each of the electronic circuits, one input is connected to the power supply circuit, and the other input is A plurality of scan register circuits that are connected to other electronic circuits and whose outputs are connected to each of the electronic circuits, and the scan register circuits are connected to the electronic circuits under the control of a control unit. In contrast, it is characterized by controlling whether or not to supply power and controlling execution of a scan test by the scan register circuit.

  In the present invention, the scan register circuit includes one shift register, one OR circuit, and two AND circuits, and an input of one AND circuit is connected to the power supply circuit, and the other A signal for performing the scan test is input to the input of the AND circuit, the outputs of the two AND circuits are connected to the inputs of the OR circuit, respectively, and the output of the OR circuit is subjected to the scan test. It is input to the shift register for performing.

  In the present invention, two logic circuits corresponding to the control unit are provided, the logic circuit is an AND circuit or an OR circuit, and an output from the control unit is one of the logic circuits. The output of the one logic circuit is input to the other logic circuit of the logic circuits, and the output of the other logic circuit is input to the selection circuit and is input from the control unit. It is characterized by controlling.

  Also, the present invention combines an RTL circuit or netlist that requires an isolation cell, reading means for reading constraints of an integrated circuit and a cell library, and a logic circuit that is a part of the isolation cell and a selection circuit. Circuit synthesis means for synthesizing a circuit to be inserted, circuit insertion means for inserting a logic circuit for performing selection control between the isolation cell and a part of logic circuits of the selection circuit, and the isolation cell. And an optimization means for optimizing timing, area and power consumption in the integrated circuit, and a netlist output means for outputting a netlist obtained by the circuit synthesis means, the circuit insertion means and the optimization means; It is characterized by having.

  Further, the present invention constructs a netlist that requires an isolation cell or a scan-inserted netlist, integrated circuit constraints and reading means for reading a cell library, and a scan register circuit including the isolation cell, Circuit construction means for forming a scan path, circuit insertion means for inserting a logic circuit for controlling the isolation cell and the scan register circuit, and the integrated circuit including the isolation cell Optimization means for optimizing the timing, area, and power consumption, and net list output means for outputting the circuit insertion means, the circuit insertion means and the net list obtained by the optimization means. It is characterized by.

  In addition, the present invention combines an RTL circuit or netlist that requires an isolation cell, a read process for reading constraints of an integrated circuit and a cell library, and a logic circuit that is a part of the isolation cell and a selection circuit. A circuit synthesis step of synthesizing a circuit to be inserted, a circuit insertion step of inserting a logic circuit for performing selection control of the isolation cell and a part of the logic circuit of the selection circuit, and the isolation cell. An optimization process for optimizing timing, area, and power consumption in the integrated circuit; and a netlist output process for outputting the netlist obtained by the circuit synthesis process, the circuit insertion process, and the optimization process; It is characterized by having.

  In addition, the present invention constructs a read process for reading a netlist that requires an isolation cell or a scan-inserted netlist, integrated circuit constraints and a cell library, and a scan register circuit including the isolation cell, A circuit construction process for forming a scan path; a circuit insertion process for inserting a logic circuit for controlling the isolation cell and the scan register circuit; and the integrated circuit including the isolation cell. And an optimization process for optimizing timing, area, and power consumption, and a netlist output process for outputting the circuit insertion process, the circuit insertion process, and a netlist obtained by the optimization process. It is characterized by.

  According to the present invention, it is possible to provide an integrated circuit, an integrated circuit support device, and an integrated circuit manufacturing method in which an isolation cell capable of saving power in a small area is inserted in the power gating technique.

Configuration diagram of an integrated circuit with a conventional isolation cell inserted Configuration diagram of an integrated circuit with a conventional isolation cell with a selection circuit inserted 1 is a configuration diagram of an integrated circuit provided with a selection circuit according to a first embodiment. Configuration diagram of an integrated circuit with a conventional isolation cell provided with a scan register circuit Configuration diagram of an integrated circuit provided with a scan register circuit according to a second embodiment The block diagram of the integrated circuit assistance apparatus which concerns on 3rd Embodiment Configuration diagram of integrated circuit support device according to the fourth embodiment

  The form for implementing this invention is demonstrated below.

[First Embodiment]
A first embodiment will be described. First, an integrated circuit having a configuration in which a conventional isolation cell is inserted and a selection circuit is provided will be described with reference to FIG. FIG. 2A is an overall configuration diagram of an integrated circuit having a configuration in which a conventional isolation cell is inserted and a selection circuit is provided, and FIG. 2B is a configuration diagram of the selection circuit.

  As shown in the figure, this circuit has a power supply domain A11 which is a power supply circuit and can be turned off. An output signal 1 and an output signal 2 from the power supply domain A11 are input to the isolation cell 12. Yes.

  The isolation cell 12 is supplied with power from a power domain B (not shown) different from the power domain A11. That is, the isolation cell 12, the selection circuit 13, the logic circuit 14 and the logic circuit 15 that are electronic circuits, and the power management unit 16 are in the power domain region of the power domain B.

  The isolation cell 12 is controlled by the power management unit 16, and when the power domain A11 is shut off, the power management unit 16 outputs an isolation enable signal iso-enb in the L state. In the isolation cell 12, the Hi-Z state is cut off regardless of the state, and the output from the isolation cell 12 is set to the L state.

  The output from the isolation cell 12 is input to the B port of the selection circuit 13. A signal from the logic circuit 14 is input to the A port of the selection circuit 13, and the signal input to the selection circuit 13 is selected and output by the select signal SEL. The signal output from the selection circuit 13 is input to the logic circuit 15.

  The isolation cell 12 is controlled by the power management unit 16. When the power domain A11 is shut off, the isolation enable signal iso-enb is output in the L state from the power management unit 16, and the Hi-Z state is shut off in the isolation cell 12, so that the isolation cell The output from 12 is set to the L state.

  The selection circuit 13 includes one OR circuit and two AND circuits. As shown in the figure, the signal from the logic circuit 14 is input to one AND circuit 21 via the A port of the selection circuit 13, and the output signal from the isolation cell 12 is input via the B port of the selection circuit 13. The other AND circuit 22 is input. The select signal SEL is input after being inverted to one AND circuit 21 and input to the other AND circuit 22 as it is. Further, the output of one AND circuit 21 and the output of the other AND circuit 22 are respectively input to the OR circuit 23, and the output of the OR circuit 23 becomes the output of the selection circuit 13 and is input to the logic circuit 15.

  In such a circuit configuration, a part of the isolation cell 12 and the selection circuit 13 overlap, resulting in a redundant circuit configuration.

  Next, a configuration of an integrated circuit in which an isolation cell according to the present embodiment is inserted and a selection circuit is provided will be described with reference to FIG.

  As shown in the figure, this integrated circuit has a configuration in which an AND circuit serving as an isolation cell 42 is provided inside a selection circuit 33, and has a power supply domain A31 that can be turned off as a power supply circuit. The output signal 1 and the output signal 2 from the power domain A31 are input to the isolation cell 42 in the selection circuit 33.

  Further, the selection circuit 33 including the isolation cell 42, the AND circuit 32, the logic circuit 34 which is an electronic circuit, the logic circuit 35, and the power management unit 36 are provided in a power supply domain B (not shown) different from the power supply domain A31. In the power domain area.

  The selection circuit 33 is configured by one OR circuit and two AND circuits. As shown in the figure, the signal from the logic circuit 34 is input to one AND circuit 41 in the selection circuit 33, and the output signal 1 and the output signal 2 from the power supply domain A 31 are input to the other AND circuit in the selection circuit 33. It is input to an isolation cell 42 which is a circuit. Further, the output from the AND circuit 32 is inputted after being inverted to one AND circuit 41 and inputted as it is to the isolation cell 42 which is the other AND circuit. The output of one AND circuit 41 and the output of the isolation cell 42, which is the other AND circuit, are respectively input to the OR circuit 43. The output of the OR circuit 43 becomes the output of the selection circuit 33, and the logic circuit 35 To enter.

  The isolation cell 42 in the selection circuit 33 is controlled by the power management unit 36 through one AND circuit 32 which is a logic circuit. An output signal from the power management unit 36 is input to one side of the AND circuit 32, and a select signal SEL is input to the other side.

  When the power domain A31 is shut off, the L-state isolation enable signal iso-enb output from the power management unit 36 is input to the AND circuit 32, and the L-state select signal SEL is input to the AND circuit 32. As a result, the output from the AND circuit 32 becomes the L state, and this output is input to the isolation cell 42.

  A signal from the logic circuit 34 is input to the selection circuit 33, and a signal from the logic circuit 34 and an output signal from the power supply domain 31 are based on the signal of the AND circuit 32 input to the selection circuit 33. 1 and the output signal 2 are selected and output and input to the logic circuit 35.

  That is, in the integrated circuit according to the present embodiment, the AND circuit 32 outputs an AND logic of the select signal SEL and the isolation enable signal iso-enb from the power management unit 36. When the isolation enable signal iso-enb is in the L state, the isolation cell 42 performs the isolation operation and blocks the Hi-Z state from the power domain A31. At this time, the selection circuit 33 selects a signal from the logic circuit 34. On the other hand, when the isolation enable signal iso-enb is in the H state, the isolation cell 42 functions as normal AND logic and performs a logic operation in the selection circuit 34.

  In the integrated circuit according to the present embodiment, when there are a plurality of selection circuits 33 in the integrated circuit, the control from the power management unit 36 can be performed via one AND circuit 32, and the number of gates increases. The increase in the number of wirings can be suppressed as much as possible.

[Second Embodiment]
Next, a first embodiment will be described. First, an integrated circuit having a configuration provided with a scan register circuit will be described with reference to FIG. 4 in which a conventional isolation cell is inserted. FIG. 4A is an overall configuration diagram of an integrated circuit in which a conventional isolation cell is inserted and a scan register circuit is provided, and FIG. 4B is a configuration diagram of the scan register circuit.

  As shown in the figure, this circuit has a power supply domain A51 that is a power supply circuit and can be turned off, and an output signal 1 and an output signal 2 from the power supply domain A51 are input to an isolation cell 52. .

  The isolation cell 52 is supplied with power from a power domain B (not shown) different from the power domain A51. That is, the isolation cell 52, the scan register circuit 53 and the scan register circuit 54, the logic circuit 55 that is an electronic circuit, and the power management unit 56 are in the power domain region of the power domain B.

  The isolation cell 52 is controlled by the power management unit 56. When the power domain A51 is shut off, the power management unit 56 outputs an L state isolation enable signal iso-enb, In the isolation cell 52, the Hi-Z state is cut off, and the output from the isolation cell 52 is set to the L state.

  The output from the isolation cell 52 is input to the D ports of the scan register circuits 53 and 54. The scan enable signal SCANEN for starting the scan test is input to the SE ports in the scan register circuits 53 and 54. The scan data input signal SCANIN is input to the SI port of the scan register circuit 53, and the output from the Q port of the scan register circuit 53 is input to the logic circuit 55 and also input to the SI port of the scan register circuit 54. is doing. Further, an output from the Q port of the scan register circuit 54 is input to the logic circuit 55 and is output as an output signal SCANOUT of the scan data.

  The scan register circuits 53 and 54 are configured by one OR circuit, two AND circuits, and one flip-flop. As shown in the figure, the output signal from the isolation cell 52 is input to one AND circuit 61 from the D port of the scan register circuits 53 and 54 and is input to the SI port of the scan register circuits 53 and 54. Signals and the like are input to the other AND circuit 62. Further, the scan enable signal SCANEN is inputted after being inverted to one AND circuit 61 via the SE port, and inputted to the other AND circuit 62 as it is. The output of one AND circuit 61 and the output of the other AND circuit 62 are each input to an OR circuit 63, and the output of the OR circuit 63 is input to a flip-flop 64. The output of the flip-flop 64 becomes the output of the Q port of the scan register circuits 53 and 54. A clock signal CK is input to each flip-flop 64 in the scan register circuits 53 and 54.

  In such a circuit configuration, the isolation cell 52 and a part of the scan register circuits 53 and 54 overlap, resulting in a redundant circuit configuration.

  Next, a configuration of an integrated circuit in which an isolation cell according to the present embodiment is inserted and a scan register circuit is provided will be described with reference to FIG.

  As shown in the figure, this integrated circuit has an AND circuit that becomes an isolation cell 82a inside the scan register circuit 74 and an AND circuit that becomes an isolation cell 82b inside the scan register circuit 75. A power supply domain A71 which is a power supply circuit and can be shut off. The output signal 1 and the output signal 2 from the power supply domain A71 are input to the isolation cell 82 in the scan register circuits 74 and 75.

  Further, scan register circuits 74 and 75 including isolation cells 82a and 82b, an OR circuit 72, an AND circuit 73, a logic circuit 76 which is an electronic circuit, and a power management unit 77 are different from the power domain A71. Is in the power domain region of the power domain B.

  The scan register circuits 74 and 75 are configured by one OR circuit, two AND circuits, and one flip-flop. As shown in the figure, a scan data input signal SCANIN is input to one AND circuit 81 a in the scan register circuit 74, and one AND circuit 81 b in the scan register circuit 75 is input from the scan register circuit 74. The output signal is being input. Further, the output signal 1 and the output signal 2 from the power domain A 71 are input to the isolation cells 82 a and 82 b which are the other AND circuits in the scan register circuits 74 and 75.

  On the other hand, an output signal from an AND circuit 73 to be described later is input after being inverted to one of the AND circuits 81a and 81b and input to the isolation cells 82a and 82b which are the other AND circuits as they are. The output of one AND circuit 81a and the output of the isolation cell 82a which is the other AND circuit are input to the OR circuit 83a, and the output of one AND circuit 81b and the isolation which is the other AND circuit are input. The output of the cell 82b is input to the OR circuit 83b. The output of the OR circuit 83a is input to the D port of the flip-flop 84a, and the output of the OR circuit 83b is input to the D port of the flip-flop 84b. The outputs from the Q ports of the flip-flops 84a and 84b become the outputs of the scan register circuits 74 and 75. The clock signal CK is input to the flip-flops 84a and 84b in the scan register circuits 74 and 75, respectively.

  The control of the isolation cells 82a and 82b in the scan register circuits 74 and 75 is performed by the power management unit 77 through an OR circuit 72 and an AND circuit 73 which are two logic circuits.

  When the power domain A 71 is shut off, the power management unit 77 outputs the isolation enable signal iso-enb in the L state and inputs it to the OR circuit 72. Also, an enable signal ATPGEN for determining whether or not to perform a scan test is input to the OR circuit 72, and an output from the OR circuit 72 is input to the AND circuit 73. Further, the scan enable signal SCANEN, which is an enable signal for determining whether or not to pass scan data, is inverted and input to the AND circuit 73. The output signal from the AND circuit 73 is input to the isolation cells 82a and 82b in the scan register circuits 74 and 75, whereby the isolation cells 82a and 82b are controlled.

  That is, the OR circuit 72 outputs an OR logic of the isolation enable signal iso-enb output from the power management unit 77 and ATPGEN, and the AND circuit 73 An output of AND logic of the output and the inverted signal of the scan path circuit enable signal SCANEN is output.

  Therefore, in the normal operation (ATPGEN is in the L state) and the isolation enable signal iso-enb is in the L state, the output of the AND circuit 73 is in the L state, and the isolation cells 82a and 82b perform the isolation operation. To shut off the Hi-Z state from the power supply domain A71. At this time, the scan register circuits 74 and 75 select the scan data input signal SCANIN and the output signal from the scan register circuit 74.

  In the case of normal operation (ATPGEN is in L state) and the isolation enable signal iso-enb is in the H state, the isolation cells 82a and 82b function as normal AND logic and operate as a scan register circuit. I do.

  In the OR circuit 72, the OR logic of ATPGEN and the isolation enable signal iso-enb is taken, and in the case of a scan test (when ATPGEN is in the H state), the power domain A71 remains in the ON state (the power supply is not shut off). ) Can be tested.

  The outputs of the flip-flops 84a and 84b are input to the logic circuit 76 as outputs of the scan register circuits 74 and 75.

  In the integrated circuit according to the present embodiment, when there are a plurality of scan register circuits 74 and 75 in the integrated circuit, the control from the power management unit 77 is controlled by two logic circuits, that is, one OR circuit 72 and 1. Since it can be performed via the two AND circuits 73, an increase in the number of gates and an increase in the number of wirings can be suppressed as much as possible.

[Third Embodiment]
Next, a third embodiment will be described. The present embodiment is an integrated circuit support device and an integrated circuit manufacturing method for manufacturing the integrated circuit of the first embodiment.

  This embodiment will be described with reference to FIG. FIG. 6 is a block diagram of the integrated circuit support apparatus according to the present embodiment. Each means constituting the integrated circuit support apparatus according to the present embodiment is preferably realized by mounting an appropriate program on an appropriate computer, and the integrated circuit support apparatus according to the present embodiment is also implemented. It is preferable that data used or generated by each of the constituent means is stored in various memories and storage media associated with the computer.

  The integrated circuit support apparatus according to the present embodiment reads the net list 111, the optimization constraint 112, the cell library 113, the multi-power supply design constraint 114, and the like by the reading unit 115.

  The netlist 111 is an isolation cell, an RTL (Register Transfer Level) circuit that requires isolation theory, or a netlist. Further, the optimization constraint 112 means constraints on the integrated circuit such as constraints and timing of logic synthesis, areas of logic circuits and logic circuits. The cell library 113 is a library of a plurality of cells, and a suitable cell is selected from these. The multi-power supply design constraint 114 includes a power format, and is a constraint on an integrated circuit that is restricted by association between a power supply circuit and a logic circuit.

  Next, an isolation cell or a circuit that combines logic and logic other than the purpose of isolation is synthesized by circuit synthesis means 116 that synthesizes a circuit that combines the isolation cell and a part of the logic circuit of the selection circuit. . Specifically, the isolation cell 42 in FIG. 3 which is a circuit that combines the isolation cell and a part of the logic circuit of the selection circuit is synthesized.

  Next, the circuit insertion means 117 for inserting a logic circuit for controlling the isolation cell and a part of the logic circuit of the selection circuit controls the isolation logic operation and the logic operation other than the isolation purpose. Insert. Specifically, the AND circuit 32 in FIG. 3 which is a logic circuit for controlling the isolation cell and a part of the logic circuits of the selection circuit is inserted. At this time, the specifications of the isolation cell or logic output value are described in the multi-power supply design constraint 114 (power format such as CPF or UPF).

  Next, the optimization means 118 for optimizing the timing, area and power consumption in the integrated circuit including the isolation cell optimizes the timing, area and power consumption in the integrated circuit including the isolation cell. I do. Specifically, cell sizing, load balancing, and the like are performed.

  Next, the net list output means 119 for outputting the net list obtained by the circuit synthesizing means, the circuit inserting means and the optimizing means, the net list designed by the integrated circuit support device, that is, the circuit synthesizing means 116, the circuit insertion. The net list obtained by the means 117 and the optimization means 118 is output.

  As a result, an optimized netlist 120 can be obtained by synthesizing the isolation cell or logic and the logic other than the isolation purpose.

  Thereby, the integrated circuit according to the first embodiment can be manufactured. Note that the order in which the circuit synthesis unit 116, the circuit insertion unit 117, and the optimization unit 118 are executed may be switched.

[Fourth Embodiment]
Next, a fourth embodiment will be described. The present embodiment is an integrated circuit support device and an integrated circuit manufacturing method for manufacturing the integrated circuit of the second embodiment.

  The present embodiment will be described with reference to FIG. FIG. 7 is a block diagram of the integrated circuit support device according to the present embodiment. Each means constituting the integrated circuit support apparatus according to the present embodiment is preferably realized by mounting an appropriate program on an appropriate computer, and the integrated circuit support apparatus according to the present embodiment is also implemented. It is preferable that data used or generated by each of the constituent means is stored in various memories and storage media associated with the computer.

  The integrated circuit support apparatus according to the present embodiment reads the scan inserted netlist 131, the optimization constraint 132, the cell library 133, the multi-power supply design constraint 134, and the like by the reading unit 135.

  The scan inserted netlist 131 is an isolation cell, a netlist that requires isolation theory, or a scan (SCAN) inserted netlist. Further, the optimization constraint 132 means constraints on the integrated circuit such as scanning. The cell library 133 is a library of a plurality of cells, and a suitable cell is selected from these. The multi-power supply design constraint 134 includes a power format, and is a constraint on an integrated circuit that is restricted by association between a power supply circuit and a logic circuit.

  Next, a scan register circuit including an isolation cell is constructed, and a scan register including an isolation cell or logic is constructed by a circuit construction unit 136 that forms a scan path, thereby forming a scan path. Specifically, the isolation cells 82a and 82b in FIG. 5 are formed.

  Next, a circuit for controlling the isolation logic operation, the logic operation other than the isolation purpose, and the scan test operation by the circuit insertion means 137 for inserting a logic circuit for controlling the isolation cell and the scan register circuit. Insert. Specifically, an OR circuit 72 and an AND circuit 73 shown in FIG. 5 which are logic circuits for controlling the isolation cell and the scan register circuit are inserted. At this time, the specification of the isolation cell or logic output value is described in the multi-power supply design constraint 134 (power format such as CPF or UPF).

  Next, the optimization means 138 for optimizing the timing, area and power consumption in the integrated circuit including the isolation cell optimizes the timing, area and power consumption in the integrated circuit including the isolation cell. To do. Specifically, cell sizing, load balancing, and the like are performed.

  Next, the net list output means 139 for outputting the net list obtained by the circuit insertion means, the circuit insertion means and the optimization means, and the net list after the scan insertion designed by the integrated circuit support device, that is, the circuit insertion means 136, the net list obtained by the circuit insertion means 137 and the optimization means 138 is output.

  Thereby, an optimized netlist 140 constituting a scan register scan path including isolation cells or logic can be obtained.

  Thereby, the integrated circuit according to the second embodiment can be manufactured. Note that the order of executing the circuit insertion unit 136, the circuit insertion unit 137, and the optimization unit 138 may be changed.

  In addition, although the form which concerns on implementation of this invention was demonstrated, the said content does not limit the content of invention.

31 Power Domain A
32 AND circuit 33 Selection circuit 34 Logic circuit 35 Logic circuit 36 Power management unit 41 AND circuit 42 Isolation cell (AND circuit)
43 OR circuit

JP 2003-132683 A JP 2007-13036 A

Claims (10)

A plurality of electronic circuits formed on a semiconductor chip;
A power supply circuit for supplying power to each of the electronic circuits;
One input is connected to the power supply circuit, the other input is connected to another electronic circuit, and a plurality of selection circuits whose outputs are connected to each of the electronic circuits,
Have
The selection circuit performs selection control of supplying power to the electronic circuit or inputting a signal of the other electronic circuit under the control of a control unit. . The selection circuit is composed of one OR circuit and two AND circuits,
The input of one AND circuit is connected to the power supply circuit, and the input of the other AND circuit is connected to the other electronic circuit,
The outputs of the two AND circuits are respectively connected to the inputs of the OR circuit,
The integrated circuit according to claim 1, wherein an output of the OR circuit is an output of the selection circuit. One logic circuit corresponding to the control unit is provided,
The logic circuit is an AND circuit or an OR circuit, and an output from the control unit is input to the logic circuit, and an output of the logic circuit is input to the selection circuit to perform the selection control. An integrated circuit according to claim 1 or 2. A plurality of electronic circuits formed on a semiconductor chip;
A power supply circuit for supplying power to each of the electronic circuits;
One input is connected to the power supply circuit, the other input is connected to another electronic circuit, a plurality of scan register circuits whose output is connected to each of the electronic circuits,
Have
The integrated circuit according to claim 1, wherein the scan register circuit controls whether or not power is supplied to the electronic circuit and control of execution of a scan test by the scan register circuit under the control of a control unit. The scan register circuit is composed of one shift register, one OR circuit, and two AND circuits,
An input of one AND circuit is connected to the power supply circuit, and a signal for performing the scan test is input to an input of the other AND circuit,
The outputs of the two AND circuits are respectively connected to the inputs of the OR circuit,
5. The integrated circuit according to claim 4, wherein the output of the OR circuit is input to a shift register for performing a scan test. Two logic circuits corresponding to the control unit are provided,
The logic circuit is an AND circuit or an OR circuit, and an output from the control unit is input to one of the logic circuits, and an output of the one logic circuit is the other of the logic circuits. 6. The integrated circuit according to claim 4, wherein an output of the other logic circuit is input to the selection circuit and is controlled by the control unit. RTL circuits or netlists that require isolation cells, integrated circuit constraints and reading means for reading cell libraries;
Circuit synthesizing means for synthesizing a circuit that combines the isolation cell and a part of the logic circuit of the selection circuit;
Circuit insertion means for inserting a logic circuit for performing selection control of the isolation cell and a part of the selection circuit;
Optimization means for optimizing timing, area, power consumption in the integrated circuit including the isolation cell;
Netlist output means for outputting a netlist obtained by the circuit synthesis means, the circuit insertion means and the optimization means;
An integrated circuit support device comprising: A netlist or scan-inserted netlist that requires an isolation cell, integrated circuit constraints and reading means for reading the cell library;
A circuit construction means for constructing a scan register circuit including the isolation cell and forming a scan path;
Circuit insertion means for inserting a logic circuit for controlling the isolation cell and the scan register circuit;
Optimization means for optimizing timing, area, power consumption in the integrated circuit including the isolation cell;
Net list output means for outputting the net list obtained by the circuit insertion means, the circuit insertion means and the optimization means;
An integrated circuit support device comprising: RTL circuits or netlists that require isolation cells, integrated circuit constraints and a reading process for reading the cell library;
A circuit synthesis step of synthesizing a circuit that combines the isolation cell and a part of the logic circuit of the selection circuit;
A circuit insertion step of inserting a logic circuit for performing selection control of the isolation cell and a part of the logic circuit of the selection circuit;
An optimization process for optimizing timing, area, power consumption in the integrated circuit including the isolation cell;
A netlist output step for outputting a netlist obtained by the circuit synthesis step, the circuit insertion step and the optimization step;
An integrated circuit manufacturing method comprising: A netlist or scan-inserted netlist that requires an isolation cell, integrated circuit constraints, and a loading process that reads the cell library;
A circuit construction process for constructing a scan register circuit including the isolation cell and forming a scan path;
A circuit insertion step of inserting a logic circuit for controlling the isolation cell and the scan register circuit;
An optimization process for optimizing timing, area, power consumption in the integrated circuit including the isolation cell;
A netlist output step for outputting a netlist obtained by the circuit insertion step, the circuit insertion step and the optimization step;
An integrated circuit manufacturing method comprising:

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