JP2010206931A - Method and device for control of three-level inverter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To miniaturize a device and reduce its cost by eliminating the need for a zero-phase reactor or reducing the necessity of the reactor by suppressing a common mode voltage. <P>SOLUTION: A control method of a three-level inverter includes a voltage command vector region discrimination means 10 which discriminates regions of tips of voltage command vectors, a voltage vector selection means 20 which surrounds the regions and selects three voltage vectors in which the maximum values of the common mode voltages become small, a calculation means 30 of a selected vector output time ratio which calculates an output time ratio of each voltage vector so that composite vectors of the three voltage vectors coincide with the voltage command vectors, a decision means 40 of a selected vector output order which determines the output order of the voltage vectors so that a switch state is not simultaneously changed in two or more phases when a certain voltage vector is transited to the other vector among three voltage vectors, a voltage vector output means 50 which outputs the three voltage vectors following the time ratio and the output order, and a decode means 60 which generates a drive signal of a semiconductor switch on the basis of the output. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a control method and a control device for a three-level inverter in which the output voltage of each phase of the inverter has three levels.

FIG. 4 is a circuit configuration diagram of a general three-level inverter (NPC (Neutral Point Clamped Inverter) inverter).
In FIG. _{4, B 1,} B ₂ is a DC power _supply, U A to _W-D are IGBT as a semiconductor _switch, D 1 to D ₆ are diodes, U, V, W are three-phase output terminal of the inverter, M is a three-phase load such as an AC motor, N is the neutral point of the stator winding, the N _P is a DC midpoint.

  The method for controlling the output voltage of the three-level inverter is described in, for example, Patent Document 1 and Non-Patent Document 1, and will be briefly described below.

FIG. 5 is an operation waveform diagram of the three-level inverter.
In FIG. 5, the uppermost waveform shows sinusoidal phase output voltage commands v _REFU , v _REFV , v _REFW and carrier triangular waves T _HIGH , T _LOW as modulation signals, and the output voltage command, carrier triangular wave, by comparing, for generating a driving signal of each IGBT U _a to _W-D that constitute the inverter. By switching each IGBT based on these drive signals, for example, U-phase output voltage v _U and U-V line voltage v _UV as shown in the figure are obtained.

Here, Table 1 summarizes the on / off conditions of each switch. In Table 1, IGBT _A is IGBT U _A in FIG. 4, _V A, the _{W A,} IGBT _B is also IGBT U _{B, V} B, the _{W B,} IGBT _C is also IGBT U _{C, V C,} W the _C, IGBT _D are also shown _{IGBT U D, V D, W} D , respectively.

In FIG. 4, for example, considering the U phase, the top IGBT U _A is turned on when the voltage command v _{REFU in} FIG. 5 is larger than the upper triangular wave T _HIGH , and turned off otherwise. The second IGBT U _B turns on when v _REFU is larger than the lower triangular wave T _LOW , and turns off otherwise. The third IGBT U _{C is, v REFU} is turned on when less than the upper triangular wave _{T HIGH,} otherwise off. The fourth UGBT U _D is turned on when v _REFU is smaller than the lower triangular wave T _LOW , and turned off otherwise.
The above operation is the same for the other V and W phases.

5 the second stage of the waveform at v _U A waveform observed voltage of the output U-phase, based on the DC midpoint N _P, 3-stage waveform v _UV is line voltage waveform across the output terminals UV addition, the waveform v _COM fourth stage is a waveform of the DC midpoint N _P voltage was observed neutral point N of the load M as a reference (the common mode voltage to be described later).
In particular, as can be seen from the waveform v _{U at} the second stage and the waveform v _{UV at} the third stage, the DC voltage is converted into a sinusoidal AC voltage for each phase by switching each IGBT based on the control method described above. And its size and frequency can be controlled.

JP-A-7-194133 (paragraphs [0002] to [0018], FIGS. 8 to 11 etc.)

General electrical magazine OHM November issue separate volume, "Power Electronics Guidebook", p. 45-46, Ohmsha, published on November 15, 1996

Now, it is known that a power converter that adjusts an output voltage by turning on and off a semiconductor switch generates a common mode voltage that induces a malfunction of another device with switching.
3-level inverter according to the present invention is no exception, the common mode voltage v _COM is a voltage obtained by observing the neutral point N of the load M based on the DC midpoint N _P in FIG. 4 is calculated by the following formula 1 be able to.

[Equation 1]
v _COM = (v _u + v _v + v _w ) / 3

For example, in FIG. 4, when the U phase outputs E _d / 2 and the V phase and W phase output 0, that is, IGBT U _A , IGBT U _B , IGBT V _B , IGBT V _C , IGBT Considering the case where W _B and IGBT W _C are turned on and the other switches are turned off, the common mode voltage v _COM can be calculated by Equation 2.

[Equation 2]
v _COM = (E _d / 2 + 0 + 0) / 3 = E _d / 6

The waveform of the common mode voltage v _COM is shown in the fourth stage from the top in FIG. As described above, in the power converter, a common mode voltage is generated in principle, and this common mode voltage causes a high frequency common mode current to flow to the ground via the stray capacitance of the load, which is another noise. Inflowing into the device induces malfunction of other devices.
In order to solve the above problem, conventionally, countermeasures such as installing a zero-phase reactor effective for suppressing the high-frequency component of the common mode current on the output side of the power converter have been taken. This has hindered volume reduction and cost reduction of the apparatus.

  Accordingly, the problem to be solved by the present invention is that the common mode voltage is suppressed to eliminate the need for the zero-phase reactor, or the inductance value of the zero-phase reactor can be reduced to reduce the size and cost of the device. An object of the present invention is to provide an inverter control method and control apparatus.

In order to solve the above-mentioned problem, a control method for a three-level inverter according to claim 1 is to turn on and off a semiconductor switch of each phase of a three-phase inverter connected to a DC power source to start DC high voltage, medium voltage, low In a three-level inverter that outputs DC voltages at three levels of voltage at a predetermined time ratio, and outputs a three-phase AC voltage according to a three-phase AC voltage command,
As the switch state of each phase of the semiconductor switch, a state in which a DC high voltage, medium voltage, or low voltage is output is expressed as 1, 0, −1, respectively. While expressing the phase output voltage as an output voltage vector,
The distance is close to the voltage command vector obtained by converting the three-phase AC voltage command of the inverter to two-phase AC, and the absolute value of the result of adding the switch states of each phase for three phases is 1 or less. Select three such output voltage vectors such that
When transitioning from one output voltage vector to another, among the three selected output voltage vectors, the output voltage vector is transitioned and selected so that the switch state does not change simultaneously in two or more phases. The time ratio of each output voltage vector is adjusted so that the combined vector of the three output voltage vectors matches the voltage command vector.

The control device according to claim 2 turns on and off the semiconductor switch of each phase of the three-phase inverter connected to the DC power source to supply DC high voltage, medium voltage, and low voltage DC voltage from each phase to a predetermined level. In a three-level inverter that outputs each at a time ratio and outputs a three-phase AC voltage according to the three-phase AC voltage command,
As the switch state of each phase of the semiconductor switch, a state in which a DC high voltage, medium voltage, or low voltage is output is expressed as 1, 0, −1, respectively. When the phase output voltage is expressed as an output voltage vector,
Voltage command vector region discriminating means for discriminating a region where the tip of the voltage command vector obtained by converting the three-phase AC voltage command of the inverter into a two-phase AC coordinate is located;
Voltage vector selection means for selecting three of the output voltage vectors that are vectors surrounding the region, and whose absolute value as a result of adding the switch states of each phase for three phases is 1 or less;
Selection vector output time ratio calculation means for calculating a time ratio for outputting each output voltage vector so that a combined vector of the three output voltage vectors selected by the selection means matches the voltage command vector;
A selection vector output that determines the output order of the output voltage vectors so that the switch state does not change simultaneously in two or more phases when transitioning from one output voltage vector to another output voltage vector among the three output voltage vectors Order determination means;
Voltage vector output means for outputting the three output voltage vectors according to the time ratio and output order;
Decoding means for generating a drive signal for the semiconductor switch based on the output of the output means.

  According to the present invention, the semiconductor switch can be controlled so that the average value of the output voltage within the control period becomes equal to the voltage command without increasing the number of switching more than necessary, and at the same time, the maximum value of the common mode voltage. Can be suppressed. As a result, it is possible to suppress the occurrence of common mode noise and eliminate the need for a zero-phase reactor for suppressing common-mode high-frequency current, or to reduce the inductance value even if a zero-phase reactor is used. it can. Therefore, the control device can be reduced in size and cost.

It is a functional block diagram which shows embodiment of this invention. It is the space vector figure which showed the voltage vector and switch state in embodiment of this invention, and the transition path | route of a voltage vector. It is an example of a waveform at the time of operating a 3 level inverter by the embodiment of the present invention. It is a circuit block diagram of a 3 level inverter. It is an operation | movement waveform diagram of a 3 level inverter. It is the space vector figure which expressed the output voltage of the 3 level inverter as a vector according to the switch state.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
First, FIG. 6 is a space vector diagram in which the three-phase output voltage of the three-level inverter is vector-represented according to the on / off state of the switch on the α-β axis coordinates obtained by converting the three-phase alternating current into the two-phase alternating current. In the present embodiment, the three-level inverter is controlled based on this space vector diagram.
Hereinafter, a description will be given with reference to FIG.

In FIG. 6, the α axis and the β axis normalize the phase voltage instantaneous value with 2E _d / 3 (E _d is the DC voltage of the three-level inverter) (1.0 in FIG. 6 corresponds to 2E _d / 3). To do). In the figure, v ₁ to v ₁₈ are names of voltage vectors that can be output by the three-level inverter, and there are 18 types in total. These voltage vectors _v 1 _{to v 18} are are arranged a code _v 1 _{to v 18} the origin of the alpha-beta-axis coordinate at the tip position of each voltage vector as a base point.

Further, (u, v, w) (where u, v, w are values of 1 or 0 or −1, respectively) described under the voltage vectors v _{1 to} v ₁₈ are U, 3 of the three-level inverter. It shows the state of the switch of each phase of V and W. For the circuit configuration shown in FIG. 4, for example U-phase, IGBT U _A, if the output _E d / 2 by IGBT U _B is turned on, the "u" in the (u, v, w) Expressed as “1”. If 0 is output when the IGBT U _B and the IGBT U _C are turned on, “u” in (u, v, w) is expressed as “0”. Further, IGBT U _C, if the output _-E d / 2 by IGBT U _D is turned on, is expressed as "-1" and "u" in the (u, v, w).
There may be a plurality of such switch states depending on the types of the voltage vectors v _{1 to} v ₁₈ .

Considering the state in which the 3-level inverter outputs 0 to the U and V phases and −E _d / 2 to the W phase, the voltage vector at this time is v ₂ , and in the switch state Considering (0, 0, -1).
On the other hand, the region where the tip of the voltage vector that can be output by the three-level inverter is located can be divided into S _{1 to} S ₂₄ based on the position of the voltage vectors v _{1 to} v ₁₈ .

First, in the present embodiment, for the purpose of reducing the maximum value of the common mode voltage, a prohibited state is provided as a switch state.
For example, in the case of the voltage vector v2, as shown in FIG. 4, there are _two possible switch states: (0, 0, −1) and (1, 1, 0).
Here, when the switch state is (1, 1, 0), when the direct-current voltage is E _d , the common mode voltage is v _COM = (E _d / 2 + E _d / 2 + 0) / 3 = E _d / 3. On the other hand, the common mode voltage in the case of (0, 0, −1) is v _COM = (0 + 0−E _d / 2) / 3 = −E _d / 6. Selecting (0, 0, -1) can reduce the common mode voltage.

  For this reason, in this embodiment, only the switch state in which the absolute value of the result obtained by adding the switch states of each phase for three phases is at least 1 or less is permitted, and the other switch states are prohibited.

A specific control method will be described based on the above prohibition conditions.
As an example, the case where the tip of the voltage command vector v _REF obtained by converting the three-phase AC voltage command into the two-phase AC, that is, (v _REFα , v _REFβ ) is in the region S ₉ will be described.
First, three voltage vectors to be output by the three-level inverter are selected. Since the tip of the voltage command vector v _REF are located in the region S _9, for the purpose of reducing the high-order high frequency components due to the switching, in order to select the vector close to the voltage command vector v _REF, the area S ₉ 6 Consider that enclosing vectors v ₂ , v ₈ , and v ₉ are selected and these vectors v ₂ , v ₈ , and v ₉ are divided in time and output.

Next, a time ratio D for outputting the selected vectors v ₂ , v ₈ , v ₉ during a certain control period T is calculated. That is, the time ratio of outputting each vector v ₂ , v ₈ , v ₉ is adjusted, and the resultant vector only _needs to match the voltage command vector v _REF , so that the vector v ₂ is (v _2α , v _2β ), The vector v ₈ is (v _8α , v _8β ), the vector v ₉ is (v _9α , v _9β ), and the time ratios for outputting the vectors v ₂ , v ₈ , v ₉ within a certain time are D ₂ , Assuming D ₈ and D ₉ , the following Equation 3 may be established.

  From Equation 3, Equation 4 is derived.

Next, for the purpose of reducing the switching loss, the order in which the voltage vectors are output is determined so that the switch states of at least two phases do not change simultaneously. For example, in the above example, considering transition from the vector v ₂ to another voltage vector, transition to either the vector v ₈ or v ₉ can be considered.
Here, the switch state realizing the vector v ₂ is (0, 0, −1) for the purpose of reducing the common mode voltage, and the switch state of the vector v ₉ is (1, 1, −1). , switch state vector _{v 8} is (1, 0, -1).

Now, when a transition is made from the vector v ₂ to the vector v ₉ , the switch state changes from “0” to “1” in the U phase and the V phase, which is a switching loss in the two phases of the U phase and the V phase. Means that
On the other hand, when the vector v ₂ changes to the vector v ₈ , only the U phase changes from “0” to “1”, which means that switching loss occurs only in the U phase.

Therefore, in this example, it is determined that the vector to be transferred next to the vector v ₂ is the vector v ₈ which is advantageous in terms of switching loss. Incidentally, after outputting the vector v _8, may output the remaining vector v ₉ which has not yet been output among the three vectors. At the time of transition from the vector v ₈ to the vector v ₉ , only the V phase changes from “0” to “1”, so that a switching loss occurs only in the V phase.

To summarize the above, during a certain control period T, the vector _{v 2} → _{v 8} → _v in the order of _9, the time ratio _D 2 previously _calculated, D 8, each at _{D 9} vector _v 2, _{v 8} , V ₉ may be output.
The selection also in the next control cycle, but may be repeated that similar to the control described above, since the end of the voltage vector outputted in the control cycle is v _9, the first v ₂ in the next control cycle Then, a transition of v ₉ → v ₂ occurs, and switching loss occurs in two phases of the U phase and the V phase. Therefore, for the purpose of reducing the switching loss, in the next control cycle, output is performed in the order of v ₉ → v ₈ → v ₂ , contrary to the current control cycle. That is, it is necessary to determine the order in which vectors are generated according to the vector output at the end of the previous control cycle.

FIG. 3 shows a waveform example when the three-level inverter is operated according to the present embodiment.
According to this embodiment, it is possible to control the average value of the output voltage within the control cycle T to be equal to the voltage command without increasing the number of switching more than necessary. Further, as shown in the figure, since the absolute value of the maximum value of the common mode voltage is suppressed to E _d / 6, the generation of common mode noise is prevented, and a zero-phase reactor for suppressing the common mode high frequency current is unnecessary, Alternatively, the inductance value can be reduced.

FIG. 2 is a space vector diagram showing voltage vectors, switch states, and voltage vector transitionable paths in the present embodiment. When there are a plurality of switch states that realize one voltage vector, the prohibited switch state is expressed by a strikethrough.
In FIG. 2, vector transition paths in which simultaneous switching of two or more phases does not occur are connected by bold lines, and the other paths are connected by thin lines. For example, in the above-described example, switching loss occurs in two phases due to the transition between the vector v ₂ and the vector v _9, and therefore, the vectors v ₂ and v ₉ are connected by a thin line.

Next, FIG. 1 is a functional block diagram of the control device according to the present embodiment. This functional block is realized by hardware and a program such as an arithmetic processing unit for generating a gate signal for the IGBTs U _{A to} W _D of the three-level inverter shown in FIG.

In FIG. 1, the voltage command vector region discriminating means 10 discriminates in which of the space vector regions S _{1 to} S ₂₄ the tip of the voltage command vector v _REF, that is, (v _REFα , v _REFβ ) is located. And output.
The voltage vector selection unit 20 selects three voltage vectors close to the region determined by the determination unit 10 (voltage vectors surrounding the region) from v ₁ to v ₁₈ . At that time, in order to reduce the maximum value of the common mode voltage, as described above, for example, if the voltage vector _{v 2,} switch state (1,1,0) is prohibited, (0,0, -1) is selected Is done.

The selection vector output time ratio calculation means 30 calculates time ratios D _{1 to} D ₃ for outputting each voltage vector based on the selected three voltage vectors and voltage command vector.
At the same time, the voltage vector output order determination means 40 determines the order in which the three vectors are output in the current control cycle T so that switching loss does not occur in two or more phases when transitioning from one vector to the next vector. . For example, when the tip of the voltage command vector v _REF is located in the region S ₉ and three vectors v ₂ , v ₈ , v ₉ are selected as output voltage vectors, the vector v ₂ → v ₈ → v to determine the _9. In addition, as described above, the voltage vector output order determining means 40, based on the vector output at the end of each control cycle T, generates a vector as necessary so that no switching loss occurs at the beginning of the next control cycle. The process of changing the output order of is performed.

In the voltage vector output means 50, numerical values corresponding to three voltage vectors are selected from numerical values 1 to 18 corresponding to the names of the voltage vectors, and these numerical values are selected according to the time ratios D _{1 to} D _{3 of} each vector and the output order. Output.
The decoding means 60, the above three numerical values to decode each phase of the switch state of the three-level inverter, generates a drive signal of each IGBT U _A ~IGBT W _D. These drive signals are transmitted to the gate of the IGBT constituting the three-level inverter, and the three-level inverter is switched.
Thereby, the three-phase AC voltage according to the three-phase AC voltage command is output.

10: Voltage command vector area discriminating means 20: Voltage vector selecting means 30: Selected vector output time ratio calculating means 40: Selected vector output order determining means 50: Voltage vector output means 60: Decoding means U _{A to} W _D : IGBT
_{B 1,} B _2: DC power source D ₁ to D _6: Diode M: Load N: neutral point N _P: DC midpoint U, V, W: Output terminal

Claims (2)

The three-phase inverter connected to the DC power supply is turned on and off, and the three phases of DC high voltage, medium voltage, and low voltage are output from each phase at a predetermined time ratio. In a three-level inverter that outputs a three-phase AC voltage according to the AC voltage command,
As the switch state of each phase of the semiconductor switch, a state in which a DC high voltage, medium voltage, or low voltage is output is expressed as 1, 0, −1, respectively. While expressing the phase output voltage as an output voltage vector,
The distance is close to the voltage command vector obtained by converting the three-phase AC voltage command of the inverter to two-phase AC, and the absolute value of the result of adding the switch states of each phase for three phases is 1 or less. Select three such output voltage vectors such that
When transitioning from one output voltage vector to another, among the three selected output voltage vectors, the output voltage vector is transitioned and selected so that the switch state does not change simultaneously in two or more phases. A control method for a three-level inverter, characterized in that a time ratio of each output voltage vector is adjusted so that a combined vector of the three output voltage vectors coincides with the voltage command vector. The three-phase inverter connected to the DC power supply is turned on and off, and the three phases of DC high voltage, medium voltage, and low voltage are output from each phase at a predetermined time ratio. In a three-level inverter that outputs a three-phase AC voltage according to the AC voltage command,
As the switch state of each phase of the semiconductor switch, a state in which a DC high voltage, medium voltage, or low voltage is output is expressed as 1, 0, −1, respectively. When the phase output voltage is expressed as an output voltage vector,
Voltage command vector region discriminating means for discriminating a region where the tip of the voltage command vector obtained by converting the three-phase AC voltage command of the inverter into a two-phase AC coordinate is located;
Voltage vector selection means for selecting three of the output voltage vectors that are vectors surrounding the region, and whose absolute value as a result of adding the switch states of each phase for three phases is 1 or less;
Selection vector output time ratio calculation means for calculating a time ratio for outputting each output voltage vector so that a combined vector of the three output voltage vectors selected by the selection means matches the voltage command vector;
A selection vector output that determines the output order of the output voltage vectors so that the switch state does not change simultaneously in two or more phases when transitioning from one output voltage vector to another output voltage vector among the three output voltage vectors Order determination means;
Voltage vector output means for outputting the three output voltage vectors according to the time ratio and output order;
Decoding means for generating a drive signal for the semiconductor switch based on the output of the output means;
A control device for a three-level inverter.

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