JP5147624B2 - Inverter device - Google Patents

Description

  The present invention relates to an inverter device, and more particularly to a multiple inverter device having an output capacity increased by combining outputs of a plurality of inverters.

  When connecting an inverter device to a power system, as shown in [Non-Patent Document 1], a guideline is provided to prevent a harmonic current of a certain level or more from flowing into the power system. In [Document 2], harmonics included in the output voltage waveform are reduced by synthesizing the outputs of a plurality of inverters via a transformer as shown in FIG. A multi-inverter device for reducing the above is disclosed.

  In the multiple inverter device, each phase AC output terminal of the unit inverter 101 is connected to one of primary windings of the open delta winding transformer 121, and each phase AC output terminal of the unit inverter 102 is connected to the open delta winding. The unit 121 is connected to the other primary winding of the transformer 121, and the DC lines of the unit inverter 101 and the unit inverter 102 are both connected to the DC capacitor 111 to form a unit inverter pair 181.

  When the unit inverters 101 and 102 constituting the unit inverter pair 181 have AC output voltage commands of the same magnitude and opposite polarities, the output voltage pulse becomes three levels and harmonics can be reduced.

  The multiple inverter device disclosed in FIG. 2 includes a unit inverter pair 182 having the same configuration as the unit inverter pair 181 and the unit inverter pair 181 in parallel on the secondary side of the open winding transformer 122 and the open winding transformer 121. It is connected to the. Further, in the multiple inverter device, the DC terminals of the unit inverter pair 181 and the unit inverter pair 182 are both connected to the DC capacitor 111. Further, as a modulation method of each unit inverter, a well-known PWM modulation is used, and the carrier frequencies of all unit inverters are the same. Further, the phase of the carrier of each unit inverter constituting the unit inverter pair 181 is different from that of each unit inverter constituting the unit inverter pair 182 by 90 degrees.

  By shifting the carrier phases of the unit inverter pair 181 and the unit inverter pair 182, the harmonic voltage output from the multiple inverter device 131 can be canceled. Further, when a multiple inverter device is configured by a plurality of unit inverter pairs, for example, n units, the carrier phase of each unit inverter pair has a phase difference of 180 degrees / n degrees, so that the harmonics output from each unit inverter Can cancel the voltage.

  Next, the configuration of the multiple inverter device disclosed in [Patent Document 1] is shown in FIG. This multiple inverter device converts the first DC capacitors 112 and 113 that are electrically insulated from each other and the DC voltage applied to the first DC capacitor 112 into a three-phase AC voltage. The first group of unit inverters 101 and 103 that are common and the DC voltage applied to the second DC capacitor 113 are converted into a three-phase AC voltage, and the second group of unit inverters 102 that have a common DC voltage. , 104 and the primary windings of the open delta-connected transformers 121, 122 connected to these unit inverters, respectively, the phase AC output ends of the unit inverters 101, 103 of the first group, At the end, each phase AC output end of the second group of unit inverters 102 and 104 is connected and multiplexed in series on the secondary side of the transformer.

  [Patent Document 1] shows that the multiple inverter device 132 shown in FIG. 3 is characterized in that it can perform well-known voltage utilization rate improvement control such as adding a third-order zero-phase voltage to the output voltage command. .

  Further, the multiple inverter device 131 of FIG. 2 disclosed in [Non-Patent Document] is treated as a prior art in [Patent Document 1].

  In the multiple inverter device 131 of FIG. 2, when the well-known voltage utilization rate improvement control is performed, the unit inverter 101, the DC capacitor 111, the unit inverter 102, and the open delta connection transformer 121 are shown by the thick lines in FIG. Excessive zero-phase current will circulate.

  However, in FIG. 2, only one phase of the flowing zero-phase current is shown, but actually, the same-phase current flows in three phases. Thereafter, when the path of the zero-phase current is shown in another figure, only one phase is indicated by a thick line.

  In the circuit shown in FIG. 3, since the first DC capacitor 112 and the second DC capacitor 113 are electrically insulated from each other, zero-phase current does not flow in the above-described path, and a well-known voltage utilization rate. Improvement control can be implemented and the utilization factor of the inverter can be improved.

Japanese Patent Laid-Open No. 06-008821 JEAG 9702-1995 Hasegawa, Takeda, et al., “Development of large capacity case-type reactive power compensator for system stabilization”, IEEJ Transaction D, Vol. 111, No. 10, 1985, p845-854

  In the specification of the present invention, the one connected to the converter will be described as “transformer primary side”, and the one connected to other than the converter such as a power system will be described as “transformer secondary side”.

  FIG. 4 is a multiple inverter device in which the connection method on the transformer secondary side of the multiple inverter device 132 shown in FIG. 3 is changed in parallel.

  The inventors have found that in the configuration of the multiple inverter device 133 shown in FIG. 4, a zero-phase current flows through a route different from the route taken as a countermeasure in [Patent Document 1].

  That is, when a zero-phase voltage is generated at the AC output terminal of the unit inverter, for example, the primary winding of the unit inverter 102, the open delta connection transformer 121, the unit inverter 101, the first inverter as shown by the thick line in FIG. A zero-phase current flows through a path of the DC capacitor 112, the unit inverter 103, the primary winding of the open delta connection transformer 122, the unit inverter 104, and the second DC capacitor 113.

  Therefore, when a general tripod iron core is used for the open delta connection transformers 121 and 122 in FIG. 4, the magnetic flux generated in the transformer by the zero phase voltage leaks into the air, and the exciting inductance for the zero phase current. Is so small that an excessive zero-phase current flows.

  In order to suppress the above-described excessive zero-phase current, a conventional technique requires a transformer using a five-legged core, a zero-phase reactor, and the like, and the apparatus becomes large.

  An object of the present invention is to provide a technique in which a zero-phase current does not flow in a multiple inverter device multiplexed in parallel on the secondary side of a transformer.

  Note that the zero-phase voltage superimposed on the AC output terminal of the unit inverter is generated by, for example, a known dead time provided to prevent a PN short circuit of the inverter. The mechanism for generating the zero-phase voltage is described in the third embodiment.

  In order to achieve the above object, the present invention comprises two or more unit inverters and a transformer, wherein the two or more unit inverters are connected in parallel on the secondary side of the transformer, The unit inverter has a self-extinguishing element and converts a DC voltage of a voltage source into a three-phase AC voltage. The transformer is an open delta transformer in which a primary winding is an open delta connection. The two unit inverters and the transformer constituting the set include one of the unit inverters at one end of the primary winding of the transformer and the other of the unit inverters at the other end. The DC voltage sources connected to the unit inverters are all insulated from each other.

  Furthermore, in the inverter device of the present invention, a DC capacitor is applied to the DC voltage source of each unit inverter.

  In order to achieve the above object, the present invention includes two or more unit inverters and a transformer, and the two or more unit inverters are connected in parallel on the secondary side of the transformer. The unit inverter converts a DC voltage of a DC capacitor into a three-phase AC voltage by a self-extinguishing element, and the transformer is an open delta transformer in which a primary winding is an open delta connection. The two unit inverters and the transformer constituting the inverter device include one of the unit inverters at one end of the primary winding of the transformer and the other of the unit inverters at the other end. The DC capacitors of the two unit inverters are connected to each other and insulated from each other, and the DC voltage of the DC capacitors is individually controlled. It is.

  Furthermore, the inverter device of the present invention includes an average DC voltage control function for controlling an average value of each DC capacitor of the two unit inverters according to a DC voltage command, and a DC voltage individually for the DC voltage command. An individual DC voltage control function for controlling is provided.

  Furthermore, the inverter device of the present invention is characterized in that the voltage of each DC capacitor of the two unit inverters is controlled according to the average of the voltage of each DC capacitor of the two unit inverters. .

  Furthermore, the inverter device of the present invention individually controls the DC voltage of each DC capacitor connected to the two unit inverters by individually controlling the phase of each AC output voltage of the two unit inverters. It has the function to perform.

  Furthermore, the inverter device of the present invention is characterized in that it has a function of switching a control method for individually controlling the DC voltage of each DC capacitor of the two unit inverters according to the magnitude of the reactive power command. .

  Further, in the inverter device of the present invention, the control circuit for controlling the output voltage of each unit inverter includes a rotation coordinate control system on the d-axis and the q-axis for controlling the output voltage and current of each unit inverter, The control circuit includes a vector control arithmetic unit and an individual DC voltage control circuit, and the vector control arithmetic unit inputs a reactive power command and an active power command to be output by each unit inverter, and each unit inverter A three-phase two-phase conversion and a dq coordinate conversion of the three-phase output current common to the two unit inverters and a current command calculator that calculates a d-axis current command and a q-axis current command to be output by the unit feedback a coordinate converter that outputs a d-axis current and a feedback q-axis current, the d-axis current command, the q-axis current command, the feedback d-axis current, and the feedback q A current controller for calculating a d-axis voltage command and a q-axis voltage command to be output from each unit inverter, and a phase adjuster for inverting the phase of the d-axis voltage command and the q-axis voltage command by 180 ° And an inverse coordinate converter for calculating a three-phase output voltage command of each unit inverter by performing dq reverse conversion and two-phase three-phase conversion, and the individual DC voltage control circuit includes each DC capacitor of each unit inverter A compensation voltage is calculated according to the deviation between the DC voltage and the DC voltage command and the polarity of the feedback q-axis current, and when the reactive power command is larger than the active power command, By adding a compensation voltage to the q-axis voltage command, a deviation between each DC voltage of the two unit inverters and the DC voltage command is reduced.

  Furthermore, the inverter device of the present invention outputs a compensation voltage according to a deviation between each DC voltage of the two unit inverters and the DC voltage command, and adds the compensation voltage to the d-axis voltage command. When the magnitude of the reactive power command is larger than the size of the active power command, the deviation between each DC voltage of the two unit inverters and the DC voltage command is reduced.

  Furthermore, the inverter device of the present invention is characterized in that the inverter device is set as one set and multiplexed by connecting the sets in parallel on the secondary side of the transformer.

  In order to achieve the above object, the present invention includes two or more unit inverters and a transformer, and the two or more unit inverters are connected in parallel on the secondary side of the transformer. The unit inverter converts a DC voltage of a DC voltage source into a three-phase AC voltage by a self-extinguishing element, and the transformer is an open delta transformer in which a primary winding is an open delta connection. The two unit inverters and the transformer constituting the set include one of the unit inverters at one end of the primary winding of the transformer and the other of the unit inverters at the other end. DC capacitors connected to each of the first unit inverters of the plurality of sets are connected to each other, and directly connected to each of the second unit inverters of the plurality of sets. Capacitors are connected to each other, and output a compensation voltage having a reverse polarity with respect to a zero-phase voltage generated due to a dead time provided so that the DC capacitor of the unit inverter is not short-circuited with DC. It is a feature.

  Furthermore, the inverter device according to the present invention provides a compensation voltage based on the length of the dead time given to each unit inverter, the carrier cycle of each unit inverter, and the polarity of each phase output current output by each unit inverter. The zero-phase voltage generated by each unit inverter is suppressed by calculating and adding the compensation voltage to each phase voltage command of each unit inverter.

  Furthermore, in the inverter device of the present invention, the dead time compensation function includes a polarity determination unit that determines the polarity of each phase output current output from each unit inverter, and a known dead time length given to each unit inverter. A compensation voltage calculator for calculating a compensation voltage determined from a carrier cycle of each unit inverter, and adding or subtracting the compensation voltage to each phase voltage command of each unit inverter, It is characterized by suppressing the flowing zero-phase current.

  In order to achieve the above object, the present invention includes two or more unit inverters and a transformer, and the two or more unit inverters are connected in parallel on the secondary side of the transformer. The unit inverter converts a DC voltage of a DC voltage source into a three-phase AC voltage by a self-extinguishing element, and the transformer is an open delta transformer in which a primary winding is an open delta connection. The two unit inverters and the transformer constituting the set include one of the unit inverters at one end of the primary winding of the transformer and the other of the unit inverters at the other end. DC capacitors connected to each of the first unit inverters of the plurality of sets are connected to each other, and directly connected to the second unit inverters of the plurality of sets. The capacitors are connected to each other, detect the zero-phase current output from each unit inverter, and control the output voltage of each unit inverter based on the detected value of the zero-phase current. The zero-phase current that flows is suppressed.

  According to the inverter device of the present invention, for example, even when a zero-phase voltage is generated due to a dead time or the like, the DC capacitors connected to each unit inverter are electrically insulated from each other, so that no zero-phase current flows. .

  As a result, the zero-phase reactor for suppressing the zero-phase current becomes unnecessary, and the apparatus can be downsized.

  On the other hand, as in FIGS. 2 and 3, the harmonic voltage can be reduced by shifting the phase of the carrier.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 shows an outline of a grid-connected multiple inverter device which is a first embodiment of a multiple inverter device of the present invention.

  First, the structure of the grid connection multiple inverter apparatus which is 1st embodiment of this invention is demonstrated.

  The grid interconnection multiple inverter device 31 of the present embodiment includes voltage-type inverter devices (hereinafter simply referred to as unit inverters) 1 and 2 having self-extinguishing elements such as MOSFETs and IGBTs, and unit inverters 1 and 2. A control circuit 61 for outputting an output voltage command for controlling the output voltage, and a gate pulse for controlling on / off of the self-extinguishing element of the unit inverter in accordance with the output voltage command given from the control circuit 61 Unit inverter pair 81, 82 each comprising a PWM circuit 51, 52 for generating a DC capacitor 11 and 12, each of which is electrically insulated and connected to the unit inverter 1, 2 respectively. It comprises winding transformers (hereinafter simply referred to as “transformers”) 21 and 22, an AC voltage detector 71, a current detector 72, and a DC voltage detector 73.

  One end of the primary winding of the transformer 21 is connected to one of the two unit inverters constituting the inverter device 81, that is, each phase AC output terminal of the unit inverter 1, and the other end of the transformer 21 is connected. Is connected to each phase AC output terminal of the unit inverter 2.

  Similarly, the transformer 22 is connected to one end of the primary winding of each unit AC constituting the unit inverter pair 82 among the unit inverters 82, and to the other end of the transformer 22. Each phase AC output terminal of the unit inverter 4 is connected.

  Next, the operation of the grid interconnection multiple inverter device 31 according to the first embodiment of the present invention will be described.

  The multiple inverter device 31 that converts a DC voltage applied to the DC capacitors 11, 12, 13, and 14 to an AC voltage supplies an AC output current to, for example, a commercial AC power supply 41.

Each control circuit 61 includes voltages Vu1, Vv1, Vw1 of the commercial AC power supply 41 and output currents Iu1, of the unit inverters 1, 2 detected by the voltage detector 71, the current detector 72, and the DC voltage detector 73. iv1, Iw1 and the DC voltage V _dc _1 of the unit inverters 1, as input V _d c_2, the output voltage to control the pre respective output voltages of the serial unit inverters 1 command Vu_1 ^*, Vv_1 ^*, Vw_1 ^* , Vu_2 ^* , Vv_2 ^* , and Vw_2 ^* are output.

Each of the PWM circuits 51 and 52 is based on the magnitude relationship between the output voltage commands Vu_1 ^* , Vv_1 ^* , Vw_1 ^* , Vu_2 ^* , Vv_2 ^* , Vw_2 ^* and a carrier such as a triangular wave. A gate pulse for ON / OFF control of the arc element is output.

  One end of the primary winding of the transformer 21 is connected to each phase output end of the unit inverter 1, and the other end is connected to each phase output end of the unit inverter 2. The difference between the output voltages of the unit inverter 1 and the unit inverter 2 output based on the gate pulse is applied to both ends of.

  Therefore, if the output voltage commands given to the unit inverters 1 and 2 connected to the same transformer 21 have the same magnitude and reverse polarity, the unit inverter 1 is connected to the primary winding of the transformer 21. , 2 can output a voltage twice as large as the output voltage.

  Moreover, since the pulse change of the output voltage applied to the primary winding of the transformer 21 is three levels, the harmonic voltage can be reduced.

  Further, by connecting the unit inverter pairs 81 and 82 to the primary side of the transformers 21 and 22 respectively, and connecting them in parallel on the secondary side to shift the phase of the carriers of the unit inverter pairs 81 and 82, further harmonics are obtained. The voltage can be reduced.

  Moreover, the utilization factor of an inverter can be improved by combining with known voltage utilization factor improvement control such as adding the third-order zero-phase voltage to the output voltage command.

  Hereinafter, it will be described that the multiple inverter device 31 of the present invention, which is a novel point, has a configuration in which no zero-phase current flows even if a zero-phase voltage is generated.

  FIG. 5 shows a circuit diagram in which only the main circuit portion is extracted from the grid interconnection multiple inverter device 31 according to the first embodiment of the present invention shown in FIG.

  The conventional multiple inverter device 132 of FIG. 4 is regarded as a configuration in which the DC capacitors 11 and 13 connected to the unit inverters 1 and 3 of FIG. 5 are replaced with a common DC capacitor 112 that is not insulated from each other. Similarly, it can be considered that the DC capacitors 12 and 14 respectively connected to the unit inverters 102 and 104 in FIG. 5 are replaced by common DC capacitors 113 that are not insulated from each other.

  However, when a zero-phase voltage is superimposed on each phase AC output terminal of each unit inverter, the unit inverter 102, the primary winding of the transformer 121, the unit inverter 101, the second DC capacitor 112, and the unit inverter indicated by the bold lines in FIG. 103, a primary winding of the transformer 122, the unit inverter 104, the first DC capacitor 113, and the like, an excessive zero-phase current flows.

  On the other hand, in the multiple inverter device 31 of the present invention of FIG. 5, unlike the conventional multiple inverter device 132, the DC capacitors 11 and 13 respectively connected to the unit inverters 1 and 3 are insulated. Further, since the DC capacitors 12 and 14 connected to the unit inverters 102 and 104, respectively, are insulated, there is no path through which the zero phase current flows, and no zero phase current flows through the unit inverter. .

  Therefore, according to this device configuration, the zero-phase reactor for suppressing the zero-phase current becomes unnecessary, and the device can be miniaturized.

  Next, another embodiment of the present invention will be described with reference to FIGS.

  FIG. 7 shows an outline of a grid-connected multiple inverter device according to the second embodiment of the present invention.

  When the inverter device 33 shown in FIG. 7 is connected to the power system and is used as a reactive power control device that improves the voltage stability of the system by supplying reactive power to the power system based on the reactive power command. The control circuit will be described with reference to FIG.

  Unlike the first embodiment, the configuration of the inverter device 33 of the present invention does not necessarily require that the unit inverter pairs are connected in multiples via a transformer.

  FIG. 6 is a configuration diagram of the control circuit 62 that controls the unit inverters 1 and 2 connected to the transformer 21 shown in FIG. However, the input of Vu1, Vv1, and Vw1 detected by the AC voltage detector 71 is omitted.

  The control circuit 62 includes a vector control calculator 311, an average DC voltage control circuit 211, and an individual DC voltage control circuit 212.

The vector control calculator 311
(1) “Reactive power command Q ^* to be output by unit inverters 1 and 2 and active power command P ^* as inputs, and d-axis current command Id ^* and q-axis current command to be output by unit inverters 1 and 2 Current command calculator 301 for calculating Iq ^* ;
(2) “Coordinate converter that performs three-phase two-phase conversion and dq coordinate conversion on the output currents Iu1, Iv1, and Iw1 common to the unit inverters 1 and 2 and outputs a feedback d-axis current Id1 and a feedback q-axis current Iq1. 303 ",
(3) “The d-axis current command Id ^* , the q-axis current command Iq ^*, and the feedback d-axis current Id1 obtained by converting the inverter output currents Iu1, Iv1, Iw1 by dq coordinates, and the feedback q-axis current Iq1 are input. A current controller 302 for calculating a d-axis voltage command Vd ^* and a q-axis voltage command Vq ^* to be output by the inverter;
(4) “Phase adjuster 304 for inverting the phase of the d-axis voltage command Vd ^* and the q-axis voltage command Vq ^* by 180 °”;
(5) “Inverse coordinate converter 305 that performs dq inverse transformation and two-phase three-phase transformation to calculate output voltage commands Vu_1 ^* , Vv_1 ^* , Vw_1 ^* and Vu_2 ^* , Vv_2 ^* , Vw_2 ^* of the unit inverters 1 and 2 Is provided.

In addition, since dq coordinate transformation, three-phase two-phase transformation, dq inverse coordinate transformation, and two-phase three-phase transformation are well known, detailed explanation is omitted.
In this specification, the dq coordinate conversion is performed using the phases of Vu1, Vv1, and Vw1 detected by the AC voltage detector 71 as the reference phase and the d-axis is treated as an effective component. Is not limited to the above description.

  In the following, the DC voltage applied to the DC capacitors 11 and 12 insulated from each other in the inverter device 33 shown in FIG. 7, which is a novel point in the control circuit 62 of the present invention shown in FIG. 6, is controlled. Two DC voltage control circuits, that is, the average DC voltage control circuit 211 and the individual DC voltage control circuit 212 will be described in detail.

  First, the average DC voltage control circuit 211 that controls the average DC voltage of the DC capacitors 11 and 12 connected to the unit inverters 1 and 2 shown in FIG. 7 will be described.

  Usually, in the reactive power control device, in order to prevent the DC voltage from being lowered, it is necessary to take in the active power corresponding to the loss of the inverter from the system.

The average DC voltage control circuit 211 includes a DC voltage command value V _dc ^* of the DC capacitors 11 and 12 connected to the unit inverters 1 and 2, and a DC voltage V _dc _ 1 actually applied to the DC capacitors 11 and 12. , V _dc _ 2 based on the deviation from the average value V _dc _ave 1, the average DC voltage controller 201 calculates the average active power command P ^* so as to make this deviation zero, and outputs it to the vector control calculator 311. .

As a result, the average DC voltage V _dc _ave1 applied to the DC capacitors 11 and 12 connected to the unit inverters 1 and 2 can be controlled to the DC voltage command value V _dc ^* .

  Next, the control mechanism of the individual DC voltage control circuit 212 that individually controls the DC voltage of the DC capacitors 11 and 12 connected to the unit inverters 1 and 2 in FIG. 7 will be described.

  Since the DC voltages of the unit inverters 1 and 2 are electrically insulated from each other, the DC voltage may be unbalanced if the losses of the inverters 1 and 2 are different.

For this reason, the individual DC voltage control circuit 212 individually controls the DC voltages V _dc _ 1 and V _dc _ 2 of the capacitors 11 and 12 connected to the unit inverters 1 and 2.

  Here, the active powers output from the unit inverters 1 and 2 are P_1 and P_2, the output voltages of the unit inverters 1 and 2 are dq coordinate-converted, and the d-axis output voltages Vd_1 and Vd_2 and the q-axis inverter output voltage Vq_1, respectively. Assuming Vq_2, it can be expressed by Equation 1 using feedback d-axis current Id1 and feedback q-axis current Iq1 obtained by converting the output current to the AC terminal side of unit inverters 1 and 2 by dq coordinates.

  Since the output currents of the unit inverters 1 and 2 are common, according to Equation 1, in order to independently control the active powers P_1 and P_2 output from the unit inverters 1 and 2, Vd_1 and Vq_1 of the unit inverters 1 and 2 are used. , Vd_2, and Vq_2 need to be controlled.

Here, since the reactive power control apparatus takes in the active power only for the loss of the inverter, when the unit inverters 1 and 2 output the reactive power, Iq1 >> Id1. Therefore, the first term on the right side of Equation 1 can be almost ignored, and the effective power output from the unit inverters 1 and 2 and the direct current capacitors 11 and 12 can be controlled by controlling Vq_1 and Vq_2 that can be controlled independently of the second term. The DC voltages V _{dc —} 1 and V _{dc —} 2 applied to the can be controlled.

  However, when the unit inverters 1 and 2 do not output reactive power, that is, in a no-load operation state, Iq1 = 0. Therefore, even if Vq_1 and Vq_2 are controlled according to Equation 1, the active power is controlled. Can not.

Therefore, when the unit inverters 1 and 2 do not output reactive power, that is, in a no-load operation state, among the first terms on the right side of Equation 2, Vd_1 and Vd_2 that can be controlled independently by the unit inverters 1 and 2 are If controlled, the effective power output from the unit inverters 1 and 2 and the DC voltages V _dc _ 1 and V _dc _ 2 applied to the DC capacitors 11 and 12 can be controlled.

  Next, the configuration and operation of the individual DC voltage control circuit 212 that individually controls the DC voltage of the DC capacitors 11 and 12 connected to the unit inverters 1 and 2 of FIG. 7 using the mechanism described above will be described. .

The individual DC voltage control circuit 212 that controls the DC voltage V _dc _ 1 of the DC capacitor 11 of the unit inverter 1 in FIG. 7 is connected to the DC voltage command V _dc ^* and the DC voltage V _dc _ 1 of the DC capacitor 11 of the unit inverter 1. Is based on the deviation between the Q-axis individual DC voltage controller 203 that outputs the q-axis voltage correction signal Vqh1, the DC voltage command V _dc ^*, and the DC voltage V _dc _ 1 of the DC capacitor 11 of the unit inverter 2. Based on this, the D-axis individual DC voltage control 204 that outputs the d-axis correction signal Vdh_1, the polarity determiner 202 that determines the polarity of the feedback q-axis current Iq1, and the reactive power command Q ^* are 0, that is, no load. And a no-load state determination unit 205 for detection.

  The polarity determiner 202 outputs a value according to Table 1 according to the polarity of the feedback q-axis current Iq1 in order to determine the polarity of the active power P_1 output from the unit inverter 1.

The product of the outputs of the Q-axis individual DC voltage controller 203 and the polarity determiner 202 is added to the q-axis voltage command Vq ^* , so that the DC voltage V _dc _ 1 of the unit inverter 1 is changed to the DC voltage command value V _dc ^*. Can be controlled.

The no-load determination unit 205 detects that the reactive power command Q ^* is 0, that is, the no-load operation state, and outputs a value according to Table 2.

Then, by adding the product of the d-axis voltage correction signal Vdh1 that is the output of the D-axis individual DC voltage control circuit 204 and the no-load determination unit 205 to the d-axis output voltage command Vd ^* , even when there is no load, The DC voltage V _dc _ 1 of the unit inverter 1 can be controlled.

  The individual DC voltage control circuit 212 can be controlled regardless of the operating state of the reactive power control device.

As described above, the average DC voltage control circuit 211 and the individual DC voltage control circuit 212 can maintain the DC voltage V _dc _ 1 of the unit inverter 1 in FIG. 7 at the DC voltage command V _dc ^* .

Also, as in the case of individually controlling the DC voltage V _dc _2 of the DC capacitor 12 of the unit inverters 2, separate DC voltage and the DC voltage V _dc _2 the q-axis feedback current Iq1 the DC capacitor 12 of unit inverters 2 An operation similar to that performed when the DC voltage V _dc _ 1 of the DC capacitor 11 of the unit inverter 1 is controlled is input to the control circuit 212, and the output of the individual DC voltage control circuit 212 is added to the output of the phase adjuster. Thus, the DC voltage V _{dc —} 2 applied to the DC capacitor connected to the unit inverter 2 in FIG. 7 can be controlled to the DC voltage command V _dc ^* . Although the direct voltage control accuracy is slightly reduced, one of the two individual DC voltage control circuits 212 shown in FIG. 6 can be omitted.

The DC voltage command V _dc ^* of the individual DC voltage control circuit 212 may be the average value V _dc _ave1 of the DC voltages V _dc _ 1 and V _dc _ 2 of the unit inverters 1 and 2.

  As described above, the control circuit 62 can control the DC voltage of the unit inverters 1 and 2 that are connected to the same transformer as shown in FIG.

  Further, as a matter of course, the control circuit 62 of the present invention shown in FIG. 6 can be applied to the control circuit 61 of FIG. 1 and applied to the DC capacitors 11, 12, 13, and 14 that are electrically insulated. Since the DC voltage can be controlled independently, when increasing the number of multiplexing, a control circuit 62 may be added for each inverter device connected to the same transformer, and the number of multiplexing can be easily increased.

  Next, as another embodiment of the present invention, FIG. 8 shows an example of a control circuit when the conventional multiple inverter device 132 shown in FIG. 9 is used in a reactive power control device. FIG. 3 is a diagram in which only the main circuit elements of FIG. 9 are extracted.

  The control circuit of the present invention shown in FIG. 8 suppresses the zero-phase current in the multiple inverter device in which a part of the DC capacitor is electrically connected like the conventional multiple inverter device 132 shown in FIG. Therefore, the main feature is that a dead time compensation circuit 411 and a zero-phase current suppression circuit 412 are provided.

  First, the generation mechanism of the zero phase voltage resulting from the dead time will be described.

  FIG. 10 shows the U-phase and DC capacitor 112 extracted from the unit inverter 101 of FIG.

  The IGBTs 501 and 502 in FIG. 10 are turned on and off by controlling gate pulses (Gate_P and Gate_N) input to the gates, and control the output voltage of the inverter.

  FIG. 11 shows the relationship between the gate signal and the inverter output voltage, that is, the relationship between the P-side gate signal Gate_P, the N-side gate signal Gate_N, and the inverter output voltage.

  However, the gate pulses Gate_P and Gate_N and the inverter output voltage in an ideal state with no dead time are indicated by solid lines Vout_i, and the gate pulses Gate_P and Gate_N and the inverter output voltage when the dead time is provided are indicated by broken lines.

11A shows the case where the polarity of the inverter output current I _{conv in} FIG. 10 is positive, and FIG. 11B shows the case where the polarity of the inverter output current I _conv is negative. The relationship between the side gate signal Gate_P, the N side gate signal Gate_N, and the inverter output voltage is shown.

  However, when the dead time is not provided, the P-side gate signal Gate_P, the N-side gate signal Gate_N, and the inverter output voltage are the same in FIGS. 11A and 11B.

Further, in order to prevent the P-side IGBT and the N-side IGBT from being turned ON at the same time, when a dead time (Td) in which both Gate_P and Gate_N are OFF is provided, the P-side gate signal Gate_P, the N-side gate signal Gate_N, and the inverter The output voltage Vout_d is as indicated by a broken line, and is different from the case where no dead time is provided. The influence of the dead time on the P-side gate signal Gate_P, the N-side gate signal Gate_N, and the inverter output voltage varies depending on the polarity of the inverter output current I _CONV during the dead time period. For example, when the inverter output current I _CONV is positive, as shown in FIG. 11A, the difference Vout_d− between the ideal inverter output voltage Vout_i having no dead time and the inverter output voltage Vout_d having the dead time is provided. Vout_i becomes negative. This Vout_d−Vout_i corresponds to a voltage generated by dead time. Assuming that a value obtained by averaging Vout_d−Vout_i within one carrier period is −V_deadtime, when I _CONV is positive, the inverter can be regarded as outputting −V_deadtime due to dead time. On the other hand, when I _CONV is negative, Vout_d−Vout_i is positive as shown in the waveform of Vout_d in FIG. 11B, and when I _CONV is negative, the inverter is regarded as outputting + V_deadtime due to dead time. Can do.

When the inverter outputs three-phase AC currents I _CONV _u, I _CONV _v, I _CONV _w, the voltage V_deadtime obtained by averaging the voltage generated due to the effect of dead time within one carrier period and the voltage of each phase FIG. 12 shows the relationship of the zero-phase voltage V0 that is the sum of the two.

FIG. 12 shows that zero phase voltage is generated due to dead time. Here, when the dead time is Td, the carrier period is Tcarry, and the PN DC voltage is 2 V _dc , the amplitude V_dead_peak of V_deadtime is expressed by Equation 2.

  In order to suppress the zero-phase voltage due to the dead time, a compensation voltage having a magnitude indicated by Equation 2 may be applied according to the output current of the inverter, and a reverse polarity voltage generated due to the dead time may be applied.

  Next, the operation of the dead time compensation circuit 411 that compensates for the zero-phase voltage caused by the dead time will be described.

  A dead time compensation circuit 411 shown in FIG. 8 includes a polarity determination unit 401 that determines the polarities of the output currents Iu1, Iv1, Iw1 and Iu2, Iv2, Iw2 of the unit inverters 101, 102 and 103, 104 of FIG. And a compensation voltage calculator 402 for calculating a compensation voltage for compensating for a zero-phase voltage caused by time.

  The polarity determination unit 401 outputs a value according to Table 3 based on the polarities of the output currents Iu1, Iv1, Iw1 and Iu2, Iv2, Iw2 of the unit inverters 101, 102 and the unit inverters 103, 104 of FIG. .

Then, the compensation voltage calculator 402 takes the product of the output of the polarity determiner 401 and the amplitude V_dead_peak of V_deadtime expressed by Equation 4 to obtain the dead time compensation voltages Vdthos_u, Vdthos_uv, and Vdthos_w of each of the unit inverters 101 and 103. Add to the phase output voltage commands Vu_1 ^* , Vv_1 ^* , Vw_1 ^* , Vu_3 ^* , Vv_3 ^* , Vw_3 ^* .

Further, since the polarity of the current detected by the current detector 72 of FIG. 9 is reversed between the unit inverters 101 and 102 and the unit inverters 103 and 104, each phase output voltage command Vu_2 ^{* of the} unit inverters 102 and 104 is obtained ^. , Vv_2 ^* , Vw_2 ^* , Vu_4 ^* , Vv_4 ^* , Vw_4 ^* , the zero phase compensation voltage V0hos is subtracted.

  The dead time compensation circuit 411 can compensate for the zero-phase voltage caused by the dead time. In a system in which all of the DC capacitors are not insulated like the conventional multiple inverter device 132 shown in FIG. The zero-phase current that flows due to the zero-phase voltage caused by time can be suppressed.

  Next, the zero-phase current suppression circuit 412 that is the second feature of the control circuit of the present invention will be described.

  The zero-phase current suppression circuit 412 calculates the zero-phase current I0_1 flowing through the unit inverters 101, 102, 103, and 104 in FIG. 9 by calculating the average of the phase output currents Iu1, Iv1, and Iw1 of the unit inverter 101. And a zero-phase current controller 208 for calculating a compensation voltage based on the calculated zero-phase current I0_1.

The output of the zero-phase current suppression circuit 412 is added as a zero-phase compensation voltage Vdt_hos to each phase output voltage command Vu_1 ^* , Vv_1 ^* , Vw_1 ^* , Vu_3 ^* , Vv_3 ^* , Vw_3 ^* of the unit inverters 101 and 103. Further, since the polarity of the current detected by the current detector 72 in FIG. 9 is reversed between the unit inverters 101 and 102 and the unit inverters 103 and 104, each phase output voltage command Vu_2 ^* , The zero-phase compensation voltage V0hos is subtracted from Vv_2 ^* , Vw_2 ^* , Vu_4 ^* , Vv_4 ^* , and Vw_4 ^* .

  The zero-phase current suppression circuit 412 can suppress the zero-phase current flowing through the unit inverter and the DC capacitor connected to different transformers as in the conventional multiple inverter device 132 shown in FIG.

  The control circuit of the present invention including the dead time compensation circuit 411 and the zero-phase current suppression circuit 412 shown in FIG. 8 can greatly reduce the zero-phase current flowing through the inverter and the DC capacitor connected to different transformers.

  As a result, a general tripod iron core can be used for the iron cores of the transformers 121 and 122 in FIG. 9, and the multiple inverter device can be reduced in size and cost.

  Further, since the first group of DC capacitors 112 and the second group of DC capacitors 113 can be respectively connected, the pulsation of the DC voltage of each DC capacitor is reduced, and the utilization rate and loss reduction of the DC capacitors are reduced. It becomes possible.

  The present invention can be generally applied to a multiple inverter device that uses a self-extinguishing element such as a MOSFET or IGBT and multiplexes outputs of a plurality of unit inverters via a transformer.

The outline | summary of the grid connection inverter apparatus which is the 1st Example form of the multiple inverter apparatus of this invention is shown. The outline of the first conventional multiple inverter device and the flow path of the zero-phase current are shown. An outline of the second conventional multiple inverter device is shown. The outline of the second conventional multiple inverter device and the flow path of zero-phase current are shown. The outline | summary of the multiple inverter apparatus of this invention is shown. The outline | summary of the control circuit at the time of using the multiple inverter apparatus which is the 2nd Example of this invention for a reactive power control apparatus is shown. The outline | summary of the main circuit part of the 2nd Example of the multiple inverter apparatus of this invention is shown. The outline | summary of the control circuit of the 3rd Example of the multiple inverter apparatus of this invention is shown. The outline | summary of the main circuit part of the 3rd Example of the multiple inverter apparatus of this invention is shown. It is the circuit diagram which extracted a part of unit inverter of the 3rd Example of the multiple inverter apparatus of this invention. (A) The relationship between the dead time gate pulse when the output current of the unit inverter is positive and the voltage output by the unit inverter is shown. (B) The relationship between the dead time gate pulse when the output current of the unit inverter is negative and the voltage output by the unit inverter is shown. The relationship between each phase output current of the unit inverter and the zero phase current generated by the dead time is shown.

Explanation of symbols

1 to 4 unit inverters 11 to 14 DC capacitors 21 and 22 each of which is electrically insulated. Each phase AC output terminal of the unit inverter is at one end of the primary winding, and each phase of another unit inverter is at the other end. Open-winding transformer 31 to which an AC output terminal is connected Multiple inverter device 33 according to Embodiment 1 of the present invention Multiple inverter device 41 according to Embodiment 2 of the present invention Commercial AC power supply 51 to 54 PWM circuit 61 Implementation of the present invention Control circuit 62 for controlling the multiple inverter device according to Example 1 Control circuit 71 for controlling the multiple inverter device according to Example 2 of the present invention AC voltage detection circuit 72 AC current detection circuit 73 DC voltage detection circuits 81 and 82 Unit Inverter Pairs 101-104 Related to the First Embodiment Unit Inverter 11 Related to Multiple Inverter Devices of First and Second Conventional Examples DC capacitor 112 related to first conventional multiple inverter device 112 First DC capacitor 113 related to second conventional multiple inverter device Second DC capacitor 121, 122 related to second conventional multiple inverter device Open winding transformer 131 related to first and second conventional multiple inverter devices First conventional multiple inverter device 132 Second conventional multiple inverter devices 151 to 154 Second conventional multiple inverter PWM circuit 163 related to the device Control circuits 181 and 182 related to the third embodiment of the present invention Unit inverter pair 183 and 184 related to the multiple inverter device of the first conventional example The third embodiment and the first of the present invention Unit inverter pair 201 related to the conventional multiple inverter device DC of each unit inverter of the unit inverter pair Average DC voltage controller 202 that controls the average value of the pressure Polarity determination unit 203 that determines the polarity of the q-axis feedback current Q-axis individual DC that calculates the compensation voltage based on the deviation between the DC voltage of each unit inverter and the DC voltage command Voltage controller 204 D-axis individual DC voltage controller 205 that calculates a compensation voltage based on the deviation between the DC voltage of each unit inverter and the DC voltage command No-load state determination unit 211 that detects a no-load state Each unit of the inverter pair Average DC voltage control circuit 212 for controlling the average of the DC voltage of the inverter to a DC voltage command Individual DC voltage control circuit 301 for individually controlling the DC voltage of each unit inverter d-axis current command and q-axis current to be output by the unit inverter Current command calculator 302 for calculating a command Current for calculating a d-axis voltage command and a q-axis voltage command to be output by a unit inverter Controller 303 Coordinate converter 304 that performs three-phase two-phase conversion and dq conversion of the three-phase output current of the unit inverter Phase adjuster 305 that reverses the phase by 180 degrees Inverse coordinates that perform known inverse dq conversion and two-phase three-phase conversion Converter 311 Vector controller 401 Polarity determination unit 402 for determining the polarity of each phase output current of the unit inverter Compensation voltage calculator 403 that outputs a compensation voltage in accordance with the dead time length, carrier cycle and DC voltage Zero phase current controller 411 for outputting compensation voltage according to zero phase current Dead time compensation circuit 412 for compensating zero phase voltage due to dead time Zero phase current suppressing circuit 501 for suppressing zero phase current P-side IGBT
502 N-side IGBT

Claims (6)

It has two or more unit inverters and a transformer,
In the inverter device in which the two or more unit inverters are connected in parallel on the secondary side of the transformer,
The unit inverter converts a DC voltage of a DC capacitor into a three-phase AC voltage by a self-extinguishing element,
The transformer is an open delta transformer whose primary winding is an open delta connection;
Of the two or more unit inverters constituting the inverter device, two unit inverters and the transformer have one of the unit inverters at one end of the primary winding of the transformer and the other end. Is connected to the other of the unit inverters,
The DC capacitors of the two unit inverters are insulated from each other,
In the inverter device for individually controlling the DC voltage of the DC capacitor,
An average DC voltage control function for controlling the average value of each DC capacitor of the two unit inverters according to a DC voltage command;
An inverter device comprising an individual DC voltage control function for individually controlling a DC voltage in response to the DC voltage command . It has two or more unit inverters and a transformer,
In the inverter device in which the two or more unit inverters are connected in parallel on the secondary side of the transformer,
The unit inverter converts a DC voltage of a DC capacitor into a three-phase AC voltage by a self-extinguishing element,
The transformer is an open delta transformer whose primary winding is an open delta connection;
Of the two or more unit inverters constituting the inverter device, two unit inverters and the transformer have one of the unit inverters at one end of the primary winding of the transformer and the other end. Is connected to the other of the unit inverters,
The DC capacitors of the two unit inverters are insulated from each other,
In the inverter device for individually controlling the DC voltage of the DC capacitor,
An inverter device that controls the voltage of each DC capacitor of the two unit inverters in accordance with an average of the voltages of the DC capacitors of the two unit inverters . It has two or more unit inverters and a transformer,
In the inverter device in which the two or more unit inverters are connected in parallel on the secondary side of the transformer,
The unit inverter converts a DC voltage of a DC capacitor into a three-phase AC voltage by a self-extinguishing element,
The transformer is an open delta transformer whose primary winding is an open delta connection;
Of the two or more unit inverters constituting the inverter device, two unit inverters and the transformer have one of the unit inverters at one end of the primary winding of the transformer and the other end. Is connected to the other of the unit inverters,
The DC capacitors of the two unit inverters are insulated from each other,
In the inverter device for individually controlling the DC voltage of the DC capacitor,
The control circuit that controls the output voltage of each unit inverter is the output voltage of each unit inverter.
And a rotational coordinate control system on the d-axis and q-axis for controlling the current,
The control circuit includes a vector control arithmetic unit and an individual DC voltage control circuit,
The vector control arithmetic unit receives a reactive power command to be output by each unit inverter and an active power command, and calculates a d-axis current command and a q-axis current command to be output by each unit inverter. And
A three-phase output current common to the two unit inverters, three-phase two-phase conversion and dq coordinate conversion, and a coordinate converter that outputs a feedback d-axis current and a feedback q-axis current;
Current control for calculating a d-axis voltage command and a q-axis voltage command to be output by each unit inverter, using the d-axis current command, the q-axis current command, the feedback d-axis current, and the feedback q-axis current as inputs. And
A phase adjuster that reverses the phase of the d-axis voltage command and the q-axis voltage command by 180 °;
an inverse coordinate converter that performs dq inverse transformation and two-phase three-phase transformation, and calculates a three-phase output voltage command of each unit inverter,
The individual DC voltage control circuit calculates a compensation voltage according to the deviation between the DC voltage of each DC capacitor of each unit inverter and the DC voltage command and the polarity of the feedback q-axis current, and the reactive power command When the magnitude is larger than the magnitude of the active power command, the compensation voltage is added to the q-axis voltage command to reduce the deviation between the DC voltages of the two unit inverters and the DC voltage command. An inverter device characterized by that. In the inverter device according to claim 3,
Output a compensation voltage according to the deviation between each DC voltage and the DC voltage command of the two unit inverters ,
When the magnitude of the reactive power command is larger than the magnitude of the active power command by adding the compensation voltage to the d-axis voltage command, the DC voltage and the DC voltage command of the two unit inverters An inverter device characterized in that the deviation is reduced . It has two or more unit inverters and a transformer,
In the inverter device in which the two or more unit inverters are connected in parallel on the secondary side of the transformer,
The unit inverter converts a DC voltage of a DC voltage source into a three-phase AC voltage by a self-extinguishing element,
The transformer is an open delta transformer in which a primary winding is an open delta connection, and two unit inverters of the two or more unit inverters and the transformer are arranged on the primary side of the transformer. One of the unit inverters is connected to one end of the winding, and the other of the unit inverters is connected to the other end,
A set of the two unit inverters is provided, and a plurality of sets are provided.
DC capacitors connected to the first unit inverters of the plurality of sets are connected to each other,
DC capacitors connected to the second unit inverters of the plurality of sets are connected to each other,
Outputting a compensation voltage having a reverse polarity to the zero-phase voltage generated by the dead time provided so that the DC capacitor of the unit inverter is not short-circuited by the DC. The zero-phase voltage is suppressed, and the dead time given to each unit inverter is reduced. A compensation voltage is calculated based on the length, the carrier cycle of each unit inverter, and the polarity of each phase output current output from each unit inverter, and the compensation voltage is added to each phase voltage command of each unit inverter. Thus , the inverter device is characterized in that the zero-phase voltage generated by each unit inverter is suppressed . It has two or more unit inverters and a transformer,
In the inverter device in which the two or more unit inverters are connected in parallel on the secondary side of the transformer,
The unit inverter converts a DC voltage of a DC voltage source into a three-phase AC voltage by a self-extinguishing element,
The transformer is an open delta transformer whose primary winding is an open delta connection;
Of the two or more unit inverters, two unit inverters and the transformer have one of the unit inverters at one end of the primary winding of the transformer and the other unit inverter at the other end. The other is connected,
A set of the two unit inverters is provided, and a plurality of sets are provided.
DC capacitors connected to the first unit inverters of the plurality of sets are connected to each other ,
DC capacitors connected to the second unit inverters of the plurality of sets are connected to each other ,
Output the compensation voltage of the opposite polarity to the zero phase voltage generated by the dead time provided so that the DC capacitor of the unit inverter is not short-circuited DC, to suppress the zero phase voltage,
The dead time compensation function is:
A polarity determiner that determines the polarity of each phase output current output by each unit inverter;
A compensation voltage calculator for calculating a compensation voltage determined from a known dead time length given to each unit inverter and a carrier cycle of each unit inverter;
An inverter device characterized in that a zero-phase current flowing through each unit inverter is suppressed by adding or subtracting the compensation voltage to each phase voltage command of each unit inverter.

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