JP2017022882A - Power conversion device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a compact power conversion device at low cost with a reduced harmonic.SOLUTION: A high voltage inverter group, a middle voltage inverter group and a three-phase full-bridge inverter constitute a main circuit. A controller is provided to generate a control signal of the high voltage inverter group, the middle voltage inverter group and the three-phase full-bridge inverter so that an average composite voltage vector in a predetermined period among a high voltage vector, which is the output voltage vector of the high voltage inverter group, a middle voltage vector, which is the output voltage vector of the middle voltage inverter group, and a low voltage vector, which is the output voltage vector of the three-phase full-bridge inverter becomes a command voltage vector.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a high-voltage power converter, and more particularly to a reactive power compensator.

  As a conventional reactive power compensator, there is one disclosed in Patent Document 1, and its main circuit has the configuration shown in FIG. The U-phase high-voltage DC voltage source 13 has a U-phase high-voltage single-phase full-bridge inverter 10 having a U-phase output terminal, and the V-phase high-voltage DC voltage source 14 has a V-phase high-voltage single-phase full-bridge inverter 11 having a V-phase output terminal. A high-voltage inverter group 19 composed of a W-phase high-voltage single-phase full-bridge inverter 12 having a W-phase output terminal in a W-phase high-voltage DC voltage source 15, and a U-phase intermediate pressure having a U-phase output terminal in a U-phase medium-voltage DC voltage source 23 Single phase full bridge inverter 20 and V phase medium voltage DC voltage source 24 have V phase output terminal V phase medium voltage single phase full bridge inverter 21 and W phase medium voltage DC voltage source 25 have W phase output terminal W phase A medium-voltage inverter group 29 composed of medium-pressure single-phase full-bridge inverters 22, a U-phase low-voltage single-phase full-bridge inverter 30 having a U-phase output terminal and a V-phase low-voltage DC voltage source 34. It consists of a V-phase low-voltage single-phase full-bridge inverter 31 having a phase output terminal and a low-voltage inverter group 39 including a W-phase low-voltage single-phase full-bridge inverter 32 having a W-phase output terminal with a W-phase low-voltage DC voltage source 35. The voltage sources 13 to 15, 23 to 25, and 33 to 35 are capacitors. The output of each phase full bridge inverter (U phase is 10, 20, 30; V phase is 11, 21, 31; W phase is 12, 22, 32) is connected in series. The other is short-circuited and the other is connected to the system via reactors 40-42.

  The U-phase high-voltage DC voltage source 13, the V-phase high-voltage DC voltage source 14, and the W-phase high-voltage DC voltage source 15 are set to a common VH, and the U-phase medium-voltage DC voltage source 23, the V-phase medium-voltage DC voltage source 24, and W When the voltage of the phase intermediate voltage DC voltage source 25 is a common VM and the voltages of the U phase low voltage DC voltage source 33, the V phase low voltage DC voltage source 34, and the W phase low voltage DC voltage source 35 are a common VL, Patent Document 1 In

VM ≦ 2 · VL Formula 1
VH ≦ 3 ・ VM Formula 2

With this relationship, the output voltages Vu, Vv, and Vw can be made to follow a sinusoidal command. For example, when the system voltage effective value is 7.26 kV which is 1.1 times 6.6 kV in consideration of fluctuations, the maximum value of the phase voltage is 5.928 kV which is 2/3 times the square root of the system voltage effective value. Therefore, when the minimum voltage satisfying Expressions 1 and 2 is obtained, VL = 0.659 kV, VM = 1.318 kV, and VH = 3.952 kV.

  By doing in this way, the voltage width of one step of the stepped waveform of the output voltage of each phase can be set to the low voltage VL, and the switching frequency of the high voltage inverter group 19 and the intermediate voltage inverter group 29 is minimized. Since the peak value of the harmonic component of the voltage applied to the reactor can be lowered and the frequency can be increased simply by increasing the switching frequency of the low-voltage inverter group 39 in the lowered state, the harmonic component of the current flowing through the reactor can be reduced. .

JP 2012-175848 A

  If the maximum output voltage of the converter is determined, the voltage of each DC voltage source is automatically determined under the conditions of Equations 1 and 2, so the voltage of the low-voltage DC voltage source cannot be lowered. Therefore, in order to reduce the harmonic component of the current flowing through the reactors 40 to 42, it is necessary to increase the switching frequency or the reactor value, resulting in a reduction in efficiency, an increase in cost, and an increase in volume and weight.

  For the same reason, since the voltage of each DC voltage source is determined, the withstand voltage of the switching element to be applied is uniquely determined. Therefore, it becomes impossible to reduce the size and cost of the apparatus by selecting the switching element.

  Since current flows through six switching elements per phase, the efficiency is poor.

  In order to solve the above problems, the present invention has a configuration in which a three-phase full-bridge inverter of a low-voltage DC voltage source is connected in place of the low-voltage inverter group 39 having the configuration of FIG.

  In the invention according to claim 2, the high voltage vector that is the output voltage vector of the high voltage inverter group, the medium voltage vector that is the output voltage vector of the medium voltage inverter group, and the output voltage vector of the three-phase full-bridge inverter. A controller that generates control signals for the high-voltage inverter group, the intermediate-voltage inverter group, and the three-phase full-bridge inverter so that an average combined voltage vector with a certain low-voltage voltage vector for a predetermined period becomes a command voltage vector; Yes.

  In the invention according to claim 3, in the same configuration as in FIG. 2, a high voltage vector that is an output voltage vector of the high voltage inverter group, an intermediate voltage vector that is an output voltage vector of the medium voltage inverter group, and the low voltage inverter group A controller that generates control signals for the high-voltage inverter group, the intermediate-voltage inverter group, and the low-voltage inverter group so that an average combined voltage vector for a predetermined period with a low-voltage voltage vector that is an output voltage vector of the output voltage vector becomes a command voltage vector It has.

  In the invention according to claim 4, in the power converter of claim 1 or 2, the voltages of the U-phase high-voltage DC voltage source, the V-phase high-voltage DC voltage source, and the W-phase high-voltage DC voltage source are set to a common VH. When the voltage of the U-phase medium voltage DC voltage source, the V phase medium voltage DC voltage source, and the W phase medium voltage DC voltage source is a common VM, and the voltage of the low voltage DC voltage source is VL,

VM ≦ 1.5 ・ VL Formula 3
VH ≦ 3 ・ VM + 1.5 ・ VL Formula 4

It is characterized by.

  According to a fifth aspect of the present invention, in the power conversion device of the third aspect, the voltages of the U-phase high-voltage DC voltage source, the V-phase high-voltage DC voltage source, and the W-phase high-voltage DC voltage source are set to a common VH, The U-phase medium-voltage DC voltage source, the V-phase medium-voltage DC voltage source, and the W-phase medium-voltage DC voltage source are set to a common VM, and the U-phase low-voltage DC voltage source, the V-phase low-voltage DC voltage source, and the When the voltage of the W-phase low-voltage DC voltage source is a common VL,

VM = VL Formula 5
VH ≦ 6 ・ VL Formula 6

It is characterized by.

  Further, in the invention according to claim 6, in the power conversion device according to claim 3, the voltages of the U-phase high-voltage DC voltage source, the V-phase high-voltage DC voltage source, and the W-phase high-voltage DC voltage source are set to a common VH, The U-phase medium-voltage DC voltage source, the V-phase medium-voltage DC voltage source, and the W-phase medium-voltage DC voltage source are set to a common VM, and the U-phase low-voltage DC voltage source, the V-phase low-voltage DC voltage source, and the When the voltage of the W-phase low-voltage DC voltage source is a common VL,

VM ≦ 3 · VL Equation 7
VH ≦ 3 · (VM + VL) Equation 8

It is characterized by.

  In the invention according to claim 7, in the controller of the power conversion device according to claim 2, the one closest to the command voltage vector is selected from 19 types of high voltage vectors and is set as VHS as the high voltage inverter group. Outputs the VHS, obtains an intermediate voltage difference vector which is a difference between the VHS and the command voltage vector, and selects a medium voltage vector closest to the intermediate voltage difference vector from 19 kinds of intermediate voltage vectors. The medium voltage inverter group outputs the VMS as VMS, obtains a low voltage difference vector which is a difference between the VMS and the medium voltage difference vector, and within a predetermined period of the output of the three-phase full bridge inverter. The average voltage vector is set to the low voltage difference vector.

  In the invention according to claim 8, in the controller of the power conversion device according to claim 3 under the condition of claim 5, the one closest to the command voltage vector is selected from 19 kinds of high voltage vectors and is used. The high voltage inverter group outputs the VHS as VHS, an intermediate voltage difference vector which is a difference between the VHS and the command voltage vector is obtained, an average voltage vector of the intermediate voltage inverter group output within a predetermined period, An average voltage vector within a predetermined period of the low-voltage inverter group output is set to be half of the medium voltage difference vector.

  In the invention according to claim 9, in the controller of the power conversion device according to claim 3 under the condition of claim 6, the closest one to the command voltage vector is selected from 19 types of high voltage vectors and is used. As the VHS, the high-voltage inverter group outputs the VHS, and obtains an intermediate voltage difference vector which is a difference between the VHS and the command voltage vector, and changes the medium voltage difference vector from 19 types of intermediate voltage vectors. The closest one is selected as VMS so that the medium voltage inverter group outputs the VMS, a low voltage difference vector which is a difference between the VMS and the medium voltage difference vector is obtained, and the low voltage inverter group output The average voltage vector within a predetermined period is set to the low voltage difference vector.

  According to a tenth aspect of the present invention, when the power converter according to any one of the first to ninth aspects is applied to a self-excited reactive power compensator linked to a three-phase AC power system, each phase high-voltage DC The voltage source, each phase medium-voltage DC voltage source, each phase low-voltage DC voltage source, or the low-voltage DC voltage source is constituted by a capacitor, respectively.

  In the invention according to claim 11, in the controller of the power converter according to claim 10, the unit sine wave GU of the U-phase current, the unit sine wave GV of the V-phase current and the unit sine of the W-phase current obtained from the current command. A wave GW is obtained, a U phase high voltage error correction voltage is obtained from the product of the difference between the voltage of the U phase high voltage DC voltage source and the high voltage command and the GU, and the voltage of the V phase high voltage DC voltage source and the high voltage A V-phase high-voltage error correction voltage is obtained from the product of the difference between the command and the GW, and a W-phase high-voltage error correction voltage is calculated from the product of the difference between the voltage of the W-phase high-voltage DC voltage source and the high-voltage voltage command and the GW. A high-voltage error correction voltage vector is obtained from the U-phase high-voltage error correction voltage, the V-phase high-voltage error correction voltage, and the W-phase high-voltage error correction voltage, and the high-voltage inverter group is selected from 19 types of high-voltage voltage vectors. When outputting the command voltage 10. In the controller of the power converter according to claim 10, the vector of the sum of the command voltage vector and a predetermined gain multiple of the high-voltage error correction voltage vector is used instead of the torque. A U phase intermediate voltage error correction voltage is obtained from the product of the difference between the voltage of the DC voltage source and the medium voltage command and the GU, and the difference between the voltage of the V phase medium voltage DC voltage source and the medium voltage command The V-phase medium pressure error correction voltage is obtained from the product of GW and the GV, and the W-phase medium pressure error correction voltage is calculated from the product of the difference between the voltage of the W-phase medium voltage DC voltage source and the medium voltage command and the GW. An intermediate pressure error correction voltage vector is obtained from the U-phase intermediate pressure error correction voltage, the V-phase intermediate pressure error correction voltage, and the W-phase intermediate pressure error correction voltage. The medium voltage difference vector when the medium voltage inverter group selectively outputs. Characterized by using the vector of the sum of the predetermined gain multiple in said pressure error correction voltage vector and the medium voltage difference vector instead.

  According to the invention of claim 1, the number of switching elements per phase is reduced to five, so that the efficiency is improved. In addition, since a module containing six switching elements can be used, the apparatus can be reduced in size and cost.

  By performing voltage vector processing in the inventions of claims 2 and 3, the voltage range that can be output by the power converter is clarified, whereby the voltage of the voltage source corresponding to the breakdown voltage of the element as shown in claims 4 to 6 is obtained. It can be seen that can be selected. As a result, in claim 5, since the voltages of the medium voltage inverter group and the low voltage inverter group are the same and low voltage, a module containing six switching elements can be used, and the size and cost of the apparatus can be reduced. Become. Further, in claim 6, since the voltage of the low-voltage inverter group can be further lowered, the harmonic component of the reactor current can be reduced without increasing the switching frequency and the reactor value.

  According to the inventions of claims 7 to 9, in the configurations and voltages of claims 4 to 6, the switching frequency of the high-voltage inverter group and the intermediate-voltage inverter group can be minimized as in the conventional case, thereby reducing the efficiency. Does not occur.

  According to the tenth and eleventh aspects of the present invention, each phase DC voltage source can be a capacitor as in the prior art, and the voltage of the capacitor can be maintained at a predetermined value. Therefore, a DC power source such as an auxiliary power source is connected. There is no need.

It is a main circuit block diagram of an example at the time of applying the power converter device of Claim 1, 2, 4, 7 to a reactive power compensation apparatus. It is a main circuit block diagram of an example at the time of applying the power converter device of Claim 3, 5, 6, 8, 9 to a reactive power compensator, or the reactive power compensator of a prior art. It is an output voltage vector of a high-voltage inverter group, a medium-voltage inverter group, or a low-voltage inverter group. FIG. 2 is a first example of a relationship diagram among a high voltage vector, an intermediate voltage vector, a low voltage vector, and a combined voltage vector. It is the example 2 of a related figure of a high voltage vector, an intermediate voltage vector, a low voltage vector, and a synthetic voltage vector. FIG. 6 is a third example of a relationship diagram among a high voltage vector, an intermediate voltage vector, a low voltage vector, and a combined voltage vector. FIG. 14 is a fourth example of a relationship diagram among a high voltage vector, an intermediate voltage vector, a low voltage vector, and a combined voltage vector. FIG. 10 is a fifth example of a relationship diagram among a high voltage vector, an intermediate voltage vector, a low voltage vector, and a combined voltage vector. It is an example of the control block diagram at the time of applying a power converter device to a reactive power compensator. FIG. 10 is a block diagram illustrating a controller according to claims 7 and 9. It is a block diagram showing the controller of Claim 8. It is a block diagram which calculates | requires a high voltage error correction voltage vector and a medium voltage error correction voltage vector. FIG. 10 is a block diagram showing a controller according to claim 7 and 9, wherein the DC voltage source is a capacitor. It is a block diagram showing the controller in Claim 8 which used the direct-current voltage source as the capacitor | condenser.

  Hereinafter, a detailed description will be given based on an example of the embodiment.

  FIG. 1 shows a main circuit configuration when the power conversion device according to claim 1 is applied to a reactive power compensation device. U-phase high-voltage single-phase full-bridge inverter 10 having a U-phase output terminal at U-phase high-voltage DC voltage source 13 and V-phase high-voltage single-phase full-bridge inverter 11 having a V-phase output terminal at V-phase high-voltage DC voltage source 14 and W-phase A high-voltage inverter group 19 comprising a W-phase high-voltage single-phase full-bridge inverter 12 having a W-phase output terminal at a high-voltage DC voltage source 15 and a U-phase medium-voltage single-phase having a U-phase output terminal at a U-phase medium-voltage DC voltage source 23 A full-phase inverter 20 and a V-phase medium-voltage DC voltage source 24 have a V-phase output terminal. A V-phase medium-voltage single-phase full-bridge inverter 21 and a W-phase medium-voltage DC voltage source 25 have a W-phase output terminal. The medium-voltage inverter group 29 composed of the single-phase full-bridge inverter 22 and the three-phase full-bridge inverter 36 of the low-voltage DC voltage source 37 are configured. The U-phase output terminal of the data group 29 and the U-phase output terminal of the high-voltage inverter group 19 are connected in series, the V-phase terminal of the three-phase full-bridge inverter 36, the V-phase output terminal of the intermediate-voltage inverter group 29, and the high-voltage inverter group. 19 V-phase output terminals are connected in series, and a W-phase terminal of the three-phase full-bridge inverter 36, a W-phase output terminal of the medium-voltage inverter group 29, and a W-phase output terminal of the high-voltage inverter group 19 are connected in series. .

  Each phase output voltage of the high-voltage inverter group 19 is VuH, VvH, VwH, each phase output voltage of the medium-voltage inverter group 29 is VuM, VvM, VwM, respectively, and each phase output voltage of the three-phase full-bridge inverter 36 is respectively Assuming VuL, VvL, and VwL, the output voltage of each phase of the entire power converter is

Vu = VuH + VuM + VuL Equation 9
Vv = VvH + VvM + VvL Equation 10
Vw = VwH + VwM + VwL Equation 11

It becomes. When the axis that coincides with the U phase is the α axis, the axis orthogonal to it is the β axis, and Vu, Vv, and Vw are converted into voltage vectors of the αβ coordinate axis, each component is

It can be expressed. here

Therefore, VαH and VβH are components of a high voltage vector that is an output voltage vector of the high voltage inverter group 19, VαM and VβM are components of an intermediate voltage vector that is an output voltage vector of the medium voltage inverter group 29, and VαL and It is obvious that VβL is a component of the low voltage vector that is the output voltage vector of the three-phase full bridge inverter 36. From the above, it can be seen that the output voltage vector of the entire power conversion device can be expressed by the combination of the high voltage vector, the medium voltage vector, and the low voltage vector.

  Each phase output voltage of the high-voltage inverter group 19 and the medium-voltage inverter group 29 is a value obtained by multiplying the DC power supply voltage by one of −1, 0, and 1. It is represented by 19 black circles shown in FIG. The numerical values in parentheses shown in the figure represent the polarity of the output voltage of each phase in the order of U, V, and W phases from the left.

  4 to 8 show a part of the output voltage vector space of the entire power converter. White circles represent the vertices of the high voltage vector, dashed hexagonal black dots represent the vertices of the medium voltage vector from the center, and solid hexagons represent the range of the low voltage vector from the center. The three-phase full-bridge inverter 36 can output all voltage vectors in a solid hexagon as an average value within a predetermined time by PWM control. As shown in the figure, a high voltage vector, a medium voltage vector, and a low voltage vector are combined (added) by drawing a medium voltage vector around a white circle and drawing a low voltage vector around that black dot. A voltage vector can be represented, which becomes the output voltage vector of the entire power converter.

  The conditions for allowing the combined voltage vector to occupy the space of the high voltage vector within the range indicated by the one-dot chain line in FIGS. 4 to 8 without any gap are the high voltage vector, the medium voltage vector, and the low voltage vector. If the maximum length of each is VHx, VMx, VLx, the following is obtained.

VMx ≦ 3 · VLx Equation 15
VHx ≦ 3 · (VMx + VLx) Equation 16

  Next, in FIGS. 4-8, the maximum voltage Vmax which a power converter device can output in all the voltage phases is calculated | required. This is the radius of the inscribed circle in the area where the composite voltage vector can be output, and is represented by the distance from the origin to the star in FIGS. When VHx> 3VMx and VHx-3 · VMx−2 · VLx ≧ 0, this is expressed in FIG. When VHx> 3VMx and VHx−3 · VMx−2 · VLx <0 and VMx + 6 · VLx−VHx ≧ 0, Vmax is the smaller of Equations 17 and 18. When VHx> 3VMx and VHx−3 · VMx−2 · VLx <0 and VMx + 6 · VLx−VHx <0, Vmax is expressed by Equation 19. When VHx ≦ 3VMx and VMx <2 · VLx, Vmax is expressed by Expression 17, and when VHx ≦ 3VMx and VMx ≧ 2 · VLx, Vmax is expressed by Expression 20 and Vmax is expressed by Expression 20.

  In the main circuit configuration of FIG. 1, the voltage of the DC voltage source of each phase of the high-voltage inverter group 19 is common VH, the voltage of the DC voltage source of each phase of the medium-voltage inverter group 29 is common VM, and three phases When the voltage of the DC voltage source 37 of the full bridge inverter 36 is VL, the relationship between VHx, VMx, and VLx is expressed by Expression 21 and Expression 22. When Expression 21 and Expression 22 are substituted into Expression 15 and Expression 16, Expression 3 and Expression 4 are obtained.

  FIG. 4 shows a vector relationship diagram when Expression 15 or Expression 16 is expressed by an equal sign, and Vmax is obtained by Expression 17. For example, when the effective value of the system voltage is 7.26 kV which is 1.1 times 6.6 kV in consideration of the fluctuation, VHx, VMx, and VLx are obtained from Equations 15, 16 and 17 of the equal sign. From Equations 21 and 22, VH = 4.271 kV, VM = 1.068 kV, and VL = 0.712 kV. Therefore, it is possible to use a module with six elements having a withstand voltage of 1200 V that is widely available on the market as the three-phase full-bridge inverter 36, and the power converter can be reduced in size and cost. Compared with the conventional configuration shown in FIG. 2, the number of switching elements is reduced from 6 to 5, so that the conduction loss of the elements can be reduced and the efficiency is improved.

  FIG. 10 shows a controller for obtaining an output voltage corresponding to the command voltage vector (Vαr, Vβr) in the power conversion device of FIG. A voltage vector closest to the command voltage vector (Vαr, Vβr) is selected from the 19 types of voltage vectors in the DC power supply voltage command VHr of the high-voltage inverter group 19 and is output as VHS. That is, a switching signal corresponding to the selected voltage vector is output. Next, an intermediate voltage difference vector (VαMr, VβMr) that is a difference between VHS and the command voltage vector is obtained, and an intermediate voltage difference vector is selected from 19 types of voltage vectors in the DC power supply voltage command VMr of the medium voltage inverter group 29. The medium pressure vector selector 71 selects the one closest to (VαMr, VβMr) and outputs it as VMS. That is, a switching signal corresponding to the selected voltage vector is output. Finally, a low voltage difference vector (VαLr, VβLr) that is a difference between VMS and a medium voltage difference vector (VαMr, VβMr) is obtained, and an average output voltage within a predetermined period is obtained by PWM control of the three-phase full bridge inverter 36. A switching signal such that the vector becomes a low voltage difference vector (VαLr, VβLr) is output from the low voltage three-phase bridge PWM generator 73. As a specific means example, a switching signal can be obtained by expanding low voltage difference vectors (VαLr, VβLr) into three-phase components and comparing them with triangular wave carriers.

  When the power conversion device is applied to the reactive power compensation device as shown in FIG. 1, it is not necessary to constantly output active power from the device, so that all the DC power sources in FIG. 1 can be configured with capacitors. . An example of a control block diagram of the reactive power compensator is shown in FIG. The system voltage (Vsα, Vsβ) of the αβ coordinate axis detected by the system voltage detector 58 is converted into an effective voltage Vsd and an invalid voltage Vsq by the coordinate converter 59. The PLL 60 determines the voltage phase θ so that the reactive voltage becomes zero. The reactive current command Iqr is obtained by dividing the reactive power command Qr output from the reactive power finger generator 51 by the effective voltage Vsd. The effective current command Idr is obtained in the Vdc controller 61 by amplifying an error from the voltage command VLr of the DC voltage source of the three-phase full bridge inverter 36, for example. The currents (Iα, Iβ) flowing through the reactors 40 to 42 of the αβ coordinate axes detected by the current detector 56 are converted into coordinates by 57 by θ to become effective current Id and reactive current Iq. The voltage commands Vdr and Vqr are obtained by the current controller 53 so that they follow the commands. Those voltage commands are converted into voltage commands Vαr and Vβr of the αβ coordinate axis by the coordinate converter 54. As described above, the controller 55 outputs the switching signal of the power converter such that the output voltage of the power converter within the predetermined period becomes the voltage commands Vαr and Vβr.

  When all the DC power sources in FIG. 1 are configured with capacitors, control must be performed so that the voltage of each capacitor can be maintained at a predetermined value. Since the controller shown in FIG. 10 cannot do this, the controller shown in FIG. 13 is used. The voltage vector closest to the sum of the command voltage vector (Vαr, Vβr) and the high voltage error correction voltage vector (ΔVHα, ΔVHβ) is selected from the 19 types of voltage vectors in the DC power supply voltage command VHr of the high voltage inverter group 19. It selects with the selector 70 and outputs it as VHS. That is, a switching signal corresponding to the selected voltage vector is output. The high voltage error correction voltage vectors (ΔVHα, ΔVHβ) can be obtained from the block diagram of FIG. GU, GV, and GW, which are unit sine waves of each phase having a peak value 1 representing the phase current flowing through the reactors 40 to 42 from the active current command Idr, the reactive current command Iqr, and the voltage phase θ, are generated by the unit sine wave generator 80. Ask. This may be obtained from the detected current instead of from the current command. A U-phase high-voltage error correction voltage is obtained from the product of the difference between the voltage of the U-phase high-voltage DC voltage source 13 and the high-voltage voltage command VHr and the GU, and the difference between the voltage of the V-phase high-voltage DC voltage source 14 and VHr and the GV The V-phase high-voltage error correction voltage is obtained from the product of the GW and the W-phase high-voltage error correction voltage is obtained from the product of the difference between the voltage of the W-phase high-voltage DC voltage source 15 and VHr and the GW. The V-phase high-voltage error correction voltage and the W-phase high-voltage error correction voltage are converted into αβ-axis components by a three-phase two-phase converter 81 and multiplied by KH of a predetermined gain at 83 to obtain high-voltage error correction voltage vectors (ΔVHα, ΔVHβ). ) Can be obtained. By applying the correction by the high voltage error correction voltage vector, the switching timing of the high voltage inverter group can be shifted and the capacitor voltage of the DC voltage source of each phase of the high voltage inverter group can be brought close to the high voltage command VHr. For example, when the U-phase capacitor voltage is insufficient, the output of the U-phase single-phase full-bridge inverter is increased in the positive direction when the U-phase current is positive, and in the negative direction when the current is negative. Undervoltage can be reduced. However, it is almost meaningless to correct the output of the U-phase single-phase full-bridge inverter because the undervoltage can hardly be reduced when the current is near 0. Therefore, the U-phase high-voltage error correction voltage represents the output correction amount of the U-phase single-phase full-bridge inverter for correcting the deviation of the U-phase capacitor voltage from the command voltage. The same applies to the V phase and the W phase. By correcting the command voltage vector with the high voltage error correction voltage vector (ΔVHα, ΔVHβ) obtained by converting the high voltage error correction voltage of each phase into three phases and two phases, the capacitor voltage of each phase is corrected. Can be made close to the high voltage command VHr.

  Similarly, in FIG. 13, an intermediate voltage difference vector (VαMr, VβMr) and an intermediate voltage error correction voltage vector (ΔVMα, ΔVMβ) are selected from 19 types of voltage vectors in the DC power supply voltage command VMr of the intermediate voltage inverter group 29. The voltage vector closest to the sum is selected by the medium pressure vector selector 71 and is output as VMS. That is, a switching signal corresponding to the selected voltage vector is output. The intermediate pressure error correction voltage vectors (ΔVMα, ΔVMβ) can be obtained from the block diagram of FIG. 12 in the same manner as the high voltage error correction voltage vector. A U-phase intermediate voltage error correction voltage is obtained from the product of the difference between the voltage of the U-phase intermediate voltage DC voltage source 23 and the intermediate voltage command VMr and the GU, and the voltage of the V-phase intermediate voltage DC voltage source 24 and VMr are obtained. A V-phase intermediate pressure error correction voltage is obtained from the product of the difference and the GW, and a W-phase intermediate pressure error correction voltage is obtained from the product of the difference between the voltage of the W-phase intermediate voltage DC voltage source 25 and VMr and the GW. The U-phase intermediate pressure error correction voltage, the V-phase intermediate pressure error correction voltage, and the W-phase intermediate pressure error correction voltage are converted into αβ-axis components by a three-phase two-phase converter 82, and a predetermined gain is multiplied by KM at 84. The intermediate pressure error correction voltage vector (ΔVMα, ΔVMβ) can be obtained. By applying the correction based on the intermediate voltage error correction voltage vector, the voltage of the DC voltage source of each phase of the intermediate voltage inverter group can be made closer to the intermediate voltage command VMr by shifting the switching timing of the intermediate voltage inverter group.

  FIG. 2 shows a main circuit configuration when the power conversion device according to claim 5 is applied to the reactive power compensation device. Since this is the same diagram as the prior art, description thereof is omitted. The DC voltage source of each phase of the high voltage inverter group 19 is set to a common VH, the DC voltage source of each phase of the medium voltage inverter group 29 is set to a common VM, and the DC voltage source of each phase of the low voltage inverter group 39 is set. Assuming that the common voltage is VL, the relationship between VHx, VMx, and VLx is expressed by Expression 21 and Expression 23. Therefore, even if the relationship between VH, VM, and VL is expressed as Equations 5 and 6, Equations 15 and 16 can be satisfied, so that the high voltage vector that is the output voltage vector of the high voltage inverter group 19 and the output voltage of the medium voltage inverter group 29 are satisfied. The average composite voltage vector of the medium voltage vector that is a vector and the low voltage vector that is the output voltage vector of the low voltage inverter group 39 in a predetermined period is a high voltage vector that is within the range indicated by the one-dot chain line in FIGS. Can occupy the space without any gaps.

  The vector relationship diagram in the case of being expressed by Equation 5 or Equation 6 is also shown in FIG. 4, and Vmax is obtained by Equation 17. For example, when the Vmax is 7.26 kV, VH = 4.271 kV, VM = 0.712 kV, and VL = 0.712 kV. Therefore, it is possible to use modules with six elements with a withstand voltage of 1200 V that are widely available on the market as switching elements for the medium-voltage inverter group 29 and the low-voltage inverter group 39, and to reduce the size and cost of the power converter. Can do. At that time, the two switching elements in the module are not used.

  FIG. 11 shows a controller for obtaining an output voltage corresponding to the command voltage vector (Vαr, Vβr) in the power conversion device of FIG. 2 satisfying Equations 5 and 6. A voltage vector closest to the command voltage vector (Vαr, Vβr) is selected from the 19 types of voltage vectors in the DC power supply voltage command VHr of the high-voltage inverter group 19 and is output as VHS. That is, a switching signal corresponding to the selected voltage vector is output. Next, half of the difference between VHS and the command voltage vector is set as a medium voltage difference vector (VαMr, VβMr) and a low voltage difference vector (VαLr, VβLr). By PWM control of the medium voltage inverter group 29 and the low voltage inverter group 39, the average output voltage vector of each inverter group within a predetermined period is made to coincide with the respective commands (VαMr, VβMr) and (VαLr, VβLr). Switching signals are output from the PWM controllers 74 and 75, respectively.

  When all of the DC power sources shown in FIG. 2 satisfying Expressions 5 and 6 are composed of capacitors, the voltage of each capacitor must be controlled to be maintained at a predetermined value. Since the controller shown in FIG. 11 cannot do this, the controller shown in FIG. 14 is used. The voltage vector closest to the sum of the command voltage vector (Vαr, Vβr) and the high voltage error correction voltage vector (ΔVHα, ΔVHβ) is selected from the 19 types of voltage vectors in the DC power supply voltage command VHr of the high voltage inverter group 19. It selects with the selector 70 and outputs it as VHS. That is, a switching signal corresponding to the selected voltage vector is output. The high voltage error correction voltage vectors (ΔVHα, ΔVHβ) can be obtained from the block diagram of FIG. By applying the correction using the high voltage error correction voltage vector, the voltage of the DC voltage source of each phase of the high voltage inverter group can be brought close to the high voltage command VHr by shifting the switching timing of the high voltage inverter group. Next, half of the difference between VHS and the command voltage vector is set as a medium voltage difference vector (VαMr, VβMr) and a low voltage difference vector (VαLr, VβLr). By PWM control of the medium voltage inverter group 29 and the low voltage inverter group 39, the average output voltage vector of each inverter group within a predetermined period is made to coincide with the respective commands (VαMr, VβMr) and (VαLr, VβLr). Switching signals are output from the PWM controllers 74 and 75, respectively. At that time, it is necessary to devise a device for controlling the voltage of the capacitor which is a DC voltage source of the medium voltage inverter group 29 and the low voltage inverter group 39. For example, if a medium voltage difference vector (VαMr, VβMr) is converted into a three-phase carrier comparison value to obtain a PWM control switching signal by comparison with a triangular wave carrier, the above three-phase carrier comparison value conversion is performed. The required zero-phase potential may be the sum of the products of the phases of the error voltage of each phase capacitor and the unit sine wave depending on the current obtained in FIG.

  FIG. 2 shows a main circuit configuration when the power conversion device according to claim 6 is applied to the reactive power compensation device. Since this is the same diagram as the prior art, description thereof is omitted. The DC voltage source of each phase of the high voltage inverter group 19 is set to a common VH, the DC voltage source of each phase of the medium voltage inverter group 29 is set to a common VM, and the DC voltage source of each phase of the low voltage inverter group 39 is set. Assuming that the common voltage is VL, the relationship between VHx, VMx, and VLx is expressed by Expression 21 and Expression 23. Therefore, even if the relationship between VH, VM, and VL is expressed as Expressions 7 and 8, Expressions 15 and 16 can be satisfied. Therefore, the high voltage vector that is the output voltage vector of the high voltage inverter group 19 and the output voltage of the medium voltage inverter group 29 are satisfied. The average composite voltage vector of the medium voltage vector that is a vector and the low voltage vector that is the output voltage vector of the low voltage inverter group 39 in a predetermined period is a high voltage vector that is within the range indicated by the one-dot chain line in FIGS. Can occupy the space without any gaps.

  A vector relationship diagram in the case where Expression 7 and Expression 8 are expressed by an equal sign is also shown in FIG. 4, and Vmax is obtained by Expression 17. For example, when the Vmax is 7.26 kV, VH = 4.271 kV, VM = 1.068 kV, and VL = 0.356 kV. Therefore, it becomes possible to use a module containing six elements having a withstand voltage of 600 V, which is widely available on the market, as the switching elements of the low-voltage inverter group 39, and the power converter can be reduced in size and cost. In addition, since the voltage of the low-voltage inverter group can be reduced to about half that in the prior art, the harmonic component of the reactor current can be reduced without increasing the switching frequency and the reactor value.

  In the power conversion apparatus of FIG. 2 that satisfies Expressions 7 and 8, the controller for obtaining the output voltage corresponding to the command voltage vector (Vαr, Vβr) is the same as that of FIG. Further, when all the DC power sources in FIG. 2 satisfying Expressions 7 and 8 are constituted by capacitors, FIG. 13 is obtained instead of FIG. Since both figures have already been explained, the explanation here is omitted.

  By applying the power converter of the present invention to a reactive power compensator that is directly connected to a high-voltage power system, high efficiency, small size, and low cost can be achieved. In addition, there is an effect that harmonic components of the compensation current can be reduced.

40 to 42 Reactors 19 High-voltage inverter group 29 Medium-voltage inverter group 39 Low-voltage inverter group 36 Three-phase full-bridge inverter

Claims (11)

U-phase high-voltage single-phase full-bridge inverter with U-phase high-voltage DC voltage source and U-phase output terminal, V-phase high-voltage single-phase full-bridge inverter with V-phase high-voltage DC voltage source and V-phase output terminal, and W-phase high-voltage DC voltage source High-voltage inverter group consisting of W-phase high-voltage single-phase full-bridge inverter with W-phase output terminal, U-phase medium-voltage single-phase full-bridge inverter with U-phase output terminal and U-phase medium-voltage DC voltage source, and V-phase medium pressure Medium-voltage inverter group consisting of a V-phase medium-voltage single-phase full-bridge inverter with a DC voltage source and a V-phase output terminal, and a W-phase medium-voltage single-phase full-bridge inverter with a W-phase medium-voltage DC voltage source and a W-phase output terminal; A three-phase full-bridge inverter of a low-voltage DC voltage source, and a U-phase terminal of the three-phase full-bridge inverter, a U-phase output terminal of the medium-voltage inverter group, and a U-phase output terminal of the high-voltage inverter group are directly connected. A V-phase terminal of the three-phase full-bridge inverter, a V-phase output terminal of the medium-voltage inverter group, and a V-phase output terminal of the high-voltage inverter group are connected in series, and the W-phase of the three-phase full-bridge inverter A power converter in which a terminal, a W-phase output terminal of the medium-voltage inverter group, and a W-phase output terminal of the high-voltage inverter group are connected in series. The high voltage vector that is the output voltage vector of the high voltage inverter group, the medium voltage vector that is the output voltage vector of the medium voltage inverter group, and the low voltage vector that is the output voltage vector of the three-phase full-bridge inverter. The power converter according to claim 1, further comprising a controller that generates control signals for the high-voltage inverter group, the intermediate-voltage inverter group, and the three-phase full-bridge inverter so that an average combined voltage vector becomes a command voltage vector. U-phase high-voltage single-phase full-bridge inverter with U-phase high-voltage DC voltage source and U-phase output terminal, V-phase high-voltage single-phase full-bridge inverter with V-phase high-voltage DC voltage source and V-phase output terminal, and W-phase high-voltage DC voltage source A high-voltage inverter group consisting of a W-phase high-voltage single-phase full-bridge inverter having a W-phase output terminal;
U-phase medium-voltage single-phase full-bridge inverter with U-phase medium-voltage DC voltage source and U-phase output terminal V-phase medium-voltage single-phase full-bridge inverter with V-phase output terminal with V-phase medium-voltage DC voltage source and W-phase A medium-voltage inverter group consisting of a W-phase medium-voltage single-phase full-bridge inverter with a medium-voltage DC voltage source and a W-phase output terminal;
U-phase low-voltage DC voltage source with U-phase output terminal U-phase low-voltage single-phase full-bridge inverter and V-phase low-voltage DC voltage source with V-phase output terminal V-phase low-voltage single-phase full-bridge inverter and W-phase low-voltage DC voltage source And a low-voltage inverter group comprising a W-phase low-voltage single-phase full-bridge inverter having a W-phase output terminal, the U-phase output terminal of the low-voltage inverter group, the U-phase output terminal of the intermediate-voltage inverter group, and the high-voltage inverter group A U-phase output terminal of the low-voltage inverter group, a V-phase output terminal of the medium-voltage inverter group, and a V-phase output terminal of the high-voltage inverter group are connected in series. A W-phase output terminal of the group, a W-phase output terminal of the medium-voltage inverter group, and a W-phase output terminal of the high-voltage inverter group are connected in series, and the low-voltage inverter group or the high-voltage inverter The power converter according to other U-phase output terminal of the data group and the other of the V-phase output terminal and the other of the W-phase output terminal is short-circuited,
Average synthesis of a high voltage vector, which is an output voltage vector of the high voltage inverter group, an intermediate voltage vector, which is an output voltage vector of the medium voltage inverter group, and a low voltage vector, which is an output voltage vector of the low voltage inverter group, for a predetermined period A power converter comprising a controller that generates control signals for the high-voltage inverter group, the intermediate-voltage inverter group, and the low-voltage inverter group so that the voltage vector becomes a command voltage vector. The U-phase high-voltage DC voltage source, the V-phase high-voltage DC voltage source, and the W-phase high-voltage DC voltage source have a common voltage VH, and the U-phase medium-voltage DC voltage source, the V-phase medium-voltage DC voltage source, and the When the voltage of the W-phase medium voltage DC voltage source is a common VM and the voltage of the low voltage DC voltage source is VL,
VM ≦ 1.5 ・ VL
VH ≦ 3 ・ VM + 1.5 ・ VL
The power conversion device according to claim 2, wherein: The U-phase high-voltage DC voltage source, the V-phase high-voltage DC voltage source, and the W-phase high-voltage DC voltage source have a common voltage VH, and the U-phase medium-voltage DC voltage source, the V-phase medium-voltage DC voltage source, and the When the voltage of the W-phase medium-voltage DC voltage source is a common VM and the voltages of the U-phase low-voltage DC voltage source, the V-phase low-voltage DC voltage source, and the W-phase low-voltage DC voltage source are common VL,
VM = VL
VH ≦ 6 ・ VL
The power conversion device according to claim 3, wherein: The U-phase high-voltage DC voltage source, the V-phase high-voltage DC voltage source, and the W-phase high-voltage DC voltage source have a common voltage VH, and the U-phase medium-voltage DC voltage source, the V-phase medium-voltage DC voltage source, and the When the voltage of the W-phase medium-voltage DC voltage source is a common VM and the voltages of the U-phase low-voltage DC voltage source, the V-phase low-voltage DC voltage source, and the W-phase low-voltage DC voltage source are common VL,
VM ≦ 3 ・ VL
VH ≦ 3 ・ (VM + VL)
The power conversion device according to claim 3, wherein: 3. The controller according to claim 2, wherein a voltage closest to the command voltage vector is selected from 19 types of high voltage vectors, and is set as VHS so that the high voltage inverter group outputs the VHS, and the VHS is output. The intermediate voltage difference vector, which is the difference between the intermediate voltage difference vector and the command voltage vector, is selected from among 19 types of intermediate voltage vectors and the one closest to the intermediate voltage difference vector is used as VMS, and the intermediate voltage inverter group The VMS is output, a low voltage difference vector that is a difference between the VMS and the medium voltage difference vector is obtained, and an average voltage vector within a predetermined period of the three-phase full-bridge inverter output is the low voltage difference vector A power conversion device characterized by comprising: 5. The controller according to claim 5 or 3, wherein a voltage closest to the command voltage vector is selected from 19 types of high voltage vectors and is used as VHS so that the high voltage inverter group outputs the VHS. An intermediate voltage difference vector which is a difference between the VHS and the command voltage vector is obtained, and an average voltage vector within a predetermined period of the intermediate voltage inverter group output and an average voltage vector within a predetermined period of the low voltage inverter group output are obtained. A power conversion device characterized in that it is half of the medium voltage difference vector. 4. The controller according to claim 6 or 3, wherein the one that is closest to the command voltage vector is selected from the 19 types of high voltage vectors and is used as VHS so that the high voltage inverter group outputs the VHS. The medium voltage difference vector, which is the difference between the VHS and the command voltage vector, is obtained, and the closest one to the medium voltage difference vector is selected from 19 types of medium voltage vectors and is used as the VMS. A voltage inverter group that outputs the VMS, obtains a low voltage difference vector that is a difference between the VMS and the medium voltage difference vector, and an average voltage vector within a predetermined period of the low voltage inverter group output is the low voltage difference A power converter characterized by being a vector. When applied to a self-excited reactive power compensator linked to a three-phase AC power system, each phase high-voltage DC voltage source, each phase medium-voltage DC voltage source, each phase low-voltage DC voltage source, The power converter according to any one of claims 1 to 9, wherein each of the low-voltage DC voltage sources includes a capacitor. 11. The controller of claim 10, wherein a U-phase current unit sine wave GU, a V-phase current unit sine wave GV, and a W-phase current unit sine wave GW obtained from a current command are obtained, and the U-phase high-voltage DC voltage source is obtained. A U-phase high-voltage error correction voltage is obtained from the product of the difference between the voltage and the high-voltage command and the GU, and V is obtained from the product of the difference between the voltage of the V-phase high-voltage DC voltage source and the high-voltage command and the GV. A phase high voltage error correction voltage is obtained, a W phase high voltage error correction voltage is obtained from the product of the difference between the voltage of the W phase high voltage DC voltage source and the high voltage command and the GW, and the U phase high voltage error correction voltage and the A high-voltage error correction voltage vector obtained by multiplying a V-phase high-voltage error correction voltage and the W-phase high-voltage error correction voltage by a predetermined gain is obtained, and the command voltage vector is selected when the high-voltage inverter group selectively outputs from 19 types of high-voltage inverter vectors. Instead of the finger Using a vector of the sum of the high error correction voltage vector and the voltage vector,
The controller according to claim 7 or 9, wherein:
A U-phase medium voltage error correction voltage is obtained from the product of the difference between the voltage of the U-phase medium voltage DC voltage source and the medium voltage command and the GU, and the voltage of the V-phase medium voltage DC voltage source and the medium voltage A V-phase medium pressure error correction voltage is obtained from the product of the difference from the command and the GV, and the W-phase medium pressure error correction voltage is calculated from the product of the difference between the voltage of the W-phase medium voltage DC voltage source and the medium voltage command and the GW. A pressure error correction voltage is obtained, and an intermediate pressure error correction voltage vector obtained by multiplying the U phase intermediate pressure error correction voltage, the V phase intermediate pressure error correction voltage, and the W phase intermediate pressure error correction voltage by a predetermined gain is obtained. When the medium voltage inverter group selectively outputs from the medium voltage vectors, a vector of the sum of the medium voltage difference vector and the medium voltage error correction voltage vector is used instead of the medium voltage difference vector. To power converter.

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