JP2010220332A - Power converting device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To bypass the output of a faulty unit inverter and relatively easily continue operation with the remaining unit inverters. <P>SOLUTION: Each unit inverter 3 has a bypass means 34 for short-circuiting an output and its output voltage is controlled according to a voltage command from a voltage control means 5. The voltage control means 5 includes a voltage reference computation means 52 that computes a voltage reference based on a frequency command and a magnetic flux reference from a magnetic flux reference generating means 51, a voltage limit value computation means 53 that computes a voltage limit value for each phase according to the number of unit inverters whose bypass means 34 is in operation, a voltage limiting means 54 that limits the voltage reference for each phase obtained by the voltage reference computation means 52 by a voltage limit value of the voltage limit value computation means 53, an adding means 55 that adds the output for each phase of the voltage limiting means 54, and an adding means 56 that adds the output of the adding means 55 to the voltage reference for each phase obtained by the voltage reference computation means 52 and corrects it to obtain a voltage command. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a power converter, and more particularly to a power converter that has three phases of phase voltages obtained by connecting single-phase outputs of a plurality of unit inverters in series and drives a load such as an electric motor.

  A power converter that has three phases of phase voltage in which single-phase outputs of one or more unit inverters are connected in series and drives a load such as an electric motor is intended to increase the capacity and voltage of the device. Used to improve the waveform. In this power conversion device, it is desired to continue the operation in a state where the output of the unit inverter is bypassed and the utilization efficiency of the remaining unit inverters is increased when the unit inverter fails. Increasing the utilization efficiency of the remaining unit inverters means that the output voltages of the unit inverters other than the failed unit inverter can be effectively used without bypassing the outputs of the other two-phase unit inverters that match the failed unit inverter. This means that the voltage utilization rate is improved.

  In response to this requirement, with the phase voltage output maximum value limited, a method of keeping the phase difference of the line voltage at 120 ° by shifting the phase difference of each phase from 120 °, and the maximum and minimum values of each phase A method for correcting a voltage from a value is known (see Patent Document 1).

JP 2000-60142 A (Overall)

  In the conventional method of outputting the maximum voltage between lines shown in Patent Document 1, the phase difference of the line voltage is kept at 120 ° by shifting the phase difference of phase voltage from 120 °, and the three-phase balanced power is increased. Supply. However, in order to maintain the phase difference of 120 ° between the line voltages by shifting the phase voltage from 120 °, complicated calculation is required and the control circuit becomes complicated. Furthermore, in this method, the phase current also has a phase difference of 120 °, but the relationship between the phase voltage and the phase current may deviate from the normal range of 0 ° to 90 ° in the case of a light load. In this case, there is a possibility that the phase power will be in a regenerative state. If the unit inverter does not have a regenerative function, problems such as overvoltage abnormality occur.

  Accordingly, a first object of the present invention is to provide an output of a unit inverter when a unit inverter fails in a power converter that has a three-phase phase voltage in which one or more unit inverters are connected in series and drives a load such as an electric motor. Is to provide a power converter having a relatively simple control circuit for continuing the operation by increasing the utilization efficiency of the remaining unit inverter.

  A second object of the present invention is to provide a power conversion device that can continue operation with the remaining unit inverters so that each phase power is not regenerated.

  In order to achieve the first object, the power converter of the present invention is configured to connect a single-phase AC output of at least one unit inverter in series to form each phase, thereby converting a multi-phase AC power into a multi-phase AC motor. Each of the unit inverters has a bypass means for short-circuiting its output, and its instantaneous output voltage is controlled in accordance with an instantaneous voltage command given from the voltage control means. The means includes: a frequency command for driving the AC motor; a voltage reference calculating means for calculating a voltage reference for driving the AC motor based on a magnetic flux reference obtained from the magnetic flux reference generating means; and the unit inverter. Voltage limit value calculating means for calculating a voltage limit value for each phase according to the number of unit inverters in which the bypass means is operating; A voltage limit means for limiting the voltage reference of each phase obtained by the computing means with the voltage limit value of each phase obtained by the voltage limit value computing means, and a first for adding the outputs of each phase of the voltage limit means And second addition means for obtaining the instantaneous voltage command by adding and correcting the output of the first addition means for each phase voltage reference obtained by the voltage reference calculation means. It is characterized by comprising.

  According to the present invention, in a power converter that has a three-phase phase voltage in which one or more unit inverters are connected in series and drives a load such as an electric motor, when the unit inverter fails, the output of the unit inverter is bypassed, It becomes possible to provide a power conversion device having a relatively simple control circuit for increasing the utilization efficiency of the remaining unit inverter and continuing the operation.

The block block diagram of the power converter device which concerns on Example 1 of this invention. The internal block diagram of the unit inverter in the power converter device of this invention. FIG. 3 is an internal configuration diagram of a voltage control circuit according to the first embodiment. The voltage vector conceptual diagram before and after the failure of the unit inverter in Example 1. FIG. The voltage waveform example in the power converter device of this invention. The block block diagram of the power converter device which concerns on Example 2 of this invention. FIG. 10 is a characteristic diagram of an excitation reference circuit of the voltage control circuit in the second embodiment. The voltage and the example of a power waveform in Example 1 of this invention. The voltage and power waveform example in Example 2 of this invention.

  Hereinafter, embodiments of a power conversion device according to the present invention will be described with reference to the drawings.

  Hereinafter, the power converter concerning Example 1 of the present invention is explained with reference to Drawing 1 thru / or Drawing 5. FIG.

  FIG. 1 is a block diagram of a power conversion apparatus according to Embodiment 1 of the present invention. Three-phase AC power is supplied from a three-phase power source 1 to a transformer 2 having a plurality of windings on the secondary side. Three-phase AC power from a plurality of secondary windings of the transformer 2 is supplied to the unit inverters 3 (3U1, 3U2, 3U3, 3V1, 3V2, 3V3, 3W1, 3W2, 3W3), respectively. Single-phase outputs of unit inverters 3U1, 3U2, and 3U3, single-phase outputs of unit inverters 3V1, 3V2, and 3V3, and single-phase outputs of unit inverters 3W1, 3W2, and 3W3 are connected in series, respectively, so A phase voltage of the phase is formed, one of these series connection bodies is connected to each other as a neutral point, and the other is connected to the three-phase input terminal of the three-phase AC motor 4 to thereby connect the AC motor 4 to the three-phase AC Supply power.

In the voltage control circuit 5, which will be described in detail later, output voltage references Vu, Vv, Vw are determined so that the speed of the AC motor 4 becomes a predetermined speed, and this is output to the PWM control circuit 6. The PWM control circuit 6 generates a gate signal applied to the switching elements constituting each unit inverter so as to generate the output voltages Vu, Vv, Vw corresponding to the output voltage reference, and controls these switching elements on and off.
FIG. 2 is an internal configuration diagram of the unit inverter 3 shown in FIG. AC power from the secondary winding of the transformer 2 is converted to DC power by the diode rectifier circuit 31 and the DC smoothing capacitor 33, and further converted to single-phase AC having an arbitrary frequency and voltage by the single-phase inverter circuit 32. . The single-phase inverter circuit 32 is configured by bridge-connecting positive arms U and V and negative arms X and Y each having a switching element. An output short circuit 34 is provided at the output of each unit inverter. This output short circuit 34 stops the operation of the unit inverter when the unit inverter 3 fails, etc., and operates the apparatus by bypassing the output of the unit inverter by turning on the output short circuit 34. Used for.

  FIG. 3 is an internal block diagram of the voltage control circuit 5 of FIG. In order to drive the AC motor 4, the voltage control circuit 5 inputs a frequency reference f given from the outside and a magnetic flux reference φ set by the magnetic flux reference generation circuit 51 to the voltage reference calculator 52, for example. The AC motor 4 can generate a magnetic flux corresponding to the magnetic flux reference φ and obtains a voltage amplitude V * that is substantially proportional to the frequency reference f by calculation. The instantaneous output voltage references Vu1, Vv1, and Vw1 for each phase can be obtained by calculation using the following equations (1), (2), and (3), respectively. Here, t represents time.

Vu1 = V * × sin (2π × f × t) (1)
Vv1 = V * × sin (2π × f × t + 2π / 3) (2)
Vw1 = V * × sin (2π × f × t−2π / 3) (3)
In addition, the voltage limit value calculation circuit 53 that receives the number of failure cells in each phase obtained from the failure detection unit of each unit inverter (also referred to as a cell) not shown in the figure is calculated from the number of failure cells in each phase according to equation (4). The output voltage limit value of each phase is calculated, and the output voltage limit circuit 54 performs limit processing based on the output voltage reference of each phase. Here, the original voltage limit value is a voltage limit value when all the unit inverters of each phase are healthy.

Voltage limit value = original voltage limit value x
Number of healthy unit inverters / number of original unit inverters (4)
The three phases of the voltage subjected to the limit processing for each phase are added by the adder 55, and the addition value of the three phases is added as a voltage correction amount to the original voltage references Vu1, Vv1, and Vw1 by the adder 56. Voltage references (voltage commands) Vu, Vv, and Vw are output.

  The operation of the first embodiment will be described below with reference to FIGS.

  FIG. 4 shows a conceptual diagram of an output possible voltage vector for each phase when one of the V-phase unit inverters is bypassed. FIG. 4A shows a voltage vector before the failure, and single-phase AC outputs of three unit inverters are connected in series for each phase. A phase voltage is obtained as a device that is 120 ° out of phase with each other.

  FIG. 4B shows a vector diagram when one of the V-phase unit inverters, for example, the unit inverter 3V3 in FIG. As shown in the figure, the phase voltage of the V phase can output only 2/3 of the original phase voltage. Therefore, the voltage limit value according to the equation (4), that is, the output of the voltage limit value calculation circuit 53 is 2/3 of the original voltage limit value only for the V phase.

  Next, the operation of the voltage control circuit 5 in FIG. 3 in this state will be considered. When the original voltage references Vu1, Vv1, and Vw1 are all within 2/3 of the original voltage limit value, the output voltage limit circuit 54 does not reach the limit. Voltage references Vu1, Vv1, and Vw1 themselves. Therefore, the output of the adder 55 becomes zero, and the correction by the adder 56 is not performed.

On the other hand, when the original voltage references Vu1, Vv1, and Vw1 all exceed 2/3 of the original voltage limit value, the output voltage limit circuit 54 applies only Vv1 out of the three voltage references. A limit is applied and the peak of the sine wave is cut. At this time, the output of the adder 55 is obtained when the positive peak of the voltage reference Vv1 of the original sine wave is cut.
When the cut portion becomes negative and the negative peak is cut, the waveform becomes such that the cut portion becomes positive.

  FIG. 5 shows the voltage waveform of each part in the above state. FIG. 5A shows the phase voltages of the U phase, the V phase, and the W phase, that is, the corrected voltage references (voltage commands) Vu, Vv, and Vw in FIG. As shown in the figure, the phase voltage of the V phase, that is, the corrected voltage reference Vv is a voltage that is peak-cut by the limit value, and the other U-phase and W-phase phase voltages are added by the V-phase peak cut. 56 is added to obtain a slightly distorted waveform.

  On the other hand, FIG. 5B shows line voltages between UV, VW, and WU. As shown in the figure, sine waves whose phases are shifted from each other by 120 ° are secured as the line voltages. This is because the adder 56 gives the same correction command to each phase, so that the line voltage does not change between the input and output of the adder 56 even if the phase voltage changes. is there.

  According to the method of the first embodiment described above, when an arbitrary unit inverter fails, the output of the unit inverter can be bypassed, and the operation efficiency of the remaining unit inverters can be increased and the operation can be continued. There may be a plurality of unit inverters to be bypassed, and even if all unit inverters in a certain phase are bypassed, the same correction concept may be used. This indicates that the first embodiment is applicable even if the number of series unit inverters in each phase is one.

  Moreover, although both the power converter device of FIG. 1 and an alternating current motor have three phases, it is clear that not only three phases but many phases may be sufficient.

  FIG. 6 is an internal configuration diagram of the voltage control circuit 5A in the power conversion apparatus according to the second embodiment of the present invention. In the second embodiment, the same parts as those in the internal configuration diagram of the voltage control circuit 5 in the power conversion apparatus according to the first embodiment of the present invention shown in FIG. The second embodiment differs from the first embodiment in that the magnetic flux reference φ, which is the output of the magnetic flux reference generating circuit 51A, is used as a function of the load amount (load factor or load power) and the voltage limit value calculation circuit 53 for each phase. The minimum value calculation circuit 57 for obtaining the minimum value from the output of the current value is provided, and the magnetic flux reference circuit 51A is configured to determine the magnetic flux reference φ when the load amount is zero according to the output of the minimum value calculation circuit 57. is there.

  FIG. 7 shows an example of the characteristics of the magnetic flux reference generation circuit 51A. As shown in FIG. 7, when the load amount is smaller than a predetermined load factor, the magnetic flux reference φ is gradually lowered. The predetermined load factor is, for example, a load factor when a current corresponding to a no-load excitation current flows at a predetermined power factor as illustrated. Normally, when the magnetic flux reference is lowered, the voltage decreases in proportion to this and the effective current increases. However, in this embodiment, since the magnetic flux reference is lowered only when the load factor is low, there is no such influence.

  Further, the minimum value circuit 57 outputs the minimum value of the voltage limit value of each phase to the magnetic flux reference generation circuit 51A. The magnetic flux reference generation circuit 51A determines the magnetic flux reference φ based on the load amount and the minimum value of the voltage limit.

  In addition, what is necessary is just to obtain | require the load factor in this Example 2 for 3 phases totaling what multiplied each phase voltage and the instantaneous value of phase current, for example.

  The operation of the second embodiment will be described below with reference to FIGS.

  FIG. 8 is a waveform showing the instantaneous power of each phase when the power conversion device according to the first embodiment outputs the phase voltage of FIG. 5A, and FIG. 8A is when the power factor is 1 FIG. 8B shows a waveform when the power factor is zero. As shown in the figure, when the power factor is 1, the average power of all phases is positive and the power running operation is performed. On the other hand, when the power factor is 0, the average power of the U phase is less than 0, indicating that the regenerative operation is performed.

  In such a case, that is, when the power factor is low and the load factor is low, the magnetic flux reference generating circuit 51A having the characteristics shown in FIG. 7 of the present embodiment lowers the magnetic flux reference φ so that the voltage is lowered to a three-phase balanced voltage. Regenerative operation can be prevented. FIG. 9 shows the waveform of each part at this time, FIG. 9A shows the phase voltage, FIG. 9B shows the line voltage, and FIG. 9C shows the power waveform of each phase.

  According to this embodiment, when the load power applied to the AC motor is low, the output voltage is lowered by lowering the magnetic flux reference φ, and it is possible to operate in a region where the voltage limit of each phase does not operate. Also, the output voltage is not affected in the speed / voltage region where the voltage limit does not operate.

  In the second embodiment, the magnetic flux reference is reduced when the overall load factor is equal to or less than a predetermined load factor, but the minimum value of the output power of each phase is equal to or less than a predetermined value. When the magnetic flux reference is reduced, it is clear that the same effect can be obtained.

DESCRIPTION OF SYMBOLS 1 3 phase power supply 2 Transformer 3, 3U1, ..., 3W1 Unit inverter 4 AC motor 5, 5A Voltage control circuit 6 PWM control circuit 31 Diode rectifier circuit 32 Single phase inverter circuit 33 DC smoothing capacitor 34 Output short circuit 51 Magnetic flux Reference circuit 52 Voltage reference calculator 53 Voltage limit value calculation circuit 54 Output voltage limit circuit 55 Minimum value circuit

Claims (5)

In a power converter for supplying multi-phase AC power to a multi-phase AC motor by configuring each phase by connecting the single-phase AC output of at least one unit inverter in series,
Each of the unit inverters
In addition to having a bypass means for short-circuiting the output, the instantaneous output voltage is controlled according to the instantaneous voltage command given from the voltage control means,
The voltage control means includes
Voltage reference calculating means for calculating a voltage reference for driving the AC motor based on a frequency command for driving the AC motor and a magnetic flux reference obtained from a magnetic flux reference generating means,
Among the unit inverters, a voltage limit value calculating unit that calculates a voltage limit value for each phase according to the number of unit inverters in which the bypass unit is operating,
Voltage limiting means for limiting the voltage reference of each phase obtained by the voltage reference calculating means with the voltage limit value of each phase obtained by the voltage limit value calculating means;
First addition means for adding the output of each phase of the voltage limit means;
Second addition means for obtaining the instantaneous voltage command by adding and correcting the output of the first addition means for each voltage reference of each phase obtained by the voltage reference calculation means. A power conversion device. The voltage reference calculation means includes
2. The power converter according to claim 1, wherein the AC motor can generate and output a voltage reference that is substantially proportional to the frequency proportional to the magnetic flux reference. The magnetic flux reference generating means is
3. The power converter according to claim 1, wherein when the load power applied to the AC motor is smaller than a predetermined value, the magnetic flux reference is decreased in proportion to the load power. The magnetic flux reference generating means is
3. The magnetic flux reference is decreased in proportion to the minimum value when a minimum value of load electric power of each phase applied to the AC motor is smaller than a predetermined value. The power converter described. The minimum value of the magnetic flux reference given by the magnetic flux reference generating means is
5. The voltage limit reduction ratio obtained by dividing the minimum value among the voltage limit values of each phase by the original voltage limit value is obtained by multiplying by the magnetic flux reference at the time of rating. The power converter described.

Images