WO2014141398A1 - Pwm control method and power conversion apparatus using same - Google Patents

Pwm control method and power conversion apparatus using same Download PDF

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Publication number
WO2014141398A1
WO2014141398A1 PCT/JP2013/056906 JP2013056906W WO2014141398A1 WO 2014141398 A1 WO2014141398 A1 WO 2014141398A1 JP 2013056906 W JP2013056906 W JP 2013056906W WO 2014141398 A1 WO2014141398 A1 WO 2014141398A1
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Prior art keywords
voltage
phase
modulation factor
output
inverter circuit
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PCT/JP2013/056906
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French (fr)
Japanese (ja)
Inventor
景山　寛
徹 増田
歩 畑中
石川　勝美
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株式会社日立製作所
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Priority to PCT/JP2013/056906 priority Critical patent/WO2014141398A1/en
Publication of WO2014141398A1 publication Critical patent/WO2014141398A1/en

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H02M7/487—Neutral point clamped inverters

Definitions

  • the present invention relates to a PWM (Pulse Width Modulation) control method (control method) of a three-level inverter that converts a DC voltage into a three-phase AC voltage, and a power converter using the same.
  • PWM Pulse Width Modulation
  • PWM control inverter device power converter using PWM control method
  • DC voltage (current) into three-phase AC voltage (current) is motor control, uninterruptible power supply, power conditioner, frequency power converter It is used for such as.
  • a triangular wave comparison method sub-harmonic method
  • a triangular wave comparison method a triangular wave carrier signal and a sinusoidal voltage command are compared.
  • the transistor connected to the high voltage node is turned on, and when the voltage command is low, the low voltage node is set. Turn on the connected transistor.
  • a phase voltage corresponding to a three-phase sine wave is obtained.
  • the PWM control inverter device there are a two-level inverter and a three-level inverter.
  • a two-level inverter which is a typical inverter, inputs a DC voltage + Ed, -Ed to an inverter main circuit, and is positive (+ Ed), negative (-Ed) by a leg circuit composed of two transistors per output phase.
  • a three-level inverter inputs a DC voltage + Ed, -Ed and a zero potential obtained by dividing into two by a capacitor to the inverter main circuit, and a leg circuit composed of four transistors per output phase.
  • the inverter can output three-stage PWM voltage waveforms of positive (+ Ed), negative ( ⁇ Ed), and 0. Since the change rate of the output voltage due to switching is halved in the 3-level inverter compared to the 2-level inverter, switching is performed by halving the switching voltage of the switch elements constituting the inverter main circuit. Loss can be reduced.
  • a two-phase modulation method as a PWM control method for reducing switching loss by stopping transistor switching for a certain period and reducing the number of times the inverter main circuit is switched.
  • a zero-phase component signal is added to each phase so that the voltage command given to one phase switching element (switching device) of the three phases becomes the maximum value or the minimum value of the triangular wave carrier. Is fixed to an ON or OFF state for a predetermined period.
  • the switching loss of the transistor can be reduced without changing the line voltage of the fundamental wave component.
  • the voltage mode is switched every 60 degrees with respect to the phase angle of the output frequency, and control is performed so that each phase is always in an ON or OFF state in order.
  • the voltage utilization rate can be increased because the sinusoidal shape of the line voltage is not distorted. It also has features. Note that “3 1/2 ” is the route 3, but is simply simplified as “ ⁇ 3”.
  • Patent Document 1 A technique in which a two-phase modulation method is applied to a two-level inverter is disclosed in Patent Document 1. Further, as in the two-phase modulation method, a technique in which a PWM control method for stopping switching of a transistor for a certain period is applied to a three-level inverter is disclosed in Patent Document 2.
  • the two-phase modulation method since the two-phase modulation method includes many harmonics in the output phase voltage, it causes harmonic noise. This harmonic also causes a further increase in power loss such as a ground capacitor.
  • the modulation factor is high (close to 2 / ⁇ 3), the output voltage jump voltage width and harmonics are small, but when the modulation factor is low, the output voltage jump voltage width, Since the harmonics become large, the adverse effects caused by the zero-phase current and the harmonics become large.
  • the present invention solves such problems, and its object is to achieve power loss due to zero-phase voltage (current) of the inverter to which the two-phase modulation method is applied, harmonic noise, and peripheral devices. It is providing the PWM control method which reduces the bad influence on a power converter, and a power converter device using the same.
  • the present invention is configured as follows. That is, the PWM control method of the present invention generates a pulse for controlling the switch of the inverter circuit by comparing the first, second and third voltage commands with the carrier triangular wave, and the first, second and third Are obtained by adding a zero-phase signal to the first, second, and third basic sine waves, respectively, and the first, second, and third basic sine waves are 0 to 2 / ⁇ .
  • the zero-phase signal is a value obtained by selecting a median value from (1 ⁇ Va), (Va + Vb), and ( ⁇ 1 ⁇ Vb).
  • the power conversion device of the present invention includes an inverter circuit composed of a plurality of switching devices that output DC voltage waveforms of three stages of + Ed, 0, and ⁇ Ed using DC voltages + Ed and ⁇ Ed as power sources, And a control circuit for generating a PWM voltage waveform from the output of the inverter circuit, the control circuit being proportional to a predetermined modulation factor M, The amplitude of the frequency component is controlled, and the output voltage of the inverter circuit is set to any one of + Ed, 0, and -Ed with respect to a specific phase angle range of the fundamental frequency component during one period of the fundamental frequency component.
  • the output voltage of the inverter circuit is set to + Ed, 0, and ⁇ Ed in the specific phase angle range.
  • the modulation factor M is less than 2/3, the output voltage of the inverter circuit is fixed only to a voltage of 0 in the specific phase angle range, and is outside the specific phase angle range.
  • the inverter circuit is a three-level output three-level inverter that generates a pulsed voltage waveform with an amplitude Ed at the output of the inverter circuit.
  • a PWM control method for reducing power loss due to zero-phase voltage (current) of an inverter to which a two-phase modulation method is applied, harmonic noise, and adverse effects on peripheral devices, and a power converter using the PWM control method are provided. Can be provided.
  • FIG. 4A is a diagram when the modulation factor M is 0.9
  • FIG. 4B is a graph when the modulation factor M is 0.5.
  • FIG. 1 is a block diagram showing a circuit configuration of a power converter (inverter) 10 according to the first embodiment of the present invention.
  • the inverter 10 of the present invention includes an inverter main circuit (inverter circuit) 15 and a control circuit 17 that controls the inverter main circuit 15.
  • the control circuit 17 includes a basic voltage command generator 11, a voltage command corrector 12, a PWM pulse generator 13, and a gate driver 14. Further, the gate driver 14 includes a plurality of buffer circuits 16.
  • a basic voltage command generator 11 receives a modulation factor M and a phase angle ⁇ , and has three-phase sinusoidal basic voltage commands Vu0, Vv0, Vw0 (first, second, and third basic sine waves). ) In accordance with the modulation factor M and the phase angle ⁇ . Details of the modulation factor M, the phase angle ⁇ , and the basic voltage command generator 11 will be described later.
  • the voltage command corrector 12 adds the zero-phase signal Vz generated in the voltage command corrector 12 to the basic voltage commands Vu0, Vv0, Vw0, so that the voltage commands Vu, Vv, Vw (first, second, 3rd voltage command) is generated. Details of the voltage command corrector 12 will be described later.
  • the PWM pulse generator 13 generates PWM pulse logic signals Pu1 to Pu4, Pv1 to Pv4, Pw1 to Pw4 based on the input voltage commands Vu, Vv, and Vw, and supplies them to the gate driver 14. Details of the PWM pulse generator 13 will be described later.
  • the gate driver 14 is composed of a plurality of buffer circuits 16, by which the PWM pulse logic signals (Pu 1 to Pu 4, Pv 1 to Pv 4, Pw 1 to Pw 4) are transferred to the gate drive differential voltage electrical signal ( (Gu1 / Eu1 to Gu4 / Eu4, Gv1 / Ev1 to Gv4 / Ev4, Gw1 / Ew1 to Gw4 / Ew4) and supplied to the inverter main circuit 15. Details of the gate driver 14 and the buffer circuit 16 will be described later.
  • the inverter main circuit 15 is a three-level inverter main circuit, and three-stage voltages (Ed, 0, ⁇ Ed) are applied to the output terminals U, V, and W of the inverter main circuit 15 by PWM control using a signal from the PWM pulse generator 13. ) PWM voltage waveform is generated. Details of the inverter main circuit 15 will be described later.
  • the basic voltage command generator 11, the voltage command corrector 12, the PWM pulse generator 13, and the gate driver 14 constitute a control circuit 17 for PWM control of the inverter main circuit 15.
  • Each circuit of the control circuit 17, or the basic voltage command generator 11, the voltage command corrector 12, the PWM pulse generator 13, and the gate driver 14, which are constituent elements thereof, is constituted by an electronic circuit or a microprocessor. It is manufactured by a software program as a control IC medium.
  • the power converter (inverter) 10 using the PWM control method of the two-phase modulation method in which the amplitude of the zero-phase voltage and the zero-phase current is small compared to the prior art is embodied.
  • the basic voltage command generator 11 has sinusoidal basic voltage commands Vu0, Vv0, Vw0 (first, second, third) defined according to the modulation factor M and the phase angle ⁇ , as shown in the following equation (1).
  • Basic sine wave is generated and output.
  • Vu0 M ⁇ sin ( ⁇ )
  • Vv0 M ⁇ sin ( ⁇ 120 °)
  • Vw0 M ⁇ sin ( ⁇ 240 °)
  • the modulation factor M can be arbitrarily changed by a value of 0 to 2 / ⁇ 3.
  • the phase angle ⁇ is given with a function that increases in proportion to the time t.
  • FIG. 2 is a block diagram showing a circuit configuration of the voltage command corrector 12 provided in the power converter (inverter) 10 according to the first embodiment of the present invention.
  • the voltage command corrector 12 includes maximum value selectors (Max) 20 and 26, minimum value selectors (Min) 21 and 25, adders 23, 27, 28 and 29, a subtractor 22, 24.
  • the median value selector 201 includes the minimum value selector 25 and the maximum value selector 26.
  • the maximum value selector 20 and the minimum value selector 21 receive basic voltage commands Vu0, Vv0, and Vw0.
  • the maximum value selector 20 outputs the maximum value Va of the basic voltage commands Vu0, Vv0, Vw0 that change with time.
  • the minimum value selector 21 outputs the minimum value Vb of the basic voltage commands Vu0, Vv0, Vw0.
  • the subtractor 22 subtracts the maximum value Va from +1 to generate a signal (1-Va).
  • the adder 23 adds the maximum value Va and the minimum value Vb to generate a signal (Va + Vb).
  • the subtractor 24 subtracts the minimum value Vb from ⁇ 1 to generate a signal of ( ⁇ 1 ⁇ Vb).
  • the minimum value selector 25 selects and outputs the smaller one of (1 ⁇ Va) and (Va + Vb).
  • the maximum value selector 26 selects and outputs the larger value of the output signal of the minimum value selector 25 and ( ⁇ 1 ⁇ Vb).
  • the signal of the maximum value selector 26 is equally applied to each of the sine wave basic voltage commands Vu0, Vv0, and Vw0 constituting the three phases, as will be described below, so that the sine wave basics constituting the three phases are applied. This corresponds to the zero phase component of the voltage commands Vu0, Vv0, Vw0. Therefore, the output signal of the maximum value selector 26 is referred to as a zero phase signal Vz.
  • the adders 27, 28, and 29 add the zero-phase signal Vz to the basic voltage commands Vu0, Vv0, and Vw0 (first, second, and third basic sine waves) and respectively add the voltage commands Vu, Vv, and Vw. Output. That is, the voltage commands Vu, Vv, and Vw are shifted from the sinusoidal basic voltage commands Vu0, Vv0, and Vw0 constituting the three phases by the zero-phase signal Vz.
  • the voltage commands Vu, Vv, and Vw are different from the sine waveform because they are shifted by the zero-phase signal Vz, but the line voltages (Vu ⁇ Vv), ( Vv ⁇ Vw) and (Vw ⁇ Vu) constitute a three-phase sine wave by canceling the zero-phase signal Vz. Therefore, if the line voltage is used, a three-phase load such as a motor can be driven without any trouble.
  • the horizontal axis is the phase angle ⁇ (deg.), And the vertical axis is the value of each signal. However, the vertical axis is normalized by the maximum value of the basic voltage commands Vu0, Vv0, Vw0.
  • the modulation factor M is 0.9
  • the thick solid line is the zero phase signal (zero phase voltage command) Vz
  • the thin broken lines are (1-Va), (Va + Vb), ( ⁇ 1 ⁇ Vb).
  • FIG. 3A shows that the zero-phase signal Vz is selected from the median values of (1 ⁇ Va), (Va + Vb), and ( ⁇ 1 ⁇ Vb).
  • the modulation factor M is 0.5
  • the thick solid line is the zero-phase signal (zero-phase voltage command) Vz
  • the thin broken lines are (1-Va) and (-1-Vb).
  • FIG. 4 is a diagram illustrating waveforms of voltage commands Vu, Vv, and Vw generated by the voltage command corrector 12 included in the power conversion device according to the first embodiment of the present invention.
  • (B) is when the modulation factor M is 0.5.
  • the horizontal axis is the phase angle ⁇ (deg.), And the vertical axis is the value of each signal. However, the vertical axis is normalized by the maximum value of the voltage commands Vu, Vv, Vw.
  • a thick solid line is Vu
  • a thin solid line is Vv
  • a thin broken line is Vw.
  • the condition of the modulation rate at which the voltage commands Vu, Vv, and Vw are fixed at three voltage command values is 2/3 ⁇ M ⁇ 2 / ⁇ 3, and 0 ⁇ M ⁇ 2/3.
  • the voltage command value is fixed only at a value of zero.
  • the parameter ⁇ is a function ⁇ (M) determined depending on the modulation factor M, and is given by the following equation (2).
  • ⁇ 30 °
  • ⁇ is defined by the frequency method.
  • FIG. 5 is a graph showing the relationship between the modulation factor M and the parameter ⁇ in the voltage command corrector provided in the power converter according to the first embodiment of the present invention.
  • the horizontal axis of FIG. 5 is the modulation factor M
  • the vertical axis is the parameter ⁇ (deg.).
  • ⁇ is constant at 30 ° ( ⁇ / 6 radians) when M is smaller than 2/3
  • ⁇ is M when M is larger than 2/3.
  • FIG. 6 shows voltage commands Vu, Vv, Vw in the voltage command corrector provided in the power converter according to the first embodiment of the present invention, and voltage command values ⁇ 1, 0, +1 to which they are fixed. It is a figure showing the relationship which put together the length of the phase angle range used as the conditions where a voltage command is fixed, and the phase angle range. Note that the phase angle range is expressed in the power method (deg.). In FIG.
  • the range of the phase angle ⁇ in which the voltage command value is fixed to +1 is 60 ° + ⁇ ⁇ ⁇ 120 ° ⁇ , and the phase angle ⁇ in which the voltage command value is fixed to 0.
  • the range is 0 ⁇ ⁇ ⁇ , 180 ° ⁇ ⁇ ⁇ 180 ° + ⁇ , 360 ° ⁇ ⁇ 360 °, and the range of the phase angle ⁇ in which the voltage command value is fixed to ⁇ 1 is 240 ° + ⁇ ⁇ ⁇ 300 ° - ⁇ .
  • the lengths of the phase angle ranges in which the voltage command value is fixed to ⁇ 1, 0, ⁇ 1 are 60 ° ⁇ 2 ⁇ , 4 ⁇ , and 60 ° ⁇ 2 ⁇ , respectively.
  • (60 ° -2 ⁇ ) + (4 ⁇ ) + (60 ° -2 ⁇ ) 120 °
  • the total length of is 120 °.
  • FIG. 7 is a block diagram showing a circuit configuration of the PWM pulse generator 13 provided in the power conversion device according to the first embodiment of the present invention.
  • the PWM pulse generator 13 includes a triangular wave generator 31, a subtractor 32, comparators 33u, 33v, 33w, 34u, 34v, 34w, logic inversion circuits 35u, 35v, 35w, 36u, 36v, 36w, and ON delay.
  • the circuit 37 is configured.
  • the triangular wave generator 31 generates the carrier triangular wave signal Vcar1 (first carrier triangular wave signal) shown in FIG. 8, and the subtracter subtracts 1 from the value of Vcar1 to thereby generate the carrier triangular wave signal Vcar2 (second carrier triangular wave signal). ).
  • the detailed waveforms of the carrier triangular wave signals Vcar1 and Vcar2 will be described later with reference to FIG.
  • the comparator 33u compares the voltage command Vu with a triangular wave (carrier triangular wave signal) Vcar1. Further, the comparator 34u compares the voltage command Vu with the triangular wave Vcar2.
  • the logic inverting circuit 35u receives the signal from the comparator 33u and outputs the inverted signal.
  • the logic inversion circuit 36u receives the signal from the comparator 34u and outputs the inverted signal.
  • four types of PWM pulse logic signals Pu1 to Pu4 are generated by combining with the comparators 33u and 34u and the logic inverting circuits 35u and 36u.
  • the PWM pulse logic signals Pu1 to Pu4 are output via the ON delay circuit 37. The function of the ON delay circuit 37 will be described later.
  • the comparators 33u and 34u usually generate a pulse in any one of Pu1 to Pu4 every period 1 / fc.
  • the amplitudes of Vcar1 and Vcar2 of the triangular wave (carrier triangular wave signal) are slightly smaller than 1 (predetermined value)
  • pulses are generated in Pu1 to Pu4 only when the voltage command Vu is +1, 0, -1. do not do.
  • the predetermined value is a condition that only when the voltage command Vu is +1, 0, ⁇ 1, no pulse is generated in Pu1 to Pu4, and the apex of the triangular wave is close to +1 (or 0, or ⁇ 1).
  • a value selected within a range that does not malfunction due to noise or the like is a value selected within a range that does not malfunction due to noise or the like.
  • the configurations of the comparators 33v and 34v and the logic inverting circuits 35v and 36v are basically the same as the configurations of the comparators 33u and 34u and the logic inverting circuits 35u and 36u described above, and thus redundant description is omitted. Therefore, a circuit combining the comparators 33v and 34v and the logic inverting circuits 35v and 36v generates the PWM pulse logic signals Pv1 to Pv4 based on the voltage command Vv. Similarly, a circuit combining comparators 33w and 34w and logic inversion circuits 35w and 36w generates PWM pulse logic signals Pw1 to Pw4 based on voltage command Vw.
  • the ON delay circuit 37 is a delay circuit for slightly delaying the time when the PWM pulse logic signal becomes H level. However, when the PWM pulse logic signal becomes L level, it is quickly made L level. When the ON delay circuit 37 is at the H level and the L level, a delay time is provided, thereby providing a dead time for the switching operation of the transistor to which the PWM pulse logic signal is supplied, and variations in signal delay, etc. Prevents accidental short circuit.
  • FIG. 8 is a diagram showing waveforms of carrier triangular wave signals Vcar1 and Vcar2 in the PWM pulse generator provided in the power conversion device according to the first embodiment of the present invention.
  • the horizontal axis is the time transition, and the vertical axis is the signal voltage, normalized.
  • carrier triangular wave signals Vcar1 and Vcar2 are triangular waves having a frequency of PWM carrier frequency fc and a voltage amplitude slightly smaller than 1 (predetermined value).
  • the carrier triangular wave signal Vcar1 sweeps between 0 and +1
  • the carrier triangular wave signal Vcar2 sweeps between ⁇ 1 and 0.
  • the white circle portion indicates that the solid line of the triangular wave does not reach the broken line slightly. That is, as described above, Vcar1 is a triangular wave that can take a value between 0 and +1 and Vcar2 can take a value between -1 and 0, but does not take a value of +1, 0, or -1.
  • the gate driver 14 includes 12 buffer circuits 16 that convert PWM pulse logic signals Pu1 to Pu4, Pv1 to Pv4, and Pw1 to Pw4 into differential voltage electrical signals that are isolated from each other. ing.
  • the PWM pulse logic signals (Pu1 to Pu4, Pv1 to Pv4, Pw1 to Pw4) are converted into gate drive differential voltage electrical signals (Gu1 / Eu1 to Gu4 / Eu4, Gv1 / Ev1 to Gv4 / Ev4, Gw1 / Ew1 to Gw4 / Ew4). ) And supplied to the inverter main circuit 15.
  • the Pu1 signal is generated as a differential voltage electric signal from the buffer circuit 16 via the buffer circuit 16, and a differential voltage is generated between Gu1 and Eu1 and output as two signals.
  • the buffer circuit 16 can isolate output signals from each other by adopting an isolator such as a photocoupler, and has a high gate drive capability by employing a low impedance output circuit such as a push-pull circuit. be able to.
  • FIG. 9 is a diagram showing a circuit configuration of the inverter main circuit 15 provided in the power conversion device according to the first embodiment of the present invention.
  • the inverter main circuit 15 includes a positive DC power supply P (node P), a negative DC power supply N (node N), and a neutral DC power supply O (node O).
  • the node O at the neutral point may be grounded.
  • a capacitor C1 is connected between the positive DC power supply P and the neutral DC power supply O, and the voltage of Ed is applied.
  • a capacitor C2 is connected between the neutral DC power supply O and the negative DC power supply N, and the voltage of Ed is applied.
  • a U-phase leg, a V-phase leg, and a W-phase leg configured by including a transistor and a diode between the positive DC power source P and the negative DC power source N are configured in a parallel configuration corresponding to three phases. Has been.
  • the U-phase leg includes transistors Q11 to Q14 and diodes D11 to D16.
  • Transistors Q11 to Q14 made of IGBT (Insulated Gate Bipolar Transistor) are connected in series, the collector of the transistor Q11 is connected to a positive DC power supply P, and the emitter of the transistor Q14 is connected to a negative DC power supply N.
  • the emitter of the transistor Q12 and the collector of the transistor Q13 are connected to each other and to the output terminal U as a U-phase leg.
  • the diodes D11 to D14 are connected in antiparallel to the transistors Q11 to Q14, respectively.
  • the anode of the diode D15 is connected to the DC power source O at the neutral point, and the cathode is connected to the connection point between the emitter of the transistor Q11 and the collector of the transistor Q12.
  • the cathode of the diode D16 is connected to a neutral direct current power source O, and the anode is connected to the connection point between the emitter of the transistor Q13 and the collector of the transistor Q14.
  • Gu1 and Eu1 are applied as a differential voltage electrical signal (Gu1 / Eu1) from the gate driver 14 to the gate and emitter of the transistor Q11 formed of an IGBT, respectively. That is, a signal is applied as a voltage difference between the gate and the emitter.
  • Gu2 and Eu2 are applied to the gate and emitter of the transistor Q12 as the differential voltage electrical signal (Gu2 / Eu2) from the gate driver 14, respectively.
  • Gu3 and Eu3 are applied to the gate and emitter of the transistor Q13 as differential voltage electrical signals (Gu3 / Eu3) from the gate driver 14, respectively.
  • Gu4 and Eu4 are applied to the gate and emitter of the transistor Q14 as differential voltage electrical signals (Gu4 / Eu4) from the gate driver 14, respectively. From the above, the U-phase leg is configured.
  • the V phase includes transistors Q21 to Q24 and diodes D21 to D26, and is configured to correspond to the U phase transistors Q11 to Q14 and the diodes D11 to D16, respectively.
  • the transistors Q21 to Q24 have the same relationship as that of the U-phase transistors Q11 to Q14 in the differential voltage electrical signals (Gv1 / Ev1), (Gv2 / Ev2), (Gv3 / Ev3), and (Gv4 / Ev4), respectively. It is connected.
  • the W phase includes transistors Q31 to Q34 and diodes D31 to D36, and is configured to correspond to the U phase transistors Q11 to Q14 and the diodes D11 to D16, respectively.
  • the transistors Q31 to Q34 have the same relationship between the differential voltage electrical signals (Gw1 / Ew1), (Gw2 / Ew2), (Gw3 / Ew3), and (Gw4 / Ew4) as the U-phase transistors Q11 to Q14, respectively. It is connected.
  • the DC positive voltage + Ed is applied from the node P and the DC negative voltage -Ed is applied from the node N to each of the U-phase, V-phase, and W-phase legs. Further, a zero voltage (0 potential) is applied from the node O. As described above, the capacitors C1 and C2 are connected between the node PO and the node ON to hold the DC voltage Ed between the nodes.
  • each of the U-phase, V-phase, and W-phase legs converts the PWM pulse logic signals Pu1 to Pu4, Pv1 to Pv4, and Pw1 to Pw4 of the PWM pulse generator into a differential voltage electrical signal (Gu1 / Eu1 to (Gu4 / Eu4, Gv1 / Ev1 to Gv4 / Ev4, Gw1 / Ew1 to Gw4 / Ew4) are controlled by the signal so that the inverter main circuit 15 converts the DC voltage (power) into the three-phase AC voltage (power). Fulfills the function of converting to
  • the transistors have a silicon IGBT or a silicon MOSFET (Metal-Oxide-) as a switch device (switching device) for ease of turn-on / turn-off control.
  • Semiconductor Field-Effect Transistor is preferably used.
  • a silicon PiN diode or a silicon Schottky barrier diode as the diodes (D11 to D16, D21 to D26, D31 to D36).
  • a wide gap device wide gap power device including a semiconductor having a larger band gap than silicon instead of the silicon device.
  • a SiC (Silicon Carbide) device can be applied.
  • FIG. 10 is a diagram showing the relationship between the transistors Q11 to Q14 constituting the U-phase leg and the voltage command Vu in the inverter main circuit provided in the power conversion device according to the first embodiment of the present invention.
  • the transistors Q11 to Q14 constituting the U-phase leg perform a switching operation according to the voltage command Vu.
  • “ON” represents an ON state
  • “OFF” represents an OFF state
  • “SW” represents a switching state (a repeated state of ON and OFF).
  • the transistor Q11 and the transistor Q13 perform a switching operation.
  • the transistor Q12 and the transistor Q14 perform a switching operation.
  • the transistors Q11 to Q14 are fixed to either ON or OFF, and no switching operation is performed. Therefore, when the voltage command Vu is +1, 0, ⁇ 1, no switching loss occurs in the U-phase leg.
  • the voltage commands Vv, Vw are +1, 0, ⁇ 1, respectively, no switching loss occurs in the V-phase leg and the W-phase leg.
  • the power conversion device (inverter) 10 reduces switching loss (power consumption), loss due to zero-phase current, and high-frequency noise.
  • FIG. 11 is a diagram illustrating a voltage waveform output to the output terminal U of the U-phase leg in the inverter main circuit provided in the power conversion device according to the first embodiment of the present invention.
  • (B) is a voltage waveform when the modulation factor M is 0.5.
  • the horizontal axis represents the phase angle ⁇ (deg.)
  • the vertical axis represents the output voltage.
  • the carrier frequency fc used for PWM control is set to 100 times the fundamental frequency f1 constituting a three-phase AC sine wave.
  • phase angle is other than the above, a PWM waveform having an amplitude Ed is output to the output terminal U.
  • the above applies not only when the modulation factor M is 0.9, but also when the modulation factor 2/3 ⁇ M ⁇ 2 / ⁇ 3.
  • ⁇ is the parameter ⁇ described above.
  • FIGS. 11 (a) and 11 (b) show that the switching operation of the U-phase leg stops in the range of the phase angle length of 120 °, that is, a period of 1/3 of the whole. Further, for the same reason, the switching operation of the U-phase leg is stopped in the 1/3 overall period for the V-phase leg and the W-phase leg.
  • the output of the inverter main circuit 15 is also the output of the power converter device (inverter) 10 of this invention. Therefore, it is also a characteristic of the power conversion device (inverter) 10.
  • FIG. 12 is a diagram illustrating a frequency spectrum of a voltage waveform output to the output terminal U of the inverter main circuit 15 provided in the power conversion device according to the first embodiment of the present invention.
  • (B) is a frequency spectrum when the modulation factor M is 0.5.
  • the horizontal axis represents the harmonic order n, and the vertical axis represents the amplitude value Vn / Ed of the nth-order frequency component Vn.
  • the carrier frequency fc is set to 99 times the basic frequency f1.
  • V1 is a component of the fundamental frequency f1
  • its amplitude value V1 / Ed is 0.90 in FIG. 12A, which is the same value as the modulation factor (0.9).
  • FIG. 12B it is 0.50, which is the same value as the modulation rate (0.5).
  • V99 is a component of the carrier frequency fc
  • its amplitude value V99 / Ed is 0.32 in FIG. 12A and 0.30 in FIG.
  • the third-order component V3 is 0.14 in FIG. 12A and 0.21 in FIG.
  • FIG. 13 shows the frequency spectrum of the voltage waveform of the output of the three-level inverter to which the control characteristic two-phase modulation method shown in FIG. 19 is applied as a comparative example. And it compares with the frequency spectrum of the voltage waveform of the output of the inverter 10 of this invention mentioned above in FIG.
  • the inverter 10 of the present invention is also a three-level inverter to which the two-phase modulation method is applied.
  • FIG. 13 is a diagram illustrating a frequency spectrum of a voltage waveform output from a three-level inverter to which a two-phase modulation method of a comparative example described later is applied.
  • FIG. ) Is a frequency spectrum when the modulation factor M is 0.5.
  • the horizontal axis represents the harmonic order n, and the vertical axis represents the amplitude value Vn / Ed of the nth-order frequency component Vn.
  • the carrier frequency fc is set to 99 times the basic frequency f1.
  • V1 is a component of the fundamental frequency f1
  • its amplitude value V1 / Ed is 0.90 in FIG. 13A, which is the same value as the modulation factor (0.9). .
  • V99 is a component of the carrier frequency fc, and its amplitude value V99 / Ed is 0.30 in FIG. 13A and 0.31 in FIG.
  • the third harmonic component V3 is 0.16 in FIG. 13A and 0.66 in FIG.
  • V9 of the 9th harmonic component and V15 of the 15th harmonic component appear at conspicuous levels.
  • FIG. 12 and FIG. 13 which are inverters of the present invention and the comparative example. Comparing FIG. 12 and FIG. 13, most amplitude values of the frequency component Vn of the voltage waveform output to the output terminal U of the first embodiment of the present invention are smaller than that of the two-phase modulation method of the comparative example. ing. In particular, this tendency becomes stronger as the modulation factor M is smaller.
  • the amplitude values of higher harmonic components V9, V15, etc. are more significant than the third harmonic component V3.
  • these are almost eliminated.
  • the inverter using the PWM control method of the present invention can suppress the harmonic component contained in the output voltage waveform to be smaller than that of the inverter using the two-phase modulation method of the comparative example. This tendency is particularly remarkable when the modulation rate is small.
  • FIG. 14 is a diagram illustrating a waveform of the zero-phase voltage Ez3 included in the output voltage of the power conversion device (inverter) 10 or the inverter main circuit 15 according to the first embodiment of the present invention.
  • the modulation factor M is 0.9
  • (b) is a waveform when the modulation factor M is 0.5.
  • the vertical axis represents the zero-phase voltage Ez3
  • the horizontal axis represents the phase angle ⁇
  • the phase angle ⁇ 0 ° to 360 °, and the range of 30 ° to 90 °.
  • 14A and 14B show that the amplitude of the zero-phase voltage Ez3 generated by the inverter 10 is within ⁇ 1/3 of the DC voltage Ed. Note that the characteristics of FIG. 14 will be further described while comparing the characteristics of the comparative example shown in FIG.
  • FIG. 15 is a diagram showing a waveform of the zero-phase voltage Ez2 included in the output voltage of the three-level inverter using the two-phase modulation method of the comparative example described later.
  • FIG. 15A shows a modulation factor M of 0.9.
  • (B) is a waveform when the modulation factor M is 0.5.
  • the vertical axis represents the zero-phase voltage Ez2
  • the horizontal axis represents the phase angle ⁇
  • the phase angle ⁇ 0 ° to 360 °
  • the range of 30 ° to 90 ° is included. Extracted and shown.
  • the inverter of the first embodiment of the present invention corresponds to the waveform of the voltage command value of FIG. 4, and the waveform of FIG. 15 of the inverter of the comparative example is the voltage command of FIG. Corresponds to the value waveform. That is, selecting the waveform of the voltage command value of the inverter of the PWM control method of the present invention as shown in FIG. 4 reduces the zero-phase current and brings about the above effect.
  • FIG. 16 is a diagram showing a measurement circuit for the zero-phase voltage Ez3 of the power converter (inverter) 10 according to the first embodiment of the present invention and the zero-phase voltage Ez2 of the comparative example.
  • the same resistance as the reactor Lac having the same reactor value is applied to the output terminals U, V, and W of the inverter (10) with the node O of the inverter 10 of the first embodiment of the present invention or the inverter of the comparative example as the ground potential.
  • a series circuit of value resistors Rac is connected to each other, and a ground voltage of a node at a portion where one ends of the resistors Rac are connected to each other is observed. With this measurement, the zero-phase voltage Ez (Ez3, Ez2) can be observed.
  • FIG. 17 is a diagram showing a circuit configuration of the inverter main circuit 45 provided in the power conversion device according to the second embodiment of the present invention.
  • the inverter main circuit 45 includes a positive DC power supply P (node P), a negative DC power supply N (node N), and a neutral DC power supply O (node O).
  • a capacitor C3 is connected between the positive DC power supply P and the neutral DC power supply O, and the voltage of Ed is applied.
  • a capacitor C4 is connected between the neutral DC power supply O and the negative DC power supply N, and the voltage of Ed is applied.
  • a U-phase leg, a V-phase leg, and a W-phase leg configured by including a transistor and a diode between the positive DC power source P and the negative DC power source N are configured in a parallel configuration corresponding to three phases. Has been.
  • the U-phase leg includes transistors Q41 to Q44 and diodes D41 to D44.
  • An IGBT transistor Q41 and a transistor Q44 are connected in series, a collector of the transistor Q41 is connected to a positive DC power supply P (node P), and an emitter of the transistor Q44 is connected to a negative DC power supply N (node N). Yes.
  • the emitter of the transistor Q41 and the collector of the transistor Q44 are connected to each other and to the output terminal U as a U-phase leg.
  • the transistor Q42 and the transistor Q43 are connected in series via each other's collector, the emitter of the transistor Q42 is connected to the node O, and the emitter of the transistor Q43 is connected to the output terminal U.
  • the diodes D41 to D44 are connected in antiparallel to the transistors Q41 to Q44, respectively.
  • Gu1 and Eu1 are applied to the gate and emitter of the transistor Q41 formed of IGBT as a differential voltage electrical signal (Gu1 / Eu1) from the gate driver 14, respectively.
  • Gu2 and Eu2 are applied to the gate and emitter of the transistor Q42 as differential voltage electrical signals (Gu2 / Eu2) from the gate driver 14, respectively.
  • Gu3 and Eu3 are applied to the gate and emitter of the transistor Q43 as differential voltage electrical signals (Gu3 / Eu3) from the gate driver 14, respectively.
  • Gu4 and Eu4 are applied to the gate and emitter of the transistor Q44 as differential voltage electrical signals (Gu4 / Eu4) from the gate driver 14, respectively. From the above, the U-phase leg is configured.
  • connection configuration of the transistor Q42 and the transistor Q43 is different from the configuration of the connection of the transistor Q12 and the transistor Q13 of the inverter main circuit 15 (FIG. 9) of the first embodiment, but the output terminal as a U-phase leg. From U, a substantially similar output waveform is output.
  • the V phase includes transistors Q51 to Q54 and diodes D51 to D54, and is configured to correspond to the U phase transistors Q41 to Q44 and the diodes D41 to D44, respectively.
  • the differential voltage electrical signals Gv1 / Ev1), (Gv2 / Ev2), (Gv3 / Ev3), and (Gv4 / Ev4) are respectively related to the transistors Q51 to Q54 in the same relationship as the U-phase transistors Q41 to Q44. Connected with.
  • the W phase includes transistors Q61 to Q64 and diodes D61 to D64, and is configured to correspond to the U phase transistors Q41 to Q44 and the diodes D41 to D44, respectively.
  • the differential voltage electrical signals (Gw1 / Ew1), (Gw2 / Ew2), (Gw3 / Ew3), and (Gw4 / Ew4) are respectively connected to the transistors Q61 to Q64 in the same relationship as the U-phase transistors Q11 to Q14. Connected with.
  • the DC positive voltage + Ed is applied from the node P and the DC negative voltage -Ed is applied from the node N to the U-phase, V-phase, and W-phase legs, and the zero voltage (0 potential) is applied from the node O. ) Is given.
  • the capacitors C3 and C4 are connected between the node PO and the node ON to hold the DC voltage Ed between the nodes.
  • each of the U-phase, V-phase, and W-phase legs converts the PWM pulse logic signals Pu1 to Pu4, Pv1 to Pv4, and Pw1 to Pw4 of the PWM pulse generator into a differential voltage electrical signal (Gu1 / Eu1 to (Gu4 / Eu4, Gv1 / Ev1 to Gv4 / Ev4, Gw1 / Ew1 to Gw4 / Ew4) are controlled by the signal so that the inverter main circuit 45 converts the DC voltage (power) into the three-phase AC voltage (power). Fulfills the function of converting to
  • the number of diode elements can be reduced by six compared to the circuit of FIG.
  • the number of series-connected transistors and diodes between the output terminals U, V, and W, and the nodes P and N is reduced from 2 to 1, these elements are required to have double withstand voltage.
  • a wide gap device wide gap power device
  • a semiconductor element having a larger band gap than silicon instead of the silicon device.
  • a SiC device can be applied.
  • a silicon IGBT or a silicon MOSFET for the transistor used in the circuit of FIG. 17 because of easy control of turn-on / turn-off.
  • the diode a silicon PiN diode or a silicon Schottky barrier diode is used.
  • Comparative example As a comparative example, an example in which the voltage command of the two-phase modulation method when the voltage command value is not fixed to 0 is applied to a three-level inverter is shown below.
  • FIG. 18 is a diagram illustrating an example of the voltage command of the two-phase modulation method of the comparative example (when the voltage command value is not fixed to 0).
  • the vertical axis represents the (normalized) voltage command value, and the horizontal axis represents the phase angle.
  • the voltage commands Vu2, Vv2, and Vw2 are generated by adding a zero-phase signal to the basic sine wave signal.
  • the waveforms (Vu2, Vv2, Vw2) in FIG. 18 a phase angle range in which the voltage command value is fixed at +1 and ⁇ 1 is formed.
  • the voltage command Vu2 is fixed to +1 at a phase angle of 60 ° to 120 °, and is fixed to ⁇ 1 at a phase angle of 240 ° to 300 °. Note that the range in which the voltage command value is fixed at 0 as shown in FIG. 4 of the present invention does not exist in FIG. 18 of the comparative example.
  • the PWM voltage waveform (only one phase is shown) shown in FIG. 19 can be output.
  • FIG. 19 is a diagram illustrating a PWM voltage waveform (U phase) obtained by applying the voltage command of the two-phase modulation method of the comparative example to the three-level inverter.
  • the vertical axis represents the output voltage
  • the horizontal axis represents the phase angle.
  • the PWM voltage waveform shown in FIG. 19 is obtained by comparing the voltage command value shown in FIG. 18 with two carrier triangular waves having amplitudes of 0 to +1 and ⁇ 1 to 0 and a PWM signal obtained by a comparator. It is obtained by switching the transistor.
  • FIG. 19 is a diagram illustrating a PWM voltage waveform (U phase) obtained by applying the voltage command of the two-phase modulation method of the comparative example to the three-level inverter.
  • the vertical axis represents the output voltage
  • the horizontal axis represents the phase angle.
  • the PWM voltage waveform shown in FIG. 19 is obtained by comparing the voltage command value shown in FIG. 18 with two carrier triangular waves having ampli
  • the output voltage waveform (PWM voltage waveform) is fixed to + Ed at a phase angle of 60 ° to 120 °, and is fixed to ⁇ Ed at a phase angle of 240 ° to 300 °. Therefore, the switching operation of the three-level inverter can be stopped at 120 ° out of the total phase angle 360 °. Therefore, in each switch element constituting the inverter, the number of times of switching can be reduced to 2/3, and the switching loss can be reduced.
  • Patent Document 1 and Patent Document 2 describe a two-phase modulation method and a PWM control method for stopping switching of a transistor for a certain period as in the case of two-phase modulation. Note that the two-phase modulation method does not distort the sinusoidal shape of the line voltage even if the modulation rate is increased to 2 / ⁇ 3, which is larger than 1, so that the voltage utilization rate can be increased. I have. However, the two-phase modulation method of the comparative example shown in FIGS. 18 and 19 is a method of fixing the voltage command value to +1 or ⁇ 1 but not fixing it to 0.
  • the voltage command value is fixed to 0 within a predetermined phase angle range.
  • the present invention uses a zero-phase voltage command that reduces the generation of harmonics, so that there is little zero-phase current, and there is an effect of reducing power consumption and noise due to harmonics and zero-phase current. This is particularly noticeable when the modulation rate is small.
  • Control circuit 17 ⁇ Control circuit 17
  • the control circuit 17 that controls the inverter main circuit 15 has been described as being configured with the basic voltage command generator 11, the voltage command corrector 12, the PWM pulse generator 13, and the gate driver 14. It is not limited.
  • the gate driver 14 may be included in the PWM pulse generator 13.
  • the basic voltage command generator 11 and the voltage command corrector 12 may be integrated.
  • the basic voltage command generator 11, the voltage command corrector 12, and the PWM pulse generator 13 may be configured by individual hardware circuits, MPU (Micro-Processing Unit), A configuration may be adopted in which control is performed collectively by a software program using a control IC such as a CPU (Central Processing Unit) as a medium.
  • MPU Micro-Processing Unit
  • the transistor is described as an IGBT, and the possibility of using a MOSFET instead has been described.
  • the transistor basically needs to be a switching element, it is limited to an IGBT or a MOSFET.
  • BJT Bipolar junction transistor
  • BiCMOS Bipolar Complementary Metal Oxide Semiconductor
  • SiC SiC was mentioned as a wide gap device, it is not limited to this.
  • a semiconductor device such as GaN (gallium nitride) or Ga 2 O 3 (gallium oxide) may be used.
  • diode 9 and 17 it has been described that the diodes (D11 to D14, D21 to D24, D31 to D34, D41 to D44, D51 to D54, D61 to D64) are connected in reverse parallel to the transistor (IGBT).
  • IGBT transistor
  • a parasitic diode incorporated in a transistor (IGBT, MOSFET) may be used without being added as an element.

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Abstract

The present invention is provided with: an inverter circuit in which a plurality of switching devices are configured to use a direct-current voltage (+Ed, -Ed) as a power source, and to output the PWM voltage waveform at three levels (+Ed, 0, and -Ed); and a control circuit for turning the plurality of switching devices on and off, and generating the PWM voltage waveform on the basis of the output of the inverter circuit. The control circuit: controls the amplitude of the fundamental frequency component of the PWM voltage waveform in proportion to a prescribed modulation factor (M); during one cycle of the fundamental frequency component, fixes the output voltage of the inverter circuit at +Ed, 0, or -Ed relative to a specified phase angle range for the fundamental frequency component; fixes the output voltage of the inverter circuit at all of the voltages +Ed, 0, and -Ed in the specified phase angle range when the modulation (M) is 2/3 or greater; and fixes the output voltage of the inverter circuit at a voltage of 0 in the specified phase angle range when the modulation (M) is less than 2/3.

Description

ＰＷＭ制御方法とそれを用いた電力変換装置PWM control method and power converter using the same
　本発明は、直流電圧を三相交流電圧に変換する３レベルインバータのＰＷＭ（Pulse Width Modulation）制御方法（制御方式）とそれを用いた電力変換装置に関するものである。 The present invention relates to a PWM (Pulse Width Modulation) control method (control method) of a three-level inverter that converts a DC voltage into a three-phase AC voltage, and a power converter using the same.
　直流電圧（電流）を三相の交流電圧（電流）に変換するＰＷＭ制御インバータ装置（ＰＷＭ制御方法を用いた電力変換装置）は、モータ制御、無停電電源装置、パワーコンディショナ、周波数電力変換装置などに使用されている。ＰＷＭ制御方法を代表する方法として、三角波比較方法（方式）（Sub-harmonic Method）が広く知られている。
　三角波比較方法では、三角波のキャリア信号と、正弦波状の電圧指令とを比較し、電圧指令が高い場合には高い電圧ノードに接続したトランジスタをＯＮ（オン）させ、低い場合には低い電圧ノードに接続したトランジスタをＯＮさせる。この制御により、三相の正弦波に相当する相電圧が得られる。
　また、ＰＷＭ制御インバータ装置としては、２レベルインバータと３レベルインバータがある。 PWM control inverter device (power converter using PWM control method) that converts DC voltage (current) into three-phase AC voltage (current) is motor control, uninterruptible power supply, power conditioner, frequency power converter It is used for such as. As a method representative of the PWM control method, a triangular wave comparison method (sub-harmonic method) is widely known.
In the triangular wave comparison method, a triangular wave carrier signal and a sinusoidal voltage command are compared. When the voltage command is high, the transistor connected to the high voltage node is turned on, and when the voltage command is low, the low voltage node is set. Turn on the connected transistor. By this control, a phase voltage corresponding to a three-phase sine wave is obtained.
As the PWM control inverter device, there are a two-level inverter and a three-level inverter.
　代表的なインバータである２レベルインバータは、インバータ主回路に直流電圧＋Ｅｄ，－Ｅｄを入力し、出力１相あたり２個のトランジスタで構成されたレグ回路によって、正（＋Ｅｄ）、負（－Ｅｄ）の２段階のＰＷＭ電圧波形を出力する。
　これに対して、３レベルインバータは、インバータ主回路に直流電圧＋Ｅｄ，－Ｅｄと、コンデンサにより２分割して得られる０電位を入力し、出力１相あたり４個のトランジスタで構成されたレグ回路によって、正（＋Ｅｄ）、負（－Ｅｄ）、および０の３段階のＰＷＭ電圧波形を出力できるインバータである。なお、３レベルインバータは、２レベルインバータと比較して、スイッチングによる出力電圧の変化率が１／２になるため、インバータ主回路を構成するスイッチ素子のスイッチング電圧を１／２にすることでスイッチング損失を減らすことができる。 A two-level inverter, which is a typical inverter, inputs a DC voltage + Ed, -Ed to an inverter main circuit, and is positive (+ Ed), negative (-Ed) by a leg circuit composed of two transistors per output phase. 2) PWM voltage waveform in two stages.
In contrast, a three-level inverter inputs a DC voltage + Ed, -Ed and a zero potential obtained by dividing into two by a capacitor to the inverter main circuit, and a leg circuit composed of four transistors per output phase. Thus, the inverter can output three-stage PWM voltage waveforms of positive (+ Ed), negative (−Ed), and 0. Since the change rate of the output voltage due to switching is halved in the 3-level inverter compared to the 2-level inverter, switching is performed by halving the switching voltage of the switch elements constituting the inverter main circuit. Loss can be reduced.
　また、トランジスタのスイッチングを一定期間停止させ、インバータ主回路のスイッチング回数を減らすことでスイッチング損失を低減するＰＷＭ制御方法として二相変調方法（方式）がある。
　二相変調方法は、三相のうちの一相のスイッチ素子（スイッチングデバイス）に与える電圧指令が三角波キャリアの最大値あるいは最小値になるように各相に零相成分の信号を加え、スイッチ素子を所定の間ＯＮあるいはＯＦＦ（オフ）の状態に固定することである。この方法により基本波成分の線間電圧を変化させることなくトランジスタのスイッチング損失を低減できる。一般的には、出力周波数の位相角に対して６０度毎に電圧モードを切り替え、各相が順番に常時ＯＮあるいはＯＦＦの状態になるように制御する。
　また、二相変調方法は、変調率を１より大きい２／３1/2まで高めても、線間電圧の正弦波形状に歪みを与えることが無いので、電圧利用率を大きくすることができる特徴も備えている。なお、「３1/2」は、ルート３であるが、適宜、簡略化して「√３」と表記する。 There is a two-phase modulation method (method) as a PWM control method for reducing switching loss by stopping transistor switching for a certain period and reducing the number of times the inverter main circuit is switched.
In the two-phase modulation method, a zero-phase component signal is added to each phase so that the voltage command given to one phase switching element (switching device) of the three phases becomes the maximum value or the minimum value of the triangular wave carrier. Is fixed to an ON or OFF state for a predetermined period. By this method, the switching loss of the transistor can be reduced without changing the line voltage of the fundamental wave component. Generally, the voltage mode is switched every 60 degrees with respect to the phase angle of the output frequency, and control is performed so that each phase is always in an ON or OFF state in order.
Further, in the two-phase modulation method, even if the modulation rate is increased to 2/3 1/2 , which is larger than 1, the voltage utilization rate can be increased because the sinusoidal shape of the line voltage is not distorted. It also has features. Note that “3 1/2 ” is the route 3, but is simply simplified as “√3”.
　前記の二相変調方法の詳細は、比較例として図１８、図１９を参照して後記する。
　２レベルインバータに二相変調方法を適用した技術は、特許文献１に開示されている。
　また、３レベルインバータに、前記二相変調方法と同様に、トランジスタのスイッチングを一定期間停止するＰＷＭ制御方法を適用した技術は、特許文献２に開示されている。 Details of the two-phase modulation method will be described later with reference to FIGS. 18 and 19 as comparative examples.
A technique in which a two-phase modulation method is applied to a two-level inverter is disclosed in Patent Document 1.
Further, as in the two-phase modulation method, a technique in which a PWM control method for stopping switching of a transistor for a certain period is applied to a three-level inverter is disclosed in Patent Document 2.
特開平９－１４９６６０号公報JP-A-9-149660 特開２００６－１２１８７７号公報JP 2006-121877 A
　特許文献１、２に開示された二相変調方法を適用した技術においては、後記（図１８）するように、二相変調方法の電圧指令に、位相角６０°毎に不連続点が存在する。
　そのため、電圧指令が不連続であるタイミングで、インバータの出力電圧が跳躍（短時間に急激に変化）し、対地コンデンサや、インバータ出力に接続された配線、負荷（モータ、あるいは変圧器など）に存在する対地間の寄生静電容量を通じて、零相電流が発生する。この零相電流は、対地コンデンサでの電力損失を生じさせる。また零相電流は、寄生静電容量を通した系統電源への流出によって、周辺機器への悪影響をもたらす可能性がある。
　また、二相変調方法は、出力の相電圧に高調波を多く含むため、高調波ノイズの原因となる。また、この高調波は、対地コンデンサなどの電力損失の一層の増加をもたらす。
　変調率が高い（２／√３に近い）場合には、前記の出力電圧の跳躍電圧幅や、高調波は小さいが、変調率が低い場合には、前記の出力電圧の跳躍電圧幅や、高調波が大きくなるため、零相電流および高調波が引き起こす悪影響が大きくなる。 In the technology to which the two-phase modulation method disclosed in Patent Documents 1 and 2 is applied, as will be described later (FIG. 18), there are discontinuities in the voltage command of the two-phase modulation method every phase angle of 60 °. .
Therefore, the output voltage of the inverter jumps at a timing when the voltage command is discontinuous (changes rapidly in a short time), and is connected to the ground capacitor, the wiring connected to the inverter output, and the load (motor, transformer, etc.) A zero-phase current is generated through the existing parasitic capacitance between the ground. This zero-phase current causes a power loss in the ground capacitor. In addition, the zero-phase current may adversely affect peripheral devices due to the outflow to the system power supply through the parasitic capacitance.
In addition, since the two-phase modulation method includes many harmonics in the output phase voltage, it causes harmonic noise. This harmonic also causes a further increase in power loss such as a ground capacitor.
When the modulation factor is high (close to 2 / √3), the output voltage jump voltage width and harmonics are small, but when the modulation factor is low, the output voltage jump voltage width, Since the harmonics become large, the adverse effects caused by the zero-phase current and the harmonics become large.
　そこで、本発明は、このような問題点を解決するもので、その目的とするところは、二相変調方法を適用したインバータの零相電圧（電流）による電力損失、高調波ノイズ、および周辺機器への悪影響を低減するＰＷＭ制御方法とそれを用いた電力変換装置を提供することである。 Therefore, the present invention solves such problems, and its object is to achieve power loss due to zero-phase voltage (current) of the inverter to which the two-phase modulation method is applied, harmonic noise, and peripheral devices. It is providing the PWM control method which reduces the bad influence on a power converter, and a power converter device using the same.
　前記の課題を解決して、本発明の目的を達成するために、以下のように構成した。
　すなわち、本発明のＰＷＭ制御方法は、第１、第２、第３の電圧指令とキャリア三角波を比較することでインバータ回路のスイッチを制御するパルスを生成し、前記第１、第２、第３の電圧指令は、第１、第２、第３の基本正弦波にそれぞれ零相信号を加算することによって得られ、前記第１、第２、第３の基本正弦波は、０から２／√３の間の値で可変できる変調率の振幅を持ち、互いに位相が１２０°異なる正弦波信号であり、前記第１、第２、第３の基本正弦波の最大値と最小値をそれぞれＶａ、Ｖｂとしたとき、前記零相信号は、（１－Ｖａ）、（Ｖａ＋Ｖｂ）、（－１－Ｖｂ）から中央値を選んだ値であることを特徴とする。 In order to solve the above-described problems and achieve the object of the present invention, the present invention is configured as follows.
That is, the PWM control method of the present invention generates a pulse for controlling the switch of the inverter circuit by comparing the first, second and third voltage commands with the carrier triangular wave, and the first, second and third Are obtained by adding a zero-phase signal to the first, second, and third basic sine waves, respectively, and the first, second, and third basic sine waves are 0 to 2 / √. 3 is a sine wave signal having a modulation factor amplitude variable by a value between 3 and having a phase difference of 120 °, and the maximum value and the minimum value of the first, second, and third basic sine waves are Va, When Vb is set, the zero-phase signal is a value obtained by selecting a median value from (1−Va), (Va + Vb), and (−1−Vb).
　また、本発明の電力変換装置は、直流電圧＋Ｅｄ、－Ｅｄを電源とし、＋Ｅｄ、０、－Ｅｄの三段階のＰＷＭ電圧波形を出力する複数のスイッチングデバイスで構成されたインバータ回路と、前記複数のスイッチングデバイスのＯＮ／ＯＦＦ制御を行い、前記インバータ回路の出力からＰＷＭ電圧波形を発生させる制御回路と、を備え、前記制御回路は、所定の変調率Ｍに比例して前記ＰＷＭ電圧波形の基本周波数成分の振幅を制御し、前記基本周波数成分の一周期の間に、前記インバータ回路の出力電圧を、前記基本周波数成分の特定の位相角範囲に対して＋Ｅｄ、０、－Ｅｄのいずれかで固定させ、前記変調率Ｍが２／３以上のときには、前記特定の位相角範囲において、前記インバータ回路の出力電圧を、＋Ｅｄ、０、および－Ｅｄの全ての電圧に固定させ、前記変調率Ｍが２／３未満のときには、前記特定の位相角範囲において、前記インバータ回路の出力電圧を、０の電圧にのみ固定させ、前記特定の位相角範囲以外の範囲では、前記インバータ回路の出力に振幅Ｅｄのパルス状電圧波形を発生させる３相出力の３レベルインバータであることを特徴とする。 Further, the power conversion device of the present invention includes an inverter circuit composed of a plurality of switching devices that output DC voltage waveforms of three stages of + Ed, 0, and −Ed using DC voltages + Ed and −Ed as power sources, And a control circuit for generating a PWM voltage waveform from the output of the inverter circuit, the control circuit being proportional to a predetermined modulation factor M, The amplitude of the frequency component is controlled, and the output voltage of the inverter circuit is set to any one of + Ed, 0, and -Ed with respect to a specific phase angle range of the fundamental frequency component during one period of the fundamental frequency component. When the modulation factor M is 2/3 or more, the output voltage of the inverter circuit is set to + Ed, 0, and −Ed in the specific phase angle range. When the modulation factor M is less than 2/3, the output voltage of the inverter circuit is fixed only to a voltage of 0 in the specific phase angle range, and is outside the specific phase angle range. In this range, the inverter circuit is a three-level output three-level inverter that generates a pulsed voltage waveform with an amplitude Ed at the output of the inverter circuit.
　また、その他の手段は、発明を実施するための形態のなかで説明する。 Further, other means will be described in the embodiment for carrying out the invention.
　本発明によれば、二相変調方法を適用したインバータの零相電圧（電流）による電力損失、高調波ノイズ、および周辺機器への悪影響を低減するＰＷＭ制御方法とそれを用いた電力変換装置を提供することができる。 According to the present invention, a PWM control method for reducing power loss due to zero-phase voltage (current) of an inverter to which a two-phase modulation method is applied, harmonic noise, and adverse effects on peripheral devices, and a power converter using the PWM control method are provided. Can be provided.
本発明の第１実施形態に係る電力変換装置の回路構成を示すブロック図である。It is a block diagram which shows the circuit structure of the power converter device which concerns on 1st Embodiment of this invention. 本発明の第１実施形態に係る電力変換装置に備えられた電圧指令補正器の回路構成を示すブロック図である。It is a block diagram which shows the circuit structure of the voltage command correction device with which the power converter device which concerns on 1st Embodiment of this invention was equipped. 本発明の第１実施形態に係る電力変換装置に備えられた電圧指令補正器における零相信号Ｖｚおよび（１－Ｖａ）、（Ｖａ＋Ｖｂ）、（－１－Ｖｂ）の各信号のそれぞれの波形を示す図であり、（ａ）は変調率Ｍが０．９のとき、（ｂ）は変調率Ｍが０．５のときである。The waveforms of the zero-phase signal Vz and each signal of (1-Va), (Va + Vb), and (-1-Vb) in the voltage command corrector provided in the power converter according to the first embodiment of the present invention are as follows. 4A is a diagram when the modulation factor M is 0.9, and FIG. 4B is a graph when the modulation factor M is 0.5. 本発明の第１実施形態に係る電力変換装置に備えられた電圧指令補正器が発生する電圧指令の波形を示す図であり、（ａ）は変調率Ｍが０．９のとき、（ｂ）は変調率Ｍが０．５のときである。It is a figure which shows the waveform of the voltage command which the voltage command corrector with which the power converter device which concerns on 1st Embodiment of this invention was equipped, (a) is a modulation factor M of 0.9, (b) Is when the modulation factor M is 0.5. 本発明の第１実施形態に係る電力変換装置に備えられた電圧指令補正器における変調率Ｍとパラメータφの関係を表したグラフである。It is a graph showing the relationship between the modulation factor M and the parameter φ in the voltage command corrector provided in the power converter according to the first embodiment of the present invention. 本発明の第１実施形態に係る電力変換装置に備えられた電圧指令補正器における電圧指令と、それらが固定される電圧指令値－１、０、＋１に対して、電圧指令が固定される条件になる位相角範囲と、その長さを纏めた関係を表す図である。Conditions for the voltage command to be fixed with respect to the voltage commands in the voltage command corrector provided in the power converter according to the first embodiment of the present invention and the voltage command values −1, 0, +1 to which they are fixed It is a figure showing the relationship which put together the phase angle range which becomes and its length. 本発明の第１実施形態に係る電力変換装置に備えられたＰＷＭパルス発生器の回路構成を示すブロック図である。It is a block diagram which shows the circuit structure of the PWM pulse generator with which the power converter device which concerns on 1st Embodiment of this invention was equipped. 本発明の第１実施形態に係る電力変換装置に備えられたＰＷＭパルス発生器におけるキャリア三角波信号Ｖｃａｒ１およびＶｃａｒ２の波形を示す図であるIt is a figure which shows the waveform of the carrier triangular wave signals Vcar1 and Vcar2 in the PWM pulse generator with which the power converter device which concerns on 1st Embodiment of this invention was equipped. 本発明の第１実施形態に係る電力変換装置に備えられたインバータ主回路の回路構成を示す図である。It is a figure which shows the circuit structure of the inverter main circuit with which the power converter device which concerns on 1st Embodiment of this invention was equipped. 本発明の第１実施形態に係る電力変換装置に備えられたインバータ主回路におけるトランジスタと電圧指令との関係を示す図である。It is a figure which shows the relationship between the transistor and voltage command in the inverter main circuit with which the power converter device which concerns on 1st Embodiment of this invention was equipped. 本発明の第１実施形態に係る電力変換装置に備えられたインバータ主回路におけるＵ相レグの出力端子Ｕに出力される電圧波形を示す図であり、（ａ）は変調率Ｍが０．９のとき、（ｂ）は変調率Ｍが０．５のときの電圧波形である。It is a figure which shows the voltage waveform output to the output terminal U of the U-phase leg in the inverter main circuit with which the power converter device which concerns on 1st Embodiment of this invention was equipped, (a) is the modulation factor M of 0.9. (B) is a voltage waveform when the modulation factor M is 0.5. 本発明の第１実施形態に係る電力変換装置に備えられたインバータ主回路におけるＵ相レグの出力端子Ｕに出力される電圧波形の周波数スペクトルを示す図であり、（ａ）は変調率Ｍが０．９のとき、（ｂ）は変調率Ｍが０．５のときの周波数スペクトルである。It is a figure which shows the frequency spectrum of the voltage waveform output to the output terminal U of the U-phase leg in the inverter main circuit with which the power converter device which concerns on 1st Embodiment of this invention was equipped, (a) is the modulation factor M. When 0.9, (b) is a frequency spectrum when the modulation factor M is 0.5. 比較例の二相変調方法を適用した３レベルインバータから出力される電圧波形の周波数スペクトルを示す図であり、（ａ）は変調率Ｍが０．９のとき、（ｂ）は変調率Ｍが０．５のときの周波数スペクトルである。It is a figure which shows the frequency spectrum of the voltage waveform output from the 3 level inverter to which the two-phase modulation method of the comparative example is applied, (a) is when the modulation factor M is 0.9, (b) is the modulation factor M. It is a frequency spectrum at 0.5. 本発明の第１実施形態に係る電力変換装置の出力電圧に含まれている零相電圧の波形を示す図であり、（ａ）は変調率Ｍが０．９のとき、（ｂ）は変調率Ｍが０．５のときの波形である。It is a figure which shows the waveform of the zero phase voltage contained in the output voltage of the power converter device which concerns on 1st Embodiment of this invention, (a) is a modulation factor M, and (b) is modulation | alteration. It is a waveform when the rate M is 0.5. 比較例の二相変調方法を用いた３レベルインバータの出力電圧に含まれている零相電圧の波形を示す図であり、（ａ）は変調率Ｍが０．９のとき、（ｂ）は変調率Ｍが０．５のときの波形である。It is a figure which shows the waveform of the zero phase voltage contained in the output voltage of the 3-level inverter using the two-phase modulation method of a comparative example, (a) is the modulation factor M is 0.9, (b) is This is a waveform when the modulation factor M is 0.5. 本発明の第１実施形態に係る電力変換装置の零相電圧、および比較例の零相電圧の測定回路を示す図である。It is a figure which shows the measurement circuit of the zero phase voltage of the power converter device which concerns on 1st Embodiment of this invention, and the zero phase voltage of a comparative example. 本発明の第２実施形態に係る電力変換装置に備えるインバータ主回路の回路構成を示す図である。It is a figure which shows the circuit structure of the inverter main circuit with which the power converter device which concerns on 2nd Embodiment of this invention is equipped. 比較例の二相変調方法の電圧指令の一例を示す図である。It is a figure which shows an example of the voltage command of the two-phase modulation method of a comparative example. 比較例の二相変調方法の電圧指令を３レベルインバータに適用することで得られるＰＷＭ電圧波形を示す図である。It is a figure which shows the PWM voltage waveform obtained by applying the voltage command of the two-phase modulation method of a comparative example to a 3 level inverter.
　以下に本願の発明を実施するための形態（以下、「実施形態」と称す）を、図面を参照して説明する。 Hereinafter, modes for carrying out the invention of the present application (hereinafter referred to as “embodiments”) will be described with reference to the drawings.
（第１実施形態）
　本発明の第１実施形態に係るＰＷＭ制御方法を用いた電力変換装置（適宜、「インバータ」とも表記する）を図１～図１５を参照して説明する。また、ＰＷＭ制御方法の説明も兼ねる。 (First embodiment)
A power conversion apparatus using a PWM control method according to a first embodiment of the present invention (also referred to as “inverter” as appropriate) will be described with reference to FIGS. It also serves as an explanation of the PWM control method.
＜電力変換装置の回路構成＞
　図１は、本発明の第１実施形態に係る電力変換装置（インバータ）１０の回路構成を示すブロック図である。
　本発明のインバータ１０は、インバータ主回路（インバータ回路）１５と、このインバータ主回路１５を制御する制御回路１７を備えて構成されている。
　制御回路１７は、基本電圧指令発生器１１、電圧指令補正器１２、ＰＷＭパルス発生器１３、ゲートドライバ１４を備えて構成されている。
　また、ゲートドライバ１４は、複数のバッファ回路１６を備えて構成されている。
　まず、インバータ１０の概略の機能構成を、図１を参照して、前記の回路ブロック毎に説明する。 <Circuit configuration of power converter>
FIG. 1 is a block diagram showing a circuit configuration of a power converter (inverter) 10 according to the first embodiment of the present invention.
The inverter 10 of the present invention includes an inverter main circuit (inverter circuit) 15 and a control circuit 17 that controls the inverter main circuit 15.
The control circuit 17 includes a basic voltage command generator 11, a voltage command corrector 12, a PWM pulse generator 13, and a gate driver 14.
Further, the gate driver 14 includes a plurality of buffer circuits 16.
First, a schematic functional configuration of the inverter 10 will be described for each circuit block with reference to FIG.
　図１において、基本電圧指令発生器１１は、変調率Ｍと位相角θを入力し、三相の正弦波状の基本電圧指令Ｖｕ０、Ｖｖ０、Ｖｗ０（第１、第２、第３の基本正弦波）を、前記の変調率Ｍと位相角θに従って出力する。
　なお、変調率Ｍと位相角θ、および基本電圧指令発生器１１の詳細については、後記する。 In FIG. 1, a basic voltage command generator 11 receives a modulation factor M and a phase angle θ, and has three-phase sinusoidal basic voltage commands Vu0, Vv0, Vw0 (first, second, and third basic sine waves). ) In accordance with the modulation factor M and the phase angle θ.
Details of the modulation factor M, the phase angle θ, and the basic voltage command generator 11 will be described later.
　また、電圧指令補正器１２は、電圧指令補正器１２内で生成した零相信号Ｖｚを基本電圧指令Ｖｕ０、Ｖｖ０、Ｖｗ０に加算することで電圧指令Ｖｕ、Ｖｖ、Ｖｗ（第１、第２、第３の電圧指令）を発生する。
　なお、電圧指令補正器１２の詳細については、後記する。 Further, the voltage command corrector 12 adds the zero-phase signal Vz generated in the voltage command corrector 12 to the basic voltage commands Vu0, Vv0, Vw0, so that the voltage commands Vu, Vv, Vw (first, second, 3rd voltage command) is generated.
Details of the voltage command corrector 12 will be described later.
　ＰＷＭパルス発生器１３は、入力した電圧指令Ｖｕ、Ｖｖ、Ｖｗに基づいてＰＷＭパルス論理信号Ｐｕ１～Ｐｕ４、Ｐｖ１～Ｐｖ４、Ｐｗ１～Ｐｗ４を発生し、ゲートドライバ１４に供給する。なお、ＰＷＭパルス発生器１３の詳細については、後記する。 The PWM pulse generator 13 generates PWM pulse logic signals Pu1 to Pu4, Pv1 to Pv4, Pw1 to Pw4 based on the input voltage commands Vu, Vv, and Vw, and supplies them to the gate driver 14. Details of the PWM pulse generator 13 will be described later.
　ゲートドライバ１４は、複数のバッファ回路１６から構成され、これらの複数のバッファ回路１６によって、ＰＷＭパルス論理信号（Ｐｕ１～Ｐｕ４、Ｐｖ１～Ｐｖ４、Ｐｗ１～Ｐｗ４）をゲートドライブ用の差電圧電気信号（Ｇｕ１／Ｅｕ１～Ｇｕ４／Ｅｕ４、Ｇｖ１／Ｅｖ１～Ｇｖ４／Ｅｖ４、Ｇｗ１／Ｅｗ１～Ｇｗ４／Ｅｗ４）に変換し、インバータ主回路１５に供給する。ゲートドライバ１４とバッファ回路１６の詳細については、後記する。 The gate driver 14 is composed of a plurality of buffer circuits 16, by which the PWM pulse logic signals (Pu 1 to Pu 4, Pv 1 to Pv 4, Pw 1 to Pw 4) are transferred to the gate drive differential voltage electrical signal ( (Gu1 / Eu1 to Gu4 / Eu4, Gv1 / Ev1 to Gv4 / Ev4, Gw1 / Ew1 to Gw4 / Ew4) and supplied to the inverter main circuit 15. Details of the gate driver 14 and the buffer circuit 16 will be described later.
　インバータ主回路１５は、３レベルインバータ主回路であり、ＰＷＭパルス発生器１３からの信号によるＰＷＭ制御により、インバータ主回路１５の出力端子Ｕ、Ｖ、Ｗに３段階電圧（Ｅｄ、０、－Ｅｄ）のＰＷＭ電圧波形を発生する。なお、インバータ主回路１５の詳細については、後記する。 The inverter main circuit 15 is a three-level inverter main circuit, and three-stage voltages (Ed, 0, −Ed) are applied to the output terminals U, V, and W of the inverter main circuit 15 by PWM control using a signal from the PWM pulse generator 13. ) PWM voltage waveform is generated. Details of the inverter main circuit 15 will be described later.
　前記したように、基本電圧指令発生器１１、電圧指令補正器１２、ＰＷＭパルス発生器１３およびゲートドライバ１４は、インバータ主回路１５をＰＷＭ制御するための制御回路１７を構成している。
　制御回路１７、あるいは、その構成要素である基本電圧指令発生器１１、電圧指令補正器１２、ＰＷＭパルス発生器１３、ゲートドライバ１４のそれぞれの回路は、電子回路で構成するか、あるいは、マイクロプロセッサなどの制御用ＩＣ媒体としたソフトウェアプログラムで製作されている。 As described above, the basic voltage command generator 11, the voltage command corrector 12, the PWM pulse generator 13, and the gate driver 14 constitute a control circuit 17 for PWM control of the inverter main circuit 15.
Each circuit of the control circuit 17, or the basic voltage command generator 11, the voltage command corrector 12, the PWM pulse generator 13, and the gate driver 14, which are constituent elements thereof, is constituted by an electronic circuit or a microprocessor. It is manufactured by a software program as a control IC medium.
　以上の構成により、従来技術に比較して、零相電圧の振幅と、零相電流の小さい二相変調方法のＰＷＭ制御方法を用いた電力変換装置（インバータ）１０を具現化している。 With the above configuration, the power converter (inverter) 10 using the PWM control method of the two-phase modulation method in which the amplitude of the zero-phase voltage and the zero-phase current is small compared to the prior art is embodied.
＜各ブロックの構成、機能動作の詳細＞
　次に、インバータ１０に備えられた前記各ブロックの構成、機能動作の詳細について、次に、順に説明する。 <Details of configuration and functional operation of each block>
Next, the configuration and functional operation of each block provided in the inverter 10 will be described in order.
《基本電圧指令発生器１１》
　基本電圧指令発生器１１について説明する。
　基本電圧指令発生器１１は、次の（１）式に示すように、変調率Ｍと位相角θに従って定義される正弦波状の基本電圧指令Ｖｕ０、Ｖｖ０、Ｖｗ０（第１、第２、第３の基本正弦波）を発生し、出力する。
Ｖｕ０＝Ｍ×ｓｉｎ（θ）
Ｖｖ０＝Ｍ×ｓｉｎ（θ－１２０°）
Ｖｗ０＝Ｍ×ｓｉｎ（θ－２４０°）　・・・（１）
　（１）式において、変調率Ｍは、０～２／√３の値で任意に可変することができる。
　また、位相角θには、時間ｔに比例して増加する関数が与えられ、基本電圧指令の基本周波数をｆ１とすると、度数表記のθに対してθ＝３６０×ｆ１×ｔとなる。なお、これは弧度法ラジアンのθ＝２×π×ｆ１×ｔの表記に対応する。 << Basic voltage command generator 11 >>
The basic voltage command generator 11 will be described.
The basic voltage command generator 11 has sinusoidal basic voltage commands Vu0, Vv0, Vw0 (first, second, third) defined according to the modulation factor M and the phase angle θ, as shown in the following equation (1). Basic sine wave) is generated and output.
Vu0 = M × sin (θ)
Vv0 = M × sin (θ−120 °)
Vw0 = M × sin (θ−240 °) (1)
In the equation (1), the modulation factor M can be arbitrarily changed by a value of 0 to 2 / √3.
Further, the phase angle θ is given with a function that increases in proportion to the time t. When the basic frequency of the basic voltage command is f1, θ = 360 × f1 × t with respect to θ in frequency notation. This corresponds to the notation of arc = 2 radians θ = 2 × π × f1 × t.
《電圧指令補正器１２》
　次に、図１に示した電圧指令補正器１２の詳しい構成を、図２を参照して、説明する。
　図２は、本発明の第１実施形態に係る電力変換装置（インバータ）１０に備えられた電圧指令補正器１２の回路構成を示すブロック図である。
　図２において、電圧指令補正器１２は、最大値選択器（Ｍａｘ）２０、２６と、最小値選択器（Ｍｉｎ）２１、２５と、加算器２３、２７、２８、２９と、減算器２２、２４とを備えて構成されている。
　なお、最小値選択器２５と最大値選択器２６とを備えて、中央値選択器２０１が構成されている。 << Voltage command corrector 12 >>
Next, a detailed configuration of the voltage command corrector 12 shown in FIG. 1 will be described with reference to FIG.
FIG. 2 is a block diagram showing a circuit configuration of the voltage command corrector 12 provided in the power converter (inverter) 10 according to the first embodiment of the present invention.
In FIG. 2, the voltage command corrector 12 includes maximum value selectors (Max) 20 and 26, minimum value selectors (Min) 21 and 25, adders 23, 27, 28 and 29, a subtractor 22, 24.
The median value selector 201 includes the minimum value selector 25 and the maximum value selector 26.
　最大値選択器２０および最小値選択器２１は、基本電圧指令Ｖｕ０、Ｖｖ０、Ｖｗ０を入力している。
　最大値選択器２０は、時間の推移とともに変化する基本電圧指令Ｖｕ０、Ｖｖ０、Ｖｗ０の最大値Ｖａを出力する。
　また、最小値選択器２１は、基本電圧指令Ｖｕ０、Ｖｖ０、Ｖｗ０の最小値Ｖｂを出力する。 The maximum value selector 20 and the minimum value selector 21 receive basic voltage commands Vu0, Vv0, and Vw0.
The maximum value selector 20 outputs the maximum value Va of the basic voltage commands Vu0, Vv0, Vw0 that change with time.
Further, the minimum value selector 21 outputs the minimum value Vb of the basic voltage commands Vu0, Vv0, Vw0.
　減算器２２は、＋１から最大値Ｖａの減算を行い、（１－Ｖａ）の信号を生成する。
　加算器２３は、最大値Ｖａと最小値Ｖｂの加算を行い、（Ｖａ＋Ｖｂ）の信号を生成する。
　減算器２４は、－１から最小値Ｖｂの減算を行い、（－１－Ｖｂ）の信号を生成する。 The subtractor 22 subtracts the maximum value Va from +1 to generate a signal (1-Va).
The adder 23 adds the maximum value Va and the minimum value Vb to generate a signal (Va + Vb).
The subtractor 24 subtracts the minimum value Vb from −1 to generate a signal of (−1−Vb).
　最小値選択器２５は、（１－Ｖａ）と（Ｖａ＋Ｖｂ）との小さい方の値を選択して出力する。
　最大値選択器２６は、前記の最小値選択器２５の出力信号と、（－１－Ｖｂ）との大きい方の値を選択して出力する。
　この最小値選択器２５と最大値選択器２６の直列構成は、中央値選択器２０１として機能し、（１－Ｖａ）、（Ｖａ＋Ｖｂ）、（－１－Ｖｂ）の信号のうち中央値（＝２番目に大きい値＝２番目に小さい値）を選択して出力する構成となっている。
　なお、最大値選択器２６の信号は、次に記すように、三相を構成する正弦波状の基本電圧指令Ｖｕ０、Ｖｖ０、Ｖｗ０のそれぞれに、等しく加えるので、三相を構成する正弦波状の基本電圧指令Ｖｕ０、Ｖｖ０、Ｖｗ０の零相成分に相当する。したがって、最大値選択器２６の出力信号を零相信号Ｖｚと称する。 The minimum value selector 25 selects and outputs the smaller one of (1−Va) and (Va + Vb).
The maximum value selector 26 selects and outputs the larger value of the output signal of the minimum value selector 25 and (−1−Vb).
This series configuration of the minimum value selector 25 and the maximum value selector 26 functions as the median value selector 201, and among the signals (1-Va), (Va + Vb), (−1−Vb), the median value (= The second largest value = the second smallest value) is selected and output.
The signal of the maximum value selector 26 is equally applied to each of the sine wave basic voltage commands Vu0, Vv0, and Vw0 constituting the three phases, as will be described below, so that the sine wave basics constituting the three phases are applied. This corresponds to the zero phase component of the voltage commands Vu0, Vv0, Vw0. Therefore, the output signal of the maximum value selector 26 is referred to as a zero phase signal Vz.
　加算器２７、２８、２９は、基本電圧指令Ｖｕ０、Ｖｖ０、Ｖｗ０（第１、第２、第３の基本正弦波）に零相信号Ｖｚを加算して、それぞれ電圧指令Ｖｕ、Ｖｖ、Ｖｗを出力する。
　つまり、電圧指令Ｖｕ、Ｖｖ、Ｖｗは、三相を構成する正弦波状の基本電圧指令Ｖｕ０、Ｖｖ０、Ｖｗ０に対して、零相信号Ｖｚの分だけ、シフトした構成となっている。
　なお、電圧指令Ｖｕ、Ｖｖ、Ｖｗは、零相信号Ｖｚの分だけ、それぞれシフトしているので正弦波形とは異なるが、電圧指令Ｖｕ、Ｖｖ、Ｖｗにおける線間電圧（Ｖｕ－Ｖｖ）、（Ｖｖ－Ｖｗ）、（Ｖｗ－Ｖｕ）は、それぞれ零相信号Ｖｚが打ち消し合って、三相の正弦波を構成する。そのため、線間電圧を用いれば、モータなどの三相負荷を支障なく駆動できる。 The adders 27, 28, and 29 add the zero-phase signal Vz to the basic voltage commands Vu0, Vv0, and Vw0 (first, second, and third basic sine waves) and respectively add the voltage commands Vu, Vv, and Vw. Output.
That is, the voltage commands Vu, Vv, and Vw are shifted from the sinusoidal basic voltage commands Vu0, Vv0, and Vw0 constituting the three phases by the zero-phase signal Vz.
The voltage commands Vu, Vv, and Vw are different from the sine waveform because they are shifted by the zero-phase signal Vz, but the line voltages (Vu−Vv), ( Vv−Vw) and (Vw−Vu) constitute a three-phase sine wave by canceling the zero-phase signal Vz. Therefore, if the line voltage is used, a three-phase load such as a motor can be driven without any trouble.
［零相電圧指令に関連する各信号波形］
　次に、零相電圧指令に関連する各信号波形について説明する。
　図３は、本発明の第１実施形態に係る電力変換装置に備えられた電圧指令補正器の位相角θ＝０°～３６０°における零相信号Ｖｚおよび（１－Ｖａ）、（Ｖａ＋Ｖｂ）、（－１－Ｖｂ）の各信号のそれぞれの波形を示す図であり、（ａ）は変調率Ｍが０．９のとき、（ｂ）は変調率Ｍが０．５のときである。
　また、横軸は位相角θ（ｄｅｇ．）であり、縦軸は各信号の値である。ただし、縦軸は、基本電圧指令Ｖｕ０、Ｖｖ０、Ｖｗ０の最大値で正規化している。 [Each signal waveform related to zero phase voltage command]
Next, each signal waveform related to the zero phase voltage command will be described.
FIG. 3 shows a zero-phase signal Vz and (1-Va), (Va + Vb) at a phase angle θ = 0 ° to 360 ° of the voltage command corrector provided in the power conversion device according to the first embodiment of the present invention, It is a figure which shows each waveform of each signal of (-1-Vb), (a) is when the modulation factor M is 0.9, (b) is when the modulation factor M is 0.5.
The horizontal axis is the phase angle θ (deg.), And the vertical axis is the value of each signal. However, the vertical axis is normalized by the maximum value of the basic voltage commands Vu0, Vv0, Vw0.
　図３（ａ）において、変調率Ｍが０．９であって、太い実線が零相信号（零相電圧指令）Ｖｚ、細い破線が（１－Ｖａ）、（Ｖａ＋Ｖｂ）、（－１－Ｖｂ）である。図３（ａ）では、零相信号Ｖｚは、（１－Ｖａ）、（Ｖａ＋Ｖｂ）、（－１－Ｖｂ）の中央値から選ばれていることが示されている。 In FIG. 3A, the modulation factor M is 0.9, the thick solid line is the zero phase signal (zero phase voltage command) Vz, and the thin broken lines are (1-Va), (Va + Vb), (−1−Vb). ). FIG. 3A shows that the zero-phase signal Vz is selected from the median values of (1−Va), (Va + Vb), and (−1−Vb).
　図３（ｂ）において、変調率Ｍが０．５であって、太い実線が零相信号（零相電圧指令）Ｖｚ、細い破線が（１－Ｖａ）、（－１－Ｖｂ）である。
　図３（ｂ）では、位相角θ＝０°～３６０°の全期間で、１－Ｖａ＞Ｖａ＋Ｖｂ＞－１－Ｖｂの関係にあり、零相信号Ｖｚは常に中央値である（Ｖａ＋Ｖｂ）の値となることが示されている。
　なお、Ｖｚ＝（Ｖａ＋Ｖｂ）の特性線は、直線にも見えるが、実際は、緩やかな曲線である。 In FIG. 3B, the modulation factor M is 0.5, the thick solid line is the zero-phase signal (zero-phase voltage command) Vz, and the thin broken lines are (1-Va) and (-1-Vb).
In FIG. 3B, the relationship of 1−Va> Va + Vb> −1−Vb is established over the entire period of the phase angle θ = 0 ° to 360 °, and the zero-phase signal Vz always has the median value (Va + Vb). It is shown to be a value.
Note that the characteristic line of Vz = (Va + Vb) appears to be a straight line, but is actually a gentle curve.
　図３（ａ）のように（Ｖａ＋Ｖｂ）が（－１－Ｖｂ）および（１－Ｖａ）と交差する場合と、図３（ｂ）のように交差しない場合は、変調率Ｍ＝２／３が境界となる。したがって、図３（ｂ）のように（Ｖａ＋Ｖｂ）が常に中央値となる変調率の条件は０≦Ｍ≦２／３であり、２／３＜Ｍ≦２／√３では、図３（ａ）のように中央値は入れ替わる。
　なお、Ｍ＝２／√３は、線間電圧が歪まない境界の変調率である。 When (Va + Vb) intersects (−1−Vb) and (1−Va) as shown in FIG. 3A and when not intersected as shown in FIG. 3B, the modulation factor M = 2/3 Is the boundary. Therefore, as shown in FIG. 3B, the condition of the modulation rate at which (Va + Vb) is always the median is 0 ≦ M ≦ 2/3, and when 2/3 <M ≦ 2 / √3, FIG. The median is swapped as in
Note that M = 2 / √3 is a modulation rate at a boundary where the line voltage is not distorted.
［電圧指令補正器１２が発生する電圧指令Ｖｕ、Ｖｖ、Ｖｗの波形］
　次に、電圧指令補正器１２が発生する電圧指令Ｖｕ、Ｖｖ、Ｖｗの波形について説明する。
　図４は、本発明の第１実施形態に係る電力変換装置に備えられた電圧指令補正器１２が発生する電圧指令Ｖｕ、Ｖｖ、Ｖｗの波形を示す図であり、（ａ）は変調率Ｍが０．９のとき、（ｂ）は変調率Ｍが０．５のときである。
　また、横軸は位相角θ（ｄｅｇ．）であり、縦軸は各信号の値である。ただし、縦軸は、電圧指令Ｖｕ、Ｖｖ、Ｖｗの最大値で正規化している。
　また、太い実線がＶｕ、細い実線がＶｖ、細い破線がＶｗである。
　電圧指令Ｖｕ、Ｖｖ、Ｖｗは、前記したように、基本電圧指令Ｖｕ０、Ｖｖ０、Ｖｗ０のそれぞれに零相信号Ｖｚが加えられてシフトしているので、正弦波形とは異なる波形となっている。 [Waveforms of voltage commands Vu, Vv, Vw generated by the voltage command corrector 12]
Next, the waveforms of the voltage commands Vu, Vv, Vw generated by the voltage command corrector 12 will be described.
FIG. 4 is a diagram illustrating waveforms of voltage commands Vu, Vv, and Vw generated by the voltage command corrector 12 included in the power conversion device according to the first embodiment of the present invention. (B) is when the modulation factor M is 0.5.
The horizontal axis is the phase angle θ (deg.), And the vertical axis is the value of each signal. However, the vertical axis is normalized by the maximum value of the voltage commands Vu, Vv, Vw.
A thick solid line is Vu, a thin solid line is Vv, and a thin broken line is Vw.
As described above, the voltage commands Vu, Vv, and Vw are shifted by adding the zero-phase signal Vz to each of the basic voltage commands Vu0, Vv0, and Vw0, and therefore have different waveforms from the sine waveform.
　図４（ａ）において、電圧指令Ｖｕ、Ｖｖ、Ｖｗは、位相角θ＝０°～３６０°の間に、電圧指令値が＋１（最大値）、－１（最小値）、および０の３つの電圧指令値で固定される期間が存在することが示されている。 In FIG. 4A, the voltage commands Vu, Vv, and Vw have voltage command values of +1 (maximum value), −1 (minimum value), and 0 between phase angles θ = 0 ° to 360 °. It is shown that there is a period that is fixed at one voltage command value.
　図４（ｂ）において、電圧指令Ｖｕ、Ｖｖ、Ｖｗは、位相角θ＝０°～３６０°の間に電圧指令値が０の値で固定される期間が存在することが示されている。 FIG. 4B shows that the voltage commands Vu, Vv, and Vw have a period in which the voltage command value is fixed at a value of 0 between the phase angles θ = 0 ° to 360 °.
　図４（ａ）のように電圧指令Ｖｕ、Ｖｖ、Ｖｗが３つの電圧指令値で固定される変調率の条件は２／３＜Ｍ≦２／√３であり、０≦Ｍ≦２／３では、図４（ｂ）のように電圧指令値が０の値でのみの固定となる。 As shown in FIG. 4A, the condition of the modulation rate at which the voltage commands Vu, Vv, and Vw are fixed at three voltage command values is 2/3 <M ≦ 2 / √3, and 0 ≦ M ≦ 2/3. Then, as shown in FIG. 4B, the voltage command value is fixed only at a value of zero.
　パラメータφは変調率Ｍに依存して決まる関数φ（Ｍ）であり、以下の（２）式で与えられる。
０≦Ｍ≦２／３のとき、
φ＝３０°
２／３＜Ｍ≦２／√３のとき、
Figure JPOXMLDOC01-appb-M000002
 　ただし、φは度数法で定義する。 The parameter φ is a function φ (M) determined depending on the modulation factor M, and is given by the following equation (2).
When 0 ≦ M ≦ 2/3,
φ = 30 °
When 2/3 <M ≦ 2 / √3,
Figure JPOXMLDOC01-appb-M000002
 However, φ is defined by the frequency method.
［変調率Ｍとパラメータφの関係］
　次に、変調率Ｍとパラメータφの関係について説明する。
　図５は、本発明の第１実施形態に係る電力変換装置に備えられた電圧指令補正器における変調率Ｍとパラメータφの関係を表したグラフである。図５の横軸は、変調率Ｍであり、縦軸は、パラメータφ（ｄｅｇ．）である。
　図５において、（２）式に従い、Ｍが２／３よりも小さい範囲では、φは３０°（π／６ラジアン）で一定であり、Ｍが２／３よりも大きい範囲では、φはＭの関数であって、φ（Ｍ）とも表記する。前記したように、φ＝φ（Ｍ）は、（２）式で表記され、Ｍの増加に従って単調に減少し、Ｍ＝２／√３で０となる。 [Relationship between modulation factor M and parameter φ]
Next, the relationship between the modulation factor M and the parameter φ will be described.
FIG. 5 is a graph showing the relationship between the modulation factor M and the parameter φ in the voltage command corrector provided in the power converter according to the first embodiment of the present invention. The horizontal axis of FIG. 5 is the modulation factor M, and the vertical axis is the parameter φ (deg.).
In FIG. 5, according to the formula (2), φ is constant at 30 ° (π / 6 radians) when M is smaller than 2/3, and φ is M when M is larger than 2/3. Which is also expressed as φ (M). As described above, φ = φ (M) is expressed by equation (2), and decreases monotonously as M increases, and becomes 0 when M = 2 / √3.
［電圧指令が固定される条件になる位相角範囲］
　次に、電圧指令が固定される条件になる位相角範囲について説明する。
　図６は、本発明の第１実施形態に係る電力変換装置に備えられた電圧指令補正器における電圧指令Ｖｕ、Ｖｖ、Ｖｗと、それらが固定される電圧指令値－１、０、＋１に対して、電圧指令が固定される条件になる位相角範囲と、その位相角範囲の長さを纏めた関係を表す図である。なお、位相角範囲は、度数法（ｄｅｇ.）で表記している。
　図６において、電圧指令Ｖｕについては、電圧指令値が＋１に固定される位相角θの範囲は、６０°＋φ＜θ＜１２０°－φ、電圧指令値が０に固定される位相角θの範囲は、０≦θ＜φ、１８０°－φ＜θ＜１８０°＋φ、３６０°－φ＜３６０°、電圧指令値が－１に固定される位相角θの範囲は、２４０°＋φ＜θ＜３００°－φである。 [Phase angle range under which the voltage command is fixed]
Next, the phase angle range that is a condition for fixing the voltage command will be described.
FIG. 6 shows voltage commands Vu, Vv, Vw in the voltage command corrector provided in the power converter according to the first embodiment of the present invention, and voltage command values −1, 0, +1 to which they are fixed. It is a figure showing the relationship which put together the length of the phase angle range used as the conditions where a voltage command is fixed, and the phase angle range. Note that the phase angle range is expressed in the power method (deg.).
In FIG. 6, for the voltage command Vu, the range of the phase angle θ in which the voltage command value is fixed to +1 is 60 ° + φ <θ <120 ° −φ, and the phase angle θ in which the voltage command value is fixed to 0. The range is 0 ≦ θ <φ, 180 ° −φ <θ <180 ° + φ, 360 ° −φ <360 °, and the range of the phase angle θ in which the voltage command value is fixed to −1 is 240 ° + φ <θ <300 ° -φ.
　その結果、電圧指令値が－１、０、－１に固定される位相角範囲の長さは、それぞれ、６０°－２φ、４φ、６０°－２φとなり、これらを合計した長さは、
（６０°－２φ）＋（４φ）＋（６０°－２φ）＝１２０°
となり、φに依らず一定となる。
　また、各電圧指令Ｖｖ、Ｖｗついても、位相角θがそれぞれ１２０°、２４０°シフトしただけで固定される位相角は、Ｖｕと同様であり、その結果、電圧指令が固定される位相角範囲の長さの合計は１２０°である。 As a result, the lengths of the phase angle ranges in which the voltage command value is fixed to −1, 0, −1 are 60 ° −2φ, 4φ, and 60 ° −2φ, respectively.
(60 ° -2φ) + (4φ) + (60 ° -2φ) = 120 °
And becomes constant regardless of φ.
For each voltage command Vv, Vw, the phase angle that is fixed only by shifting the phase angle θ by 120 ° and 240 ° is the same as Vu, and as a result, the phase angle range in which the voltage command is fixed. The total length of is 120 °.
　したがって、変調率Ｍに依存せずに、全体の１／３（＝１２０°／３６０°）の期間においてスイッチングを停止し、スイッチング回数を１／３だけ減じることができるので、スイッチング損失（消費電力）を減じる効果がある。
　なお、変調率Ｍが２／３以下の場合には、φが３０°となるため、図６に示した表の上では電圧指令値＋１および－１に固定される位相角長さは０になる。つまり電圧指令Ｖｕ、Ｖｖ、Ｖｗは電圧指令値＋１および－１には固定されなくなることを意味している。 Therefore, switching can be stopped in the entire 1/3 (= 120 ° / 360 °) period without depending on the modulation factor M, and the number of switching can be reduced by 1/3. ).
When the modulation factor M is 2/3 or less, φ is 30 °. Therefore, the phase angle length fixed to the voltage command values +1 and −1 is 0 on the table shown in FIG. Become. That is, the voltage commands Vu, Vv, and Vw are not fixed to the voltage command values +1 and −1.
《ＰＷＭパルス発生器１３》
　次に、ＰＷＭパルス発生器１３の詳細を図７と図８を参照して説明する。
　図７は、本発明の第１実施形態に係る電力変換装置に備えられたＰＷＭパルス発生器１３の回路構成を示すブロック図である。
　図７において、ＰＷＭパルス発生器１３は、三角波発生器３１、減算器３２、コンパレータ３３ｕ、３３ｖ、３３ｗ、３４ｕ、３４ｖ、３４ｗ、論理反転回路３５ｕ、３５ｖ、３５ｗ、３６ｕ、３６ｖ、３６ｗ、ＯＮディレイ回路３７によって構成されている。 << PWM pulse generator 13 >>
Next, details of the PWM pulse generator 13 will be described with reference to FIGS.
FIG. 7 is a block diagram showing a circuit configuration of the PWM pulse generator 13 provided in the power conversion device according to the first embodiment of the present invention.
In FIG. 7, the PWM pulse generator 13 includes a triangular wave generator 31, a subtractor 32, comparators 33u, 33v, 33w, 34u, 34v, 34w, logic inversion circuits 35u, 35v, 35w, 36u, 36v, 36w, and ON delay. The circuit 37 is configured.
　三角波発生器３１は、図８に示すキャリア三角波信号Ｖｃａｒ１（第１のキャリア三角波信号）を発生し、減算器はＶｃａｒ１の値から１を減算することでキャリア三角波信号Ｖｃａｒ２（第２のキャリア三角波信号）を発生する。なお、キャリア三角波信号Ｖｃａｒ１、Ｖｃａｒ２の詳しい波形は、図８を参照して後記する。 The triangular wave generator 31 generates the carrier triangular wave signal Vcar1 (first carrier triangular wave signal) shown in FIG. 8, and the subtracter subtracts 1 from the value of Vcar1 to thereby generate the carrier triangular wave signal Vcar2 (second carrier triangular wave signal). ). The detailed waveforms of the carrier triangular wave signals Vcar1 and Vcar2 will be described later with reference to FIG.
　図７において、コンパレータ３３ｕは、電圧指令Ｖｕと三角波（キャリア三角波信号）Ｖｃａｒ１を比較する。また、コンパレータ３４ｕは、電圧指令Ｖｕと三角波Ｖｃａｒ２を比較する。
　論理反転回路３５ｕは、コンパレータ３３ｕの信号を入力して、その反転信号を出力する。また、論理反転回路３６ｕは、コンパレータ３４ｕの信号を入力して、その反転信号を出力する。
　そして、コンパレータ３３ｕ、３４ｕと、論理反転回路３５ｕ、３６ｕと組み合わせることで４種類のＰＷＭパルス論理信号Ｐｕ１～Ｐｕ４を発生する。なお、ＰＷＭパルス論理信号Ｐｕ１～Ｐｕ４の出力に際しては、ＯＮディレイ回路３７を介するが、ＯＮディレイ回路３７の機能については後記する。 In FIG. 7, the comparator 33u compares the voltage command Vu with a triangular wave (carrier triangular wave signal) Vcar1. Further, the comparator 34u compares the voltage command Vu with the triangular wave Vcar2.
The logic inverting circuit 35u receives the signal from the comparator 33u and outputs the inverted signal. The logic inversion circuit 36u receives the signal from the comparator 34u and outputs the inverted signal.
Then, four types of PWM pulse logic signals Pu1 to Pu4 are generated by combining with the comparators 33u and 34u and the logic inverting circuits 35u and 36u. The PWM pulse logic signals Pu1 to Pu4 are output via the ON delay circuit 37. The function of the ON delay circuit 37 will be described later.
　コンパレータ３３ｕ、３４ｕは、通常、周期１／ｆｃ毎にＰｕ１～Ｐｕ４のいずれかにパルスを発生する。しかし、三角波（キャリア三角波信号）のＶｃａｒ１およびＶｃａｒ２の振幅が１よりわずか（所定の値）に小さいことによって、電圧指令Ｖｕが＋１、０、－１の場合に限り、Ｐｕ１～Ｐｕ４にパルスは発生しない。なお、所定の値とは、電圧指令Ｖｕが＋１、０、－１の場合に限り、Ｐｕ１～Ｐｕ４にパルスは発生せず、かつ三角波の頂点が＋１（または０、または－１）に近い条件を満たし、かつノイズ等で誤動作しない程度の範囲で選択される値である。 The comparators 33u and 34u usually generate a pulse in any one of Pu1 to Pu4 every period 1 / fc. However, since the amplitudes of Vcar1 and Vcar2 of the triangular wave (carrier triangular wave signal) are slightly smaller than 1 (predetermined value), pulses are generated in Pu1 to Pu4 only when the voltage command Vu is +1, 0, -1. do not do. Note that the predetermined value is a condition that only when the voltage command Vu is +1, 0, −1, no pulse is generated in Pu1 to Pu4, and the apex of the triangular wave is close to +1 (or 0, or −1). And a value selected within a range that does not malfunction due to noise or the like.
　コンパレータ３３ｖ、３４ｖ、論理反転回路３５ｖ、３６ｖの構成は、前記したコンパレータ３３ｕ、３４ｕ、論理反転回路３５ｕ、３６ｕの構成と基本的に同様であるので、重複する説明は省略する。
　そのため、コンパレータ３３ｖ、３４ｖ、論理反転回路３５ｖ、３６ｖを組み合わせた回路は、電圧指令Ｖｖに基づいてＰＷＭパルス論理信号Ｐｖ１～Ｐｖ４を発生する。
　同様に、コンパレータ３３ｗ、３４ｗ、論理反転回路３５ｗ、３６ｗを組み合わせた回路は、電圧指令Ｖｗに基づいてＰＷＭパルス論理信号Ｐｗ１～Ｐｗ４を発生する。 The configurations of the comparators 33v and 34v and the logic inverting circuits 35v and 36v are basically the same as the configurations of the comparators 33u and 34u and the logic inverting circuits 35u and 36u described above, and thus redundant description is omitted.
Therefore, a circuit combining the comparators 33v and 34v and the logic inverting circuits 35v and 36v generates the PWM pulse logic signals Pv1 to Pv4 based on the voltage command Vv.
Similarly, a circuit combining comparators 33w and 34w and logic inversion circuits 35w and 36w generates PWM pulse logic signals Pw1 to Pw4 based on voltage command Vw.
　また、ＯＮディレイ回路３７は、ＰＷＭパルス論理信号がＨレベルになる際の時間をわずかに遅くするためのディレイ回路である。ただし、ＰＷＭパルス論理信号がＬレベルになる際には、速やかにＬレベルにする。
　このＯＮディレイ回路３７に、ＨレベルとＬレベルとになる場合において、ディレイ時間に差を設けることによって、ＰＷＭパルス論理信号が供給されるトランジスタのスイッチング動作にデッドタイムを設け、信号遅延のばらつきなどによる誤短絡を防止する。 The ON delay circuit 37 is a delay circuit for slightly delaying the time when the PWM pulse logic signal becomes H level. However, when the PWM pulse logic signal becomes L level, it is quickly made L level.
When the ON delay circuit 37 is at the H level and the L level, a delay time is provided, thereby providing a dead time for the switching operation of the transistor to which the PWM pulse logic signal is supplied, and variations in signal delay, etc. Prevents accidental short circuit.
［キャリア三角波信号Ｖｃａｒ１、Ｖｃａｒ２の波形］
　次に、キャリア三角波信号Ｖｃａｒ１およびＶｃａｒ２について説明する。
　図８は、本発明の第１実施形態に係る電力変換装置に備えられたＰＷＭパルス発生器におけるキャリア三角波信号Ｖｃａｒ１およびＶｃａｒ２の波形を示す図である。横軸は時間の推移であり、縦軸は信号の電圧であり、正規化している。
　図８において、キャリア三角波信号Ｖｃａｒ１およびＶｃａｒ２は、周波数がＰＷＭキャリア周波数ｆｃであって、電圧の振幅が１よりわずか（所定の値）に小さい三角波である。ただし、キャリア三角波信号Ｖｃａｒ１は、０～＋１の間を、キャリア三角波信号Ｖｃａｒ２は、－１～０の間をスイープする。
　また、白丸の部分では三角波の実線がわずかに破線に達していないことを示している。
　すなわち、前記したように、Ｖｃａｒ１は０と＋１間、Ｖｃａｒ２は－１と０間の値を取りうる三角波であるが、＋１、０、－１の値は取らない。 [Waveforms of carrier triangular wave signals Vcar1, Vcar2]
Next, carrier triangular wave signals Vcar1 and Vcar2 will be described.
FIG. 8 is a diagram showing waveforms of carrier triangular wave signals Vcar1 and Vcar2 in the PWM pulse generator provided in the power conversion device according to the first embodiment of the present invention. The horizontal axis is the time transition, and the vertical axis is the signal voltage, normalized.
In FIG. 8, carrier triangular wave signals Vcar1 and Vcar2 are triangular waves having a frequency of PWM carrier frequency fc and a voltage amplitude slightly smaller than 1 (predetermined value). However, the carrier triangular wave signal Vcar1 sweeps between 0 and +1, and the carrier triangular wave signal Vcar2 sweeps between −1 and 0.
Further, the white circle portion indicates that the solid line of the triangular wave does not reach the broken line slightly.
That is, as described above, Vcar1 is a triangular wave that can take a value between 0 and +1 and Vcar2 can take a value between -1 and 0, but does not take a value of +1, 0, or -1.
《ゲートドライバ１４とバッファ回路１６》
　図１に戻って、ゲートドライバ１４とバッファ回路１６についてより詳しく説明する。
　ゲートドライバ１４は、図１に示すように、ＰＷＭパルス論理信号Ｐｕ１～Ｐｕ４、Ｐｖ１～Ｐｖ４、Ｐｗ１～Ｐｗ４を、互いにアイソレーションされた差電圧電気信号に変換する１２個のバッファ回路１６で構成されている。
　ＰＷＭパルス論理信号（Ｐｕ１～Ｐｕ４、Ｐｖ１～Ｐｖ４、Ｐｗ１～Ｐｗ４）をゲートドライブ用の差電圧電気信号（Ｇｕ１／Ｅｕ１～Ｇｕ４／Ｅｕ４、Ｇｖ１／Ｅｖ１～Ｇｖ４／Ｅｖ４、Ｇｗ１／Ｅｗ１～Ｇｗ４／Ｅｗ４）に変換し、インバータ主回路１５に供給する。 << Gate Driver 14 and Buffer Circuit 16 >>
Returning to FIG. 1, the gate driver 14 and the buffer circuit 16 will be described in more detail.
As shown in FIG. 1, the gate driver 14 includes 12 buffer circuits 16 that convert PWM pulse logic signals Pu1 to Pu4, Pv1 to Pv4, and Pw1 to Pw4 into differential voltage electrical signals that are isolated from each other. ing.
The PWM pulse logic signals (Pu1 to Pu4, Pv1 to Pv4, Pw1 to Pw4) are converted into gate drive differential voltage electrical signals (Gu1 / Eu1 to Gu4 / Eu4, Gv1 / Ev1 to Gv4 / Ev4, Gw1 / Ew1 to Gw4 / Ew4). ) And supplied to the inverter main circuit 15.
　なお、ゲートドライバ１４において、例えばＰｕ１の信号は、バッファ回路１６を介するとバッファ回路１６から差電圧電気信号として、Ｇｕ１とＥｕ１との間に差電圧を発生させ、２本の信号として出力する。他のＰＷＭパルス論理信号についても同様であるので重複する説明は省略する。この信号の使い方については、図９を参照して後記する。
　また、バッファ回路１６には、フォトカプラなどのアイソレータを採用することで出力信号を互いに絶縁させることができ、またプッシュプル回路などの低インピーダンス出力回路を採用することで、高いゲートドライブ能力を有することができる。 In the gate driver 14, for example, the Pu1 signal is generated as a differential voltage electric signal from the buffer circuit 16 via the buffer circuit 16, and a differential voltage is generated between Gu1 and Eu1 and output as two signals. The same applies to the other PWM pulse logic signals, and therefore redundant description is omitted. The use of this signal will be described later with reference to FIG.
Also, the buffer circuit 16 can isolate output signals from each other by adopting an isolator such as a photocoupler, and has a high gate drive capability by employing a low impedance output circuit such as a push-pull circuit. be able to.
《インバータ主回路１５》
　次に、インバータ主回路１５の詳細を図９～図１１を参照して説明する。
　図９は、本発明の第１実施形態に係る電力変換装置に備えられたインバータ主回路１５の回路構成を示す図である。
　図９において、インバータ主回路１５は、正極の直流電源Ｐ（ノードＰ）と負極の直流電源Ｎ（ノードＮ）と中性点の直流電源Ｏ（ノードＯ）を備えている。中性点のノードＯは、グランドに接地されることもある。
　正極の直流電源Ｐと中性点の直流電源Ｏとの間に、コンデンサＣ１が接続され、Ｅｄの電圧が印加されている。
　また、中性点の直流電源Ｏと負極の直流電源Ｎとの間に、コンデンサＣ２が接続され、Ｅｄの電圧が印加されている。
　また、正極の直流電源Ｐと負極の直流電源Ｎとの間に、トランジスタとダイオードを備えて構成されるＵ相レグ、Ｖ相レグ、Ｗ相レグが三相に対応して、並列構成で構成されている。 << Inverter main circuit 15 >>
Next, details of the inverter main circuit 15 will be described with reference to FIGS.
FIG. 9 is a diagram showing a circuit configuration of the inverter main circuit 15 provided in the power conversion device according to the first embodiment of the present invention.
In FIG. 9, the inverter main circuit 15 includes a positive DC power supply P (node P), a negative DC power supply N (node N), and a neutral DC power supply O (node O). The node O at the neutral point may be grounded.
A capacitor C1 is connected between the positive DC power supply P and the neutral DC power supply O, and the voltage of Ed is applied.
A capacitor C2 is connected between the neutral DC power supply O and the negative DC power supply N, and the voltage of Ed is applied.
In addition, a U-phase leg, a V-phase leg, and a W-phase leg configured by including a transistor and a diode between the positive DC power source P and the negative DC power source N are configured in a parallel configuration corresponding to three phases. Has been.
　Ｕ相レグは、トランジスタＱ１１～Ｑ１４とダイオードＤ１１～Ｄ１６を備えて構成されている。
　ＩＧＢＴ（Insulated Gate Bipolar Transistor）からなるトランジスタＱ１１～Ｑ１４は直列に接続され、トランジスタＱ１１のコレクタは正極の直流電源Ｐに接続され、トランジスタＱ１４のエミッタは負極の直流電源Ｎに接続されている。
　トランジスタＱ１２のエミッタとトランジスタＱ１３のコレクタは互いに接続され、かつＵ相レグとしての出力端子Ｕに接続されている。 The U-phase leg includes transistors Q11 to Q14 and diodes D11 to D16.
Transistors Q11 to Q14 made of IGBT (Insulated Gate Bipolar Transistor) are connected in series, the collector of the transistor Q11 is connected to a positive DC power supply P, and the emitter of the transistor Q14 is connected to a negative DC power supply N.
The emitter of the transistor Q12 and the collector of the transistor Q13 are connected to each other and to the output terminal U as a U-phase leg.
　また、ダイオードＤ１１～Ｄ１４は、トランジスタＱ１１～Ｑ１４にそれぞれ逆並列に接続されている。
　また、ダイオードＤ１５のアノードは中性点の直流電源Ｏに接続され、カソードはトランジスタＱ１１のエミッタとトランジスタＱ１２のコレクタの接続点に接続されている。
　また、ダイオードＤ１６のカソードは中性点の直流電源Ｏに接続され、アノードはトランジスタＱ１３のエミッタとトランジスタＱ１４のコレクタの接続点に接続されている。 The diodes D11 to D14 are connected in antiparallel to the transistors Q11 to Q14, respectively.
The anode of the diode D15 is connected to the DC power source O at the neutral point, and the cathode is connected to the connection point between the emitter of the transistor Q11 and the collector of the transistor Q12.
The cathode of the diode D16 is connected to a neutral direct current power source O, and the anode is connected to the connection point between the emitter of the transistor Q13 and the collector of the transistor Q14.
　ＩＧＢＴで構成されるトランジスタＱ１１のゲートとエミッタには、ゲートドライバ１４からの差電圧電気信号（Ｇｕ１／Ｅｕ１）として、それぞれＧｕ１とＥｕ１が印加されている。つまり、ゲートとエミッタ間の差電圧として信号を印加している。
　また、同様にトランジスタＱ１２のゲートとエミッタには、ゲートドライバ１４からの差電圧電気信号（Ｇｕ２／Ｅｕ２）として、それぞれＧｕ２とＥｕ２が印加されている。
　また、同様にトランジスタＱ１３のゲートとエミッタには、ゲートドライバ１４からの差電圧電気信号（Ｇｕ３／Ｅｕ３）として、それぞれＧｕ３とＥｕ３が印加されている。
　また、同様にトランジスタＱ１４のゲートとエミッタには、ゲートドライバ１４からの差電圧電気信号（Ｇｕ４／Ｅｕ４）として、それぞれＧｕ４とＥｕ４が印加されている。
　以上からＵ相レグが構成されている。 Gu1 and Eu1 are applied as a differential voltage electrical signal (Gu1 / Eu1) from the gate driver 14 to the gate and emitter of the transistor Q11 formed of an IGBT, respectively. That is, a signal is applied as a voltage difference between the gate and the emitter.
Similarly, Gu2 and Eu2 are applied to the gate and emitter of the transistor Q12 as the differential voltage electrical signal (Gu2 / Eu2) from the gate driver 14, respectively.
Similarly, Gu3 and Eu3 are applied to the gate and emitter of the transistor Q13 as differential voltage electrical signals (Gu3 / Eu3) from the gate driver 14, respectively.
Similarly, Gu4 and Eu4 are applied to the gate and emitter of the transistor Q14 as differential voltage electrical signals (Gu4 / Eu4) from the gate driver 14, respectively.
From the above, the U-phase leg is configured.
　Ｖ相も、同様にトランジスタＱ２１～Ｑ２４とダイオードＤ２１～Ｄ２６を備えて、それぞれＵ相のトランジスタＱ１１～Ｑ１４とダイオードＤ１１～Ｄ１６に対応して構成されている。
　また、トランジスタＱ２１～Ｑ２４には、それぞれ差電圧電気信号（Ｇｖ１／Ｅｖ１）、（Ｇｖ２／Ｅｖ２）、（Ｇｖ３／Ｅｖ３）、（Ｇｖ４／Ｅｖ４）がＵ相のトランジスタＱ１１～Ｑ１４と同様の関係で接続されている。 Similarly, the V phase includes transistors Q21 to Q24 and diodes D21 to D26, and is configured to correspond to the U phase transistors Q11 to Q14 and the diodes D11 to D16, respectively.
In addition, the transistors Q21 to Q24 have the same relationship as that of the U-phase transistors Q11 to Q14 in the differential voltage electrical signals (Gv1 / Ev1), (Gv2 / Ev2), (Gv3 / Ev3), and (Gv4 / Ev4), respectively. It is connected.
　Ｗ相も、同様にトランジスタＱ３１～Ｑ３４とダイオードＤ３１～Ｄ３６を備えて、それぞれＵ相のトランジスタＱ１１～Ｑ１４とダイオードＤ１１～Ｄ１６に対応して構成されている。
　また、トランジスタＱ３１～Ｑ３４には、それぞれ差電圧電気信号（Ｇｗ１／Ｅｗ１）、（Ｇｗ２／Ｅｗ２）、（Ｇｗ３／Ｅｗ３）、（Ｇｗ４／Ｅｗ４）がＵ相のトランジスタＱ１１～Ｑ１４と同様の関係で接続されている。 Similarly, the W phase includes transistors Q31 to Q34 and diodes D31 to D36, and is configured to correspond to the U phase transistors Q11 to Q14 and the diodes D11 to D16, respectively.
In addition, the transistors Q31 to Q34 have the same relationship between the differential voltage electrical signals (Gw1 / Ew1), (Gw2 / Ew2), (Gw3 / Ew3), and (Gw4 / Ew4) as the U-phase transistors Q11 to Q14, respectively. It is connected.
　以上の構成により、Ｕ相、Ｖ相、Ｗ相の各レグには、ノードＰから直流正電圧＋Ｅｄが、ノードＮから直流負電圧－Ｅｄが与えられている。また、ノードＯからは、零電圧（０電位）が与えられている。前記したように、ノードＰ－Ｏ間とノードＯ－Ｎ間にはコンデンサＣ１、Ｃ２が接続され、それぞれのノード間の直流電圧Ｅｄを保持している。
　また、Ｕ相、Ｖ相、Ｗ相の各レグが、ＰＷＭパルス発生器のＰＷＭパルス論理信号Ｐｕ１～Ｐｕ４、Ｐｖ１～Ｐｖ４、Ｐｗ１～Ｐｗ４を、ゲートドライバ１４で差電圧電気信号（Ｇｕ１／Ｅｕ１～Ｇｕ４／Ｅｕ４、Ｇｖ１／Ｅｖ１～Ｇｖ４／Ｅｖ４、Ｇｗ１／Ｅｗ１～Ｇｗ４／Ｅｗ４）に変換された信号によって制御されることで、インバータ主回路１５が直流電圧（電力）を三相交流電圧（電力）に変換する機能を果たす。 With the above configuration, the DC positive voltage + Ed is applied from the node P and the DC negative voltage -Ed is applied from the node N to each of the U-phase, V-phase, and W-phase legs. Further, a zero voltage (0 potential) is applied from the node O. As described above, the capacitors C1 and C2 are connected between the node PO and the node ON to hold the DC voltage Ed between the nodes.
Also, each of the U-phase, V-phase, and W-phase legs converts the PWM pulse logic signals Pu1 to Pu4, Pv1 to Pv4, and Pw1 to Pw4 of the PWM pulse generator into a differential voltage electrical signal (Gu1 / Eu1 to (Gu4 / Eu4, Gv1 / Ev1 to Gv4 / Ev4, Gw1 / Ew1 to Gw4 / Ew4) are controlled by the signal so that the inverter main circuit 15 converts the DC voltage (power) into the three-phase AC voltage (power). Fulfills the function of converting to
　なお、トランジスタ（Ｑ１１～Ｑ１４、Ｑ２１～Ｑ２４、Ｑ３１～Ｑ３４）には、ターンオン／ターンオフ制御のしやすさから、スイッチ素子（スイッチングデバイス）としてシリコンデバイスであるシリコンＩＧＢＴあるいはシリコンＭＯＳＦＥＴ（Metal-Oxide-Semiconductor Field-Effect Transistor）を用いることが好ましい。
　また、ダイオード（Ｄ１１～Ｄ１６、Ｄ２１～Ｄ２６、Ｄ３１～Ｄ３６）には、シリコンＰｉＮダイオードあるいはシリコンショットキーバリアダイオードを用いることが好ましい。
　なお、スイッチング損失をより下げたい場合や、耐圧を高めたい場合には、シリコンデバイスの代わりに、シリコンよりもバンドギャップの大きい半導体を備えたワイドギャップデバイス（ワイドギャップパワーデバイス）を用いることが好ましい。例えばＳｉＣ（Silicon Carbide、シリコンカーバイド）デバイスを適用することも可能である。 The transistors (Q11 to Q14, Q21 to Q24, Q31 to Q34) have a silicon IGBT or a silicon MOSFET (Metal-Oxide-) as a switch device (switching device) for ease of turn-on / turn-off control. Semiconductor Field-Effect Transistor) is preferably used.
Further, it is preferable to use a silicon PiN diode or a silicon Schottky barrier diode as the diodes (D11 to D16, D21 to D26, D31 to D36).
When it is desired to lower the switching loss or increase the breakdown voltage, it is preferable to use a wide gap device (wide gap power device) including a semiconductor having a larger band gap than silicon instead of the silicon device. . For example, a SiC (Silicon Carbide) device can be applied.
［トランジスタＱ１１～Ｑ１４と電圧指令Ｖｕとの関係］
　次に、インバータ主回路１５を構成するトランジスタ（Ｑ１１～Ｑ１４、Ｑ２１～Ｑ２４、Ｑ３１～Ｑ３４）と電圧指令Ｖｕ、Ｖｖ、Ｖｗとの関係について説明する。ただし、電圧指令Ｖｕ、Ｖｖ、Ｖｗは、１２０°ずつ異なる位相関係以外は、概ね同一であるから、電圧指令Ｖｕを代表して説明する。
　図１０は、本発明の第１実施形態に係る電力変換装置に備えられたインバータ主回路におけるＵ相レグを構成するトランジスタＱ１１～Ｑ１４と電圧指令Ｖｕとの関係を示す図である。
　図１０において、Ｕ相レグを構成するトランジスタＱ１１～Ｑ１４は、電圧指令Ｖｕに従ってスイッチング動作を行う。また、「ＯＮ」はＯＮ状態、「ＯＦＦ」はＯＦＦ状態、「ＳＷ」はスイッチング状態（ＯＮ、ＯＦＦの繰り返し状態）を表している。 [Relationship between transistors Q11 to Q14 and voltage command Vu]
Next, the relationship between the transistors (Q11 to Q14, Q21 to Q24, Q31 to Q34) constituting the inverter main circuit 15 and the voltage commands Vu, Vv, Vw will be described. However, since the voltage commands Vu, Vv, and Vw are substantially the same except for a phase relationship that differs by 120 °, the voltage command Vu will be described as a representative.
FIG. 10 is a diagram showing the relationship between the transistors Q11 to Q14 constituting the U-phase leg and the voltage command Vu in the inverter main circuit provided in the power conversion device according to the first embodiment of the present invention.
In FIG. 10, the transistors Q11 to Q14 constituting the U-phase leg perform a switching operation according to the voltage command Vu. “ON” represents an ON state, “OFF” represents an OFF state, and “SW” represents a switching state (a repeated state of ON and OFF).
　電圧指令Ｖｕが０＜Ｖｕ＜＋１の間であるときには、トランジスタＱ１１とトランジスタＱ１３でスイッチング動作が行われる。
　また、電圧指令Ｖｕが－１＜Ｖｕ＜０の間であるときには、トランジスタＱ１２とトランジスタＱ１４でスイッチング動作が行われる。
　一方、電圧指令Ｖｕが＋１、０、－１のときにはトランジスタＱ１１～Ｑ１４は、ＯＮあるいはＯＦＦのいずれかに固定され、スイッチング動作は行われない。
　したがって、電圧指令Ｖｕが＋１、０、－１のときには、Ｕ相レグではスイッチング損失が発生しない。 When the voltage command Vu is between 0 <Vu <+1, the transistor Q11 and the transistor Q13 perform a switching operation.
When the voltage command Vu is between -1 <Vu <0, the transistor Q12 and the transistor Q14 perform a switching operation.
On the other hand, when the voltage command Vu is +1, 0, −1, the transistors Q11 to Q14 are fixed to either ON or OFF, and no switching operation is performed.
Therefore, when the voltage command Vu is +1, 0, −1, no switching loss occurs in the U-phase leg.
　また、前記したように、Ｖ相レグおよびＷ相レグに関しても同様であり、それぞれ電圧指令Ｖｖ、Ｖｗが＋１、０、－１のときにはＶ相レグ、Ｗ相レグでスイッチング損失は発生しない。
　このように、スイッチング動作を停止する状態を導入することにより、電力変換装置（インバータ）１０として、スイッチング損失（消費電力）と、零相電流による損失と高周波ノイズの低減を図っている。 As described above, the same applies to the V-phase leg and the W-phase leg. When the voltage commands Vv, Vw are +1, 0, −1, respectively, no switching loss occurs in the V-phase leg and the W-phase leg.
In this way, by introducing a state in which the switching operation is stopped, the power conversion device (inverter) 10 reduces switching loss (power consumption), loss due to zero-phase current, and high-frequency noise.
［Ｕ相レグの出力端子Ｕに出力される電圧波形］
　次に、Ｕ相レグの出力端子Ｕに出力される電圧波形について説明する。なお、出力端子Ｖ、Ｗについても概ね同様であるので出力端子Ｕに出力される電圧波形を代表して説明する。
　図１１は、本発明の第１実施形態に係る電力変換装置に備えられたインバータ主回路におけるＵ相レグの出力端子Ｕに出力される電圧波形を示す図であり、（ａ）は変調率Ｍが０．９のとき、（ｂ）は変調率Ｍが０．５のときの電圧波形である。また、図１１（ａ）、（ｂ）において、横軸は位相角θ（ｄｅｇ．）であり、縦軸は出力電圧である。
　また、ＰＷＭ制御に用いるキャリア周波数ｆｃは、三相交流の正弦波を構成する基本周波数ｆ１の１００倍に設定している。 [Voltage waveform output to output terminal U of U-phase leg]
Next, the voltage waveform output to the output terminal U of the U-phase leg will be described. Since the output terminals V and W are substantially the same, the voltage waveform output to the output terminal U will be described as a representative.
FIG. 11 is a diagram illustrating a voltage waveform output to the output terminal U of the U-phase leg in the inverter main circuit provided in the power conversion device according to the first embodiment of the present invention. (B) is a voltage waveform when the modulation factor M is 0.5. In FIGS. 11A and 11B, the horizontal axis represents the phase angle θ (deg.), And the vertical axis represents the output voltage.
The carrier frequency fc used for PWM control is set to 100 times the fundamental frequency f1 constituting a three-phase AC sine wave.
　変調率Ｍ＝０．９であるときの図１１（ａ）において、位相角θが、６０°＋φ＜θ＜１２０°－φの範囲にあるときには、電圧指令Ｖｕは＋１であり、出力端子Ｕの電圧は＋Ｅｄに固定される。
　また、位相角θが、０≦θ＜φ、１８０°－φ＜θ＜１８０°＋φ、３６０°－φ＜θ＜３６０°の範囲にあるときには、電圧指令Ｖｕは０であり、出力端子Ｕの電圧は０に固定される。
　さらに、位相角θが、２４０°＋φ≦θ＜３００°－φの範囲にあるときには、電圧指令Ｖｕは－１であり、出力端子Ｕの電圧は－Ｅｄに固定される。
　上記以外の位相角のときには、出力端子Ｕに振幅ＥｄのＰＷＭ波形が出力される。
　以上のことは、変調率Ｍが０．９の場合だけでなく、変調率が２／３＜Ｍ≦２／√３の場合にもあてはまる。なお、φは前述したパラメータφである。 In FIG. 11A when the modulation factor M is 0.9, when the phase angle θ is in the range of 60 ° + φ <θ <120 ° −φ, the voltage command Vu is +1 and the output terminal U Is fixed at + Ed.
When the phase angle θ is in the range of 0 ≦ θ <φ, 180 ° −φ <θ <180 ° + φ, 360 ° −φ <θ <360 °, the voltage command Vu is 0 and the output terminal U Is fixed at zero.
Further, when the phase angle θ is in the range of 240 ° + φ ≦ θ <300 ° −φ, the voltage command Vu is −1 and the voltage of the output terminal U is fixed to −Ed.
When the phase angle is other than the above, a PWM waveform having an amplitude Ed is output to the output terminal U.
The above applies not only when the modulation factor M is 0.9, but also when the modulation factor 2/3 <M ≦ 2 / √3. Φ is the parameter φ described above.
　変調率Ｍ＝０．５であるときの図１１（ｂ）において、位相角θが、０≦θ＜３０°、１５０°＜θ＜２１０°、３３０°＜θ＜３６０°の範囲にあるときには、電圧指令Ｖｕは０であり、出力端子Ｕの電圧は０に固定される。
　なお、前記の電圧指令Ｖｕが０となる位相角θの合計は、
（３０°－０°）＋（２１０°－１５０°）＋（３６０°－３３０°）＝１２０°
であるので、１２０°である。
　また、図１１（ｂ）においては、出力端子Ｕの電圧が、＋Ｅｄや－Ｅｄに固定されることはない。
　この出力端子Ｕの電圧が前記の区間において０に固定されることは、変調率Ｍが０．５の場合だけでなく、変調率が０≦Ｍ≦２／３の場合にもあてはまる。 In FIG. 11B when the modulation factor M is 0.5, when the phase angle θ is in the range of 0 ≦ θ <30 °, 150 ° <θ <210 °, 330 ° <θ <360 °. The voltage command Vu is 0, and the voltage of the output terminal U is fixed to 0.
The total phase angle θ at which the voltage command Vu is 0 is
(30 ° -0 °) + (210 ° -150 °) + (360 ° -330 °) = 120 °
Therefore, it is 120 °.
In FIG. 11B, the voltage at the output terminal U is not fixed at + Ed or -Ed.
The fact that the voltage of the output terminal U is fixed to 0 in the above-described interval applies not only when the modulation factor M is 0.5, but also when the modulation factor is 0 ≦ M ≦ 2/3.
　結局、図１１（ａ）、（ｂ）いずれにおいても、位相角長さ１２０°の範囲、つまり、全体の１／３の期間でＵ相レグのスイッチング動作が停止することが示されている。
　また、Ｖ相レグ、Ｗ相レグについても同様の理由により、全体の１／３の期間でＵ相レグのスイッチング動作が停止する。
　なお、以上の説明は、インバータ主回路１５のＵ相（Ｖ相、Ｗ相）の特性として、説明したが、インバータ主回路１５の出力は、本発明の電力変換装置（インバータ）１０の出力でもあるので、電力変換装置（インバータ）１０の特性でもある。 Eventually, both FIGS. 11 (a) and 11 (b) show that the switching operation of the U-phase leg stops in the range of the phase angle length of 120 °, that is, a period of 1/3 of the whole.
Further, for the same reason, the switching operation of the U-phase leg is stopped in the 1/3 overall period for the V-phase leg and the W-phase leg.
In addition, although the above description demonstrated as the characteristic of the U phase (V phase, W phase) of the inverter main circuit 15, the output of the inverter main circuit 15 is also the output of the power converter device (inverter) 10 of this invention. Therefore, it is also a characteristic of the power conversion device (inverter) 10.
［本発明のインバータ１０の出力端子Ｕに出力される電圧波形の周波数スペクトル］
　次に、図１１に示したインバータ主回路１５（またはインバータ１０）の出力端子Ｕに出力される電圧波形の周波数スペクトルについて説明する。なお、出力端子Ｖ、Ｗについても概ね同様であるので、出力端子Ｕに出力される電圧波形の周波数スペクトルを代表して説明する。
　図１２は、本発明の第１実施形態に係る電力変換装置に備えられたインバータ主回路１５の出力端子Ｕに出力される電圧波形の周波数スペクトルを示す図であり、（ａ）は変調率Ｍが０．９のとき、（ｂ）は変調率Ｍが０．５のときの周波数スペクトルである。
　なお、横軸は高調波次数ｎ、縦軸はｎ次の周波数成分Ｖｎの振幅値Ｖｎ／Ｅｄを示している。
　また、キャリア周波数ｆｃは、基本周波数ｆ１の９９倍に設定している。 [Frequency spectrum of voltage waveform output to output terminal U of inverter 10 of the present invention]
Next, the frequency spectrum of the voltage waveform output to the output terminal U of the inverter main circuit 15 (or the inverter 10) shown in FIG. 11 will be described. Since the output terminals V and W are substantially the same, the frequency spectrum of the voltage waveform output to the output terminal U will be described as a representative.
FIG. 12 is a diagram illustrating a frequency spectrum of a voltage waveform output to the output terminal U of the inverter main circuit 15 provided in the power conversion device according to the first embodiment of the present invention. (B) is a frequency spectrum when the modulation factor M is 0.5.
The horizontal axis represents the harmonic order n, and the vertical axis represents the amplitude value Vn / Ed of the nth-order frequency component Vn.
The carrier frequency fc is set to 99 times the basic frequency f1.
　図１２において、Ｖ１が基本周波数ｆ１の成分であり、その振幅値Ｖ１／Ｅｄは、図１２（ａ）では、０．９０であって、変調率（０．９）と同じ値となっている。また、図１２（ｂ）では、０．５０であって、変調率（０．５）と同じ値となっている。
　また、Ｖ９９がキャリア周波数ｆｃの成分であり、その振幅値Ｖ９９／Ｅｄは、図１２（ａ）で０．３２、図１２（ｂ）で０．３０である。
　また、３次成分のＶ３は、図１２（ａ）で０．１４、図１２（ｂ）で０．２１である。
　図１２（ａ）、（ｂ）に示した電圧波形の周波数スペクトルの特徴は、次に示す比較例の周波数スペクトルと比較し、あらためて後記する。 In FIG. 12, V1 is a component of the fundamental frequency f1, and its amplitude value V1 / Ed is 0.90 in FIG. 12A, which is the same value as the modulation factor (0.9). . In FIG. 12B, it is 0.50, which is the same value as the modulation rate (0.5).
V99 is a component of the carrier frequency fc, and its amplitude value V99 / Ed is 0.32 in FIG. 12A and 0.30 in FIG.
The third-order component V3 is 0.14 in FIG. 12A and 0.21 in FIG.
The characteristics of the frequency spectrum of the voltage waveform shown in FIGS. 12A and 12B will be described later in comparison with the frequency spectrum of the comparative example shown below.
［比較例のインバータから出力される電圧波形の周波数スペクトル］
　次に、比較例として図１９に示す制御特性の二相変調方法を適用した３レベルインバータの出力の電圧波形の周波数スペクトルを図１３に示す。そして、図１２に前記した本発明のインバータ１０の出力の電圧波形の周波数スペクトルと比較する。なお、本発明のインバータ１０も二相変調方法を適用した３レベルインバータである。 [Frequency spectrum of voltage waveform output from the inverter of the comparative example]
Next, FIG. 13 shows the frequency spectrum of the voltage waveform of the output of the three-level inverter to which the control characteristic two-phase modulation method shown in FIG. 19 is applied as a comparative example. And it compares with the frequency spectrum of the voltage waveform of the output of the inverter 10 of this invention mentioned above in FIG. The inverter 10 of the present invention is also a three-level inverter to which the two-phase modulation method is applied.
　図１３は、後記する比較例の二相変調方法を適用した３レベルインバータから出力される電圧波形の周波数スペクトルを示す図であり、（ａ）は変調率Ｍが０．９のとき、（ｂ）は変調率Ｍが０．５のときの周波数スペクトルである。なお、横軸は高調波次数ｎ、縦軸はｎ次の周波数成分Ｖｎの振幅値Ｖｎ／Ｅｄを示している。また、キャリア周波数ｆｃは基本周波数ｆ１の９９倍に設定している。
　図１３において、Ｖ１が基本周波数ｆ１の成分であり、その振幅値Ｖ１／Ｅｄは、図１３（ａ）では、０．９０であって、変調率（０．９）と同じ値となっている。また、図１３（ｂ）では、０．５０であって、変調率（０．５）と同じ値となっている。
　また、Ｖ９９がキャリア周波数ｆｃの成分であり、その振幅値Ｖ９９／Ｅｄは、図１３（ａ）で０．３０、図１２（ｂ）で０．３１である。
　また、３次高調波成分のＶ３は、図１３（ａ）で０．１６、図１３（ｂ）で０．６６である。
　また、９次高調波成分のＶ９、そして１５次高調波成分のＶ１５が、目立つレベルに出現している。 FIG. 13 is a diagram illustrating a frequency spectrum of a voltage waveform output from a three-level inverter to which a two-phase modulation method of a comparative example described later is applied. FIG. ) Is a frequency spectrum when the modulation factor M is 0.5. The horizontal axis represents the harmonic order n, and the vertical axis represents the amplitude value Vn / Ed of the nth-order frequency component Vn. The carrier frequency fc is set to 99 times the basic frequency f1.
In FIG. 13, V1 is a component of the fundamental frequency f1, and its amplitude value V1 / Ed is 0.90 in FIG. 13A, which is the same value as the modulation factor (0.9). . Moreover, in FIG.13 (b), it is 0.50 and is the same value as a modulation factor (0.5).
V99 is a component of the carrier frequency fc, and its amplitude value V99 / Ed is 0.30 in FIG. 13A and 0.31 in FIG.
The third harmonic component V3 is 0.16 in FIG. 13A and 0.66 in FIG.
Further, V9 of the 9th harmonic component and V15 of the 15th harmonic component appear at conspicuous levels.
［本発明と比較例のインバータから出力される電圧波形の周波数スペクトルの比較］
　本発明と比較例のインバータである図１２および図１３について、キャリア周波数ｆｃと基本周波数ｆ１との間の周波数成分Ｖｎを比較する。
　図１２および図１３を比較すると、本発明の第１実施形態の出力端子Ｕに出力される電圧波形の周波数成分Ｖｎのほとんどの振幅値は、比較例の二相変調方法のそれよりも少なくなっている。特に変調率Ｍが小さいほど、この傾向は強くなる。
　例えば、３次高調波成分Ｖ３を比較すると、変調率Ｍが０．９のとき、比較例の二相変調回路ではＶｎ＝０．１６に対し、本発明ではＶｎ＝０．１４となり僅かに減少する。また、変調率Ｍが０．５のとき、従来の二相変調方法ではＶｎ＝０．６６に対し、本発明ではＶｎ＝０．２１となり大幅に減少する。 [Comparison of frequency spectra of voltage waveforms output from the inverter of the present invention and a comparative example]
The frequency component Vn between the carrier frequency fc and the fundamental frequency f1 is compared between FIG. 12 and FIG. 13 which are inverters of the present invention and the comparative example.
Comparing FIG. 12 and FIG. 13, most amplitude values of the frequency component Vn of the voltage waveform output to the output terminal U of the first embodiment of the present invention are smaller than that of the two-phase modulation method of the comparative example. ing. In particular, this tendency becomes stronger as the modulation factor M is smaller.
For example, when the third-order harmonic component V3 is compared, when the modulation factor M is 0.9, Vn = 0.16 in the two-phase modulation circuit of the comparative example and Vn = 0.14 in the present invention, which is slightly decreased. To do. Further, when the modulation factor M is 0.5, Vn = 0.66 in the conventional two-phase modulation method, and Vn = 0.21 in the present invention, which is greatly reduced.
　また、比較例の二相変調方法では、３次高調波成分Ｖ３より高次の高調波成分Ｖ９、Ｖ１５などの振幅値が顕著であるが、本発明では、それらがほとんど無くなっていることが示されている。
　以上に示した特徴は、出力端子Ｖ、出力端子Ｗの出力でも全く同じである。したがって、本発明のＰＷＭ制御方法を用いたインバータは、出力電圧波形に含まれる高調波成分を、比較例の二相変調方法を用いたインバータよりも少なく抑えることができる。特にその傾向は変調率が小さい場合に顕著である。 Further, in the two-phase modulation method of the comparative example, the amplitude values of higher harmonic components V9, V15, etc. are more significant than the third harmonic component V3. However, in the present invention, these are almost eliminated. Has been.
The characteristics described above are exactly the same for the output of the output terminal V and the output terminal W. Therefore, the inverter using the PWM control method of the present invention can suppress the harmonic component contained in the output voltage waveform to be smaller than that of the inverter using the two-phase modulation method of the comparative example. This tendency is particularly remarkable when the modulation rate is small.
［本発明のインバータ１０の出力電圧に含まれている零相電圧Ｅｚ３の波形］
　次に、本発明の第１実施形態のインバータ１０の出力電圧に含まれている零相電圧Ｅｚ３の波形について説明する。なお、出力電圧に含まれている零相電圧Ｅｚ３は、図２、図３で示した電圧指令補正器１２内で生成した零相信号Ｖｚに起因する。
　図１４は、本発明の第１実施形態に係る電力変換装置（インバータ）１０、またはインバータ主回路１５の出力電圧に含まれている零相電圧Ｅｚ３の波形を示す図であり、（ａ）は変調率Ｍが０．９のとき、（ｂ）は変調率Ｍが０．５のときの波形である。また、図１４（ａ）、（ｂ）において、縦軸は零相電圧Ｅｚ３、横軸は位相角θであり、位相角θ＝０°～３６０°のうち、３０°～９０°の範囲を抜き出して示してある。
　図１４（ａ）および（ｂ）において、インバータ１０が発生する零相電圧Ｅｚ３の振幅は、直流電圧Ｅｄの±１／３に収まっていることが示されている。
　なお、図１４の特性については、次に図１５に比較例の特性を示すなかで、比較しながら特徴について、さらに説明する。 [Waveform of Zero Phase Voltage Ez3 Included in Output Voltage of Inverter 10 of the Present Invention]
Next, the waveform of the zero-phase voltage Ez3 included in the output voltage of the inverter 10 according to the first embodiment of the present invention will be described. The zero-phase voltage Ez3 included in the output voltage is caused by the zero-phase signal Vz generated in the voltage command corrector 12 shown in FIGS.
FIG. 14 is a diagram illustrating a waveform of the zero-phase voltage Ez3 included in the output voltage of the power conversion device (inverter) 10 or the inverter main circuit 15 according to the first embodiment of the present invention. When the modulation factor M is 0.9, (b) is a waveform when the modulation factor M is 0.5. 14A and 14B, the vertical axis represents the zero-phase voltage Ez3, the horizontal axis represents the phase angle θ, and the phase angle θ = 0 ° to 360 °, and the range of 30 ° to 90 °. Extracted and shown.
14A and 14B show that the amplitude of the zero-phase voltage Ez3 generated by the inverter 10 is within ± 1/3 of the DC voltage Ed.
Note that the characteristics of FIG. 14 will be further described while comparing the characteristics of the comparative example shown in FIG.
［比較例のインバータの出力電圧に含まれている零相電圧Ｅｚ２の波形］
　図１５は、後記する比較例の二相変調方法を用いた３レベルインバータの出力電圧に含まれている零相電圧Ｅｚ２の波形を示す図であり、（ａ）は変調率Ｍが０．９のとき、（ｂ）は変調率Ｍが０．５のときの波形である。また、図１５（ａ）、（ｂ）において、縦軸は零相電圧Ｅｚ２、横軸は位相角θであり、位相角θ＝０°～３６０°のうち、３０°～９０°の範囲を抜き出して示してある。 [Waveform of Zero Phase Voltage Ez2 Included in Output Voltage of Inverter of Comparative Example]
FIG. 15 is a diagram showing a waveform of the zero-phase voltage Ez2 included in the output voltage of the three-level inverter using the two-phase modulation method of the comparative example described later. FIG. 15A shows a modulation factor M of 0.9. (B) is a waveform when the modulation factor M is 0.5. 15A and 15B, the vertical axis represents the zero-phase voltage Ez2, the horizontal axis represents the phase angle θ, and the phase angle θ = 0 ° to 360 °, and the range of 30 ° to 90 ° is included. Extracted and shown.
　変調率Ｍ＝０．９であるときの図１５（ａ）において、インバータが発生する零相電圧Ｅｚ２の振幅は、直流電圧Ｅｄの±２／３であることが示されている。特に、位相角θ＝６０°において、零相電圧Ｅｚ２は－２／３Ｅｄから＋２／３Ｅｄへ急激に変化していることが示されている。 In FIG. 15A when the modulation factor M is 0.9, it is shown that the amplitude of the zero-phase voltage Ez2 generated by the inverter is ± 2/3 of the DC voltage Ed. In particular, it is shown that the zero-phase voltage Ez2 rapidly changes from −2 / 3Ed to + 2 / 3Ed at the phase angle θ = 60 °.
　変調率Ｍ＝０．５であるときの図１５（ｂ）において、インバータが発生する零相電圧Ｅｚ２の振幅は、±Ｅｄであることが示されている。特に、位相角θ＝６０°において、－Ｅｄから＋Ｅｄへ急激に変化している。
　以上に示した特徴は、他の相（Ｖ相、Ｗ相の出力）についても同じである。また、他の位相角についても同じである。 In FIG. 15B when the modulation factor M is 0.5, it is shown that the amplitude of the zero-phase voltage Ez2 generated by the inverter is ± Ed. In particular, at the phase angle θ = 60 °, there is a rapid change from −Ed to + Ed.
The characteristics described above are the same for the other phases (V-phase and W-phase outputs). The same applies to other phase angles.
［本発明のインバータと比較例のインバータとの零相電圧の比較］
　図１４と図１５の零相電圧を比較すると、本発明の第１実施形態のインバータの出力の零相電圧の振幅および零相電圧の変化（図１４）は、比較例の二相変調方法を用いたインバータのそれ（図１５）よりも小さくするできることが解る。特にその傾向は変調率が小さい場合に顕著である。
　零相電圧の振幅および零相電圧の変化が小さいことは、寄生抵抗や寄生静電容量を通して発生する零相電流を小さくすることに貢献する。そして零相電流を小さくすることは、零相電流による消費電力と高周波ノイズの低減に寄与する。特に変調率Ｍが小さいほど、この傾向は強くなる。
　なお、本発明の第１実施形態のインバータによる図１４の零相電圧は、図４の電圧指令値の波形に対応し、比較例のインバータの図１５の波形は、後記する図１８の電圧指令値の波形に対応している。すなわち、本発明のＰＷＭ制御方法のインバータの電圧指令値の波形を、図４のように選択したことが、零相電流を小さくし、前記の効果をもたらしている。 [Comparison of zero-phase voltage between the inverter of the present invention and the inverter of the comparative example]
Comparing the zero-phase voltage of FIG. 14 and FIG. 15, the change of the zero-phase voltage amplitude and the zero-phase voltage of the output of the inverter of the first embodiment of the present invention (FIG. 14) is the same as the two-phase modulation method of the comparative example. It can be seen that it can be made smaller than that of the inverter used (FIG. 15). This tendency is particularly remarkable when the modulation rate is small.
The small amplitude of the zero-phase voltage and the small change in the zero-phase voltage contribute to reducing the zero-phase current generated through the parasitic resistance and the parasitic capacitance. Reducing the zero-phase current contributes to reducing power consumption and high-frequency noise due to the zero-phase current. In particular, this tendency becomes stronger as the modulation factor M is smaller.
14 by the inverter of the first embodiment of the present invention corresponds to the waveform of the voltage command value of FIG. 4, and the waveform of FIG. 15 of the inverter of the comparative example is the voltage command of FIG. Corresponds to the value waveform. That is, selecting the waveform of the voltage command value of the inverter of the PWM control method of the present invention as shown in FIG. 4 reduces the zero-phase current and brings about the above effect.
［零相電圧Ｅｚ３、Ｅｚ２の測定回路］
　図１６は、本発明の第１実施形態に係る電力変換装置（インバータ）１０の零相電圧Ｅｚ３、および比較例の零相電圧Ｅｚ２の測定回路を示す図である。
　図１６において、本発明の第１実施形態のインバータ１０、または比較例のインバータのノードＯを接地電位として、インバータ（１０）の出力端子Ｕ、Ｖ、Ｗに同じリアクトル値のリアクトルＬａｃと同じ抵抗値の抵抗Ｒａｃの直列回路をそれぞれ接続し、抵抗Ｒａｃの一端を互いに接続した部分のノードの対地電圧を観測する。
　この測定で零相電圧Ｅｚ（Ｅｚ３、Ｅｚ２）を観測することができる。 [Measurement circuit for zero-phase voltages Ez3, Ez2]
FIG. 16 is a diagram showing a measurement circuit for the zero-phase voltage Ez3 of the power converter (inverter) 10 according to the first embodiment of the present invention and the zero-phase voltage Ez2 of the comparative example.
In FIG. 16, the same resistance as the reactor Lac having the same reactor value is applied to the output terminals U, V, and W of the inverter (10) with the node O of the inverter 10 of the first embodiment of the present invention or the inverter of the comparative example as the ground potential. A series circuit of value resistors Rac is connected to each other, and a ground voltage of a node at a portion where one ends of the resistors Rac are connected to each other is observed.
With this measurement, the zero-phase voltage Ez (Ez3, Ez2) can be observed.
（第２実施形態）
　次に、本発明の第２実施形態の電力変換装置として、第１実施形態における電力変換装置１０におけるインバータ主回路１５に代わる別のインバータ主回路４５（図１７）を用いた電力変換装置を示す。
　図１７は、本発明の第２実施形態に係る電力変換装置に備えるインバータ主回路４５の回路構成を示す図である。 (Second Embodiment)
Next, as a power conversion device according to the second embodiment of the present invention, a power conversion device using another inverter main circuit 45 (FIG. 17) instead of the inverter main circuit 15 in the power conversion device 10 according to the first embodiment is shown. .
FIG. 17 is a diagram showing a circuit configuration of the inverter main circuit 45 provided in the power conversion device according to the second embodiment of the present invention.
　図１７において、インバータ主回路４５は、正極の直流電源Ｐ（ノードＰ）と負極の直流電源Ｎ（ノードＮ）と中性点の直流電源Ｏ（ノードＯ）を備えている。
　正極の直流電源Ｐと中性点の直流電源Ｏとの間に、コンデンサＣ３が接続され、Ｅｄの電圧が印加されている。
　また、中性点の直流電源Ｏと負極の直流電源Ｎとの間に、コンデンサＣ４が接続され、Ｅｄの電圧が印加されている。
　また、正極の直流電源Ｐと負極の直流電源Ｎとの間に、トランジスタとダイオードを備えて構成されるＵ相レグ、Ｖ相レグ、Ｗ相レグが三相に対応して、並列構成で構成されている。 In FIG. 17, the inverter main circuit 45 includes a positive DC power supply P (node P), a negative DC power supply N (node N), and a neutral DC power supply O (node O).
A capacitor C3 is connected between the positive DC power supply P and the neutral DC power supply O, and the voltage of Ed is applied.
Further, a capacitor C4 is connected between the neutral DC power supply O and the negative DC power supply N, and the voltage of Ed is applied.
In addition, a U-phase leg, a V-phase leg, and a W-phase leg configured by including a transistor and a diode between the positive DC power source P and the negative DC power source N are configured in a parallel configuration corresponding to three phases. Has been.
　Ｕ相レグは、トランジスタＱ４１～Ｑ４４とダイオードＤ４１～Ｄ４４を備えて構成されている。
　ＩＧＢＴからなるトランジスタＱ４１とトランジスタＱ４４は直列に接続され、トランジスタＱ４１のコレクタは正極の直流電源Ｐ（ノードＰ）に接続され、トランジスタＱ４４のエミッタは負極の直流電源Ｎ（ノードＮ）に接続されている。
　また、トランジスタＱ４１のエミッタとトランジスタＱ４４のコレクタは互いに接続され、かつＵ相レグとしての出力端子Ｕに接続されている。
　トランジスタＱ４２とトランジスタＱ４３とは、互いのコレクタを介して直列に接続され、トランジスタＱ４２のエミッタは、ノードＯに接続され、トランジスタＱ４３のエミッタは、出力端子Ｕに接続されている。
　また、ダイオードＤ４１～Ｄ４４は、トランジスタＱ４１～Ｑ４４にそれぞれ逆並列に接続されている。 The U-phase leg includes transistors Q41 to Q44 and diodes D41 to D44.
An IGBT transistor Q41 and a transistor Q44 are connected in series, a collector of the transistor Q41 is connected to a positive DC power supply P (node P), and an emitter of the transistor Q44 is connected to a negative DC power supply N (node N). Yes.
The emitter of the transistor Q41 and the collector of the transistor Q44 are connected to each other and to the output terminal U as a U-phase leg.
The transistor Q42 and the transistor Q43 are connected in series via each other's collector, the emitter of the transistor Q42 is connected to the node O, and the emitter of the transistor Q43 is connected to the output terminal U.
The diodes D41 to D44 are connected in antiparallel to the transistors Q41 to Q44, respectively.
　ＩＧＢＴで構成されるトランジスタＱ４１のゲートとエミッタには、ゲートドライバ１４からの差電圧電気信号（Ｇｕ１／Ｅｕ１）として、それぞれＧｕ１とＥｕ１が印加されている。
　また、同様にトランジスタＱ４２のゲートとエミッタには、ゲートドライバ１４からの差電圧電気信号（Ｇｕ２／Ｅｕ２）として、それぞれＧｕ２とＥｕ２が印加されている。
　また、同様にトランジスタＱ４３のゲートとエミッタには、ゲートドライバ１４からの差電圧電気信号（Ｇｕ３／Ｅｕ３）として、それぞれＧｕ３とＥｕ３が印加されている。
　また、同様にトランジスタＱ４４のゲートとエミッタには、ゲートドライバ１４からの差電圧電気信号（Ｇｕ４／Ｅｕ４）として、それぞれＧｕ４とＥｕ４が印加されている。
　以上からＵ相レグが構成されている。 Gu1 and Eu1 are applied to the gate and emitter of the transistor Q41 formed of IGBT as a differential voltage electrical signal (Gu1 / Eu1) from the gate driver 14, respectively.
Similarly, Gu2 and Eu2 are applied to the gate and emitter of the transistor Q42 as differential voltage electrical signals (Gu2 / Eu2) from the gate driver 14, respectively.
Similarly, Gu3 and Eu3 are applied to the gate and emitter of the transistor Q43 as differential voltage electrical signals (Gu3 / Eu3) from the gate driver 14, respectively.
Similarly, Gu4 and Eu4 are applied to the gate and emitter of the transistor Q44 as differential voltage electrical signals (Gu4 / Eu4) from the gate driver 14, respectively.
From the above, the U-phase leg is configured.
　以上の構成は、トランジスタＱ４２とトランジスタＱ４３の接続の構成が、第１実施形態のインバータ主回路１５（図９）のトランジスタＱ１２とトランジスタＱ１３の接続の構成と異なるが、Ｕ相レグとしての出力端子Ｕからは、概ね同様の出力波形が出力する。 In the above configuration, the connection configuration of the transistor Q42 and the transistor Q43 is different from the configuration of the connection of the transistor Q12 and the transistor Q13 of the inverter main circuit 15 (FIG. 9) of the first embodiment, but the output terminal as a U-phase leg. From U, a substantially similar output waveform is output.
　Ｖ相も、同様にトランジスタＱ５１～Ｑ５４とダイオードＤ５１～Ｄ５４を備えて、それぞれＵ相のトランジスタＱ４１～Ｑ４４とダイオードＤ４１～Ｄ４４に対応して構成されている。
　また、トランジスタＱ５１～Ｑ５４には、それぞれ差電圧電気信号（Ｇｖ１／Ｅｖ１）、（Ｇｖ２／Ｅｖ２）、（Ｇｖ３／Ｅｖ３）、（Ｇｖ４／Ｅｖ４）が、Ｕ相のトランジスタＱ４１～Ｑ４４と同様の関係で接続されている。 Similarly, the V phase includes transistors Q51 to Q54 and diodes D51 to D54, and is configured to correspond to the U phase transistors Q41 to Q44 and the diodes D41 to D44, respectively.
Further, the differential voltage electrical signals (Gv1 / Ev1), (Gv2 / Ev2), (Gv3 / Ev3), and (Gv4 / Ev4) are respectively related to the transistors Q51 to Q54 in the same relationship as the U-phase transistors Q41 to Q44. Connected with.
　Ｗ相も、同様にトランジスタＱ６１～Ｑ６４とダイオードＤ６１～Ｄ６４を備えて、それぞれＵ相のトランジスタＱ４１～Ｑ４４とダイオードＤ４１～Ｄ４４に対応して構成されている。
　また、トランジスタＱ６１～Ｑ６４には、それぞれ差電圧電気信号（Ｇｗ１／Ｅｗ１）、（Ｇｗ２／Ｅｗ２）、（Ｇｗ３／Ｅｗ３）、（Ｇｗ４／Ｅｗ４）が、Ｕ相のトランジスタＱ１１～Ｑ１４と同様の関係で接続されている。 Similarly, the W phase includes transistors Q61 to Q64 and diodes D61 to D64, and is configured to correspond to the U phase transistors Q41 to Q44 and the diodes D41 to D44, respectively.
In addition, the differential voltage electrical signals (Gw1 / Ew1), (Gw2 / Ew2), (Gw3 / Ew3), and (Gw4 / Ew4) are respectively connected to the transistors Q61 to Q64 in the same relationship as the U-phase transistors Q11 to Q14. Connected with.
　以上の構成により、Ｕ相、Ｖ相、Ｗ相の各レグには、ノードＰから直流正電圧＋Ｅｄが、ノードＮから直流負電圧－Ｅｄが与えられ、ノードＯからは、零電圧（０電位）が与えられている。前記したように、ノードＰ－Ｏ間とノードＯ－Ｎ間にはコンデンサＣ３、Ｃ４が接続され、ノード間の直流電圧Ｅｄを保持している。
　また、Ｕ相、Ｖ相、Ｗ相の各レグが、ＰＷＭパルス発生器のＰＷＭパルス論理信号Ｐｕ１～Ｐｕ４、Ｐｖ１～Ｐｖ４、Ｐｗ１～Ｐｗ４を、ゲートドライバ１４で差電圧電気信号（Ｇｕ１／Ｅｕ１～Ｇｕ４／Ｅｕ４、Ｇｖ１／Ｅｖ１～Ｇｖ４／Ｅｖ４、Ｇｗ１／Ｅｗ１～Ｇｗ４／Ｅｗ４）に変換された信号によって制御されることで、インバータ主回路４５が直流電圧（電力）を三相交流電圧（電力）に変換する機能を果たす。 With the above configuration, the DC positive voltage + Ed is applied from the node P and the DC negative voltage -Ed is applied from the node N to the U-phase, V-phase, and W-phase legs, and the zero voltage (0 potential) is applied from the node O. ) Is given. As described above, the capacitors C3 and C4 are connected between the node PO and the node ON to hold the DC voltage Ed between the nodes.
Also, each of the U-phase, V-phase, and W-phase legs converts the PWM pulse logic signals Pu1 to Pu4, Pv1 to Pv4, and Pw1 to Pw4 of the PWM pulse generator into a differential voltage electrical signal (Gu1 / Eu1 to (Gu4 / Eu4, Gv1 / Ev1 to Gv4 / Ev4, Gw1 / Ew1 to Gw4 / Ew4) are controlled by the signal so that the inverter main circuit 45 converts the DC voltage (power) into the three-phase AC voltage (power). Fulfills the function of converting to
　なお、図１７の回路では、図９の回路に比べてダイオードの素子数が６つ少なく構成することができる。
　一方で、出力端子Ｕ、Ｖ、Ｗと、ノードＰおよびノードＮ間のトランジスタとダイオードの直列数が２から１に減るために、それらの素子に耐圧が２倍要求される。耐圧を高めたい場合には、前記したように、シリコンデバイスの代わりに、シリコンよりもバンドギャップの大きい半導体素子を備えたワイドギャップデバイス（ワイドギャップパワーデバイス）を用いることが好ましい。例えばＳｉＣデバイスを適用することも可能である。
　なお、図９の回路と同様に、図１７の回路に用いるトランジスタには、ターンオン／ターンオフ制御のしやすさから、シリコンＩＧＢＴあるいはシリコンＭＯＳＦＥＴが用いることが好ましい。また、ダイオードにはシリコンＰｉＮダイオードあるいはシリコンショットキーバリアダイオードが用いられる。 In the circuit of FIG. 17, the number of diode elements can be reduced by six compared to the circuit of FIG.
On the other hand, since the number of series-connected transistors and diodes between the output terminals U, V, and W, and the nodes P and N is reduced from 2 to 1, these elements are required to have double withstand voltage. When it is desired to increase the breakdown voltage, as described above, it is preferable to use a wide gap device (wide gap power device) including a semiconductor element having a larger band gap than silicon instead of the silicon device. For example, a SiC device can be applied.
Similar to the circuit of FIG. 9, it is preferable to use a silicon IGBT or a silicon MOSFET for the transistor used in the circuit of FIG. 17 because of easy control of turn-on / turn-off. As the diode, a silicon PiN diode or a silicon Schottky barrier diode is used.
（比較例）
　比較例として、電圧指令値を０に固定しない場合の二相変調方法の電圧指令を３レベルインバータに適用する例を次に示す。 (Comparative example)
As a comparative example, an example in which the voltage command of the two-phase modulation method when the voltage command value is not fixed to 0 is applied to a three-level inverter is shown below.
<電圧指令>
　図１８は、比較例の二相変調方法の電圧指令の一例（電圧指令値を０に固定しない場合）を示す図である。なお、縦軸は（正規化した）電圧指令値、横軸は位相角である。
　図１８において、電圧指令Ｖｕ２、Ｖｖ２、Ｖｗ２は、基本正弦波信号に零相信号を加えることにより生成されている。
　図１８の波形（Ｖｕ２、Ｖｖ２、Ｖｗ２）に示すように電圧指令値が＋１および－１に固定される位相角範囲ができる。電圧指令Ｖｕ２は、位相角６０°～１２０°では＋１に、位相角２４０°～３００°では－１に固定している。なお、本発明の図４に示すような電圧指令値が０で固定される範囲は、比較例の図１８においては、存在していない。
　このような二相変調方法の電圧指令を３レベルインバータに適用することで、図１９に示すＰＷＭ電圧波形（１相のみを表記）を出力することができる。 <Voltage command>
FIG. 18 is a diagram illustrating an example of the voltage command of the two-phase modulation method of the comparative example (when the voltage command value is not fixed to 0). The vertical axis represents the (normalized) voltage command value, and the horizontal axis represents the phase angle.
In FIG. 18, the voltage commands Vu2, Vv2, and Vw2 are generated by adding a zero-phase signal to the basic sine wave signal.
As shown by the waveforms (Vu2, Vv2, Vw2) in FIG. 18, a phase angle range in which the voltage command value is fixed at +1 and −1 is formed. The voltage command Vu2 is fixed to +1 at a phase angle of 60 ° to 120 °, and is fixed to −1 at a phase angle of 240 ° to 300 °. Note that the range in which the voltage command value is fixed at 0 as shown in FIG. 4 of the present invention does not exist in FIG. 18 of the comparative example.
By applying such a voltage command of the two-phase modulation method to a three-level inverter, the PWM voltage waveform (only one phase is shown) shown in FIG. 19 can be output.
<ＰＷＭ電圧波形>
　図１９は、比較例の二相変調方法の電圧指令を３レベルインバータに適用することで得られるＰＷＭ電圧波形（Ｕ相）を示す図である。なお、縦軸は出力電圧、横軸は位相角である。
　図１９に示すＰＷＭ電圧波形は、図１８の電圧指令値を０～＋１および－１～０の振幅を持った２つのキャリア三角波とコンパレータで比較して得られたＰＷＭ信号により、３レベルインバータのトランジスタをスイッチングすることで得られる。
　図１９において、出力電圧波形（ＰＷＭ電圧波形）は、位相角６０°～１２０°では＋Ｅｄに、位相角２４０°～３００°で－Ｅｄに固定する。そのため、全位相角３６０°のうち、１２０°で３レベルインバータのスイッチング動作を停止することができる。
　したがって、インバータを構成する各スイッチ素子において、スイッチング回数を２／３に低減でき、スイッチング損失を減らすことができる。 <PWM voltage waveform>
FIG. 19 is a diagram illustrating a PWM voltage waveform (U phase) obtained by applying the voltage command of the two-phase modulation method of the comparative example to the three-level inverter. The vertical axis represents the output voltage, and the horizontal axis represents the phase angle.
The PWM voltage waveform shown in FIG. 19 is obtained by comparing the voltage command value shown in FIG. 18 with two carrier triangular waves having amplitudes of 0 to +1 and −1 to 0 and a PWM signal obtained by a comparator. It is obtained by switching the transistor.
In FIG. 19, the output voltage waveform (PWM voltage waveform) is fixed to + Ed at a phase angle of 60 ° to 120 °, and is fixed to −Ed at a phase angle of 240 ° to 300 °. Therefore, the switching operation of the three-level inverter can be stopped at 120 ° out of the total phase angle 360 °.
Therefore, in each switch element constituting the inverter, the number of times of switching can be reduced to 2/3, and the switching loss can be reduced.
<比較例の二相変調方法の補足と本発明との比較>
　二相変調方法および、二相変調と同様にトランジスタのスイッチングを一定期間停止させるＰＷＭ制御方法は、特許文献１および特許文献２に記載されている。
　なお、二相変調方法は、変調率を１より大きい２／√３まで高めても、線間電圧の正弦波形状に歪みを与えることが無いので、電圧利用率を大きくすることができる特徴も備えている。
　しかしながら、図１８、図１９に示した比較例の二相変調方法は、電圧指令値を＋１または－１に固定することはあるが、０に固定しない方法である。
　一方、本発明のＰＷＭ制御方法では、図４に示すように、電圧指令値を所定の位相角の範囲で、０に固定する方法をとっている。この相異が、図１２（本発明）と図１３（比較例）で示すように、本発明が比較例に対して、高調波の発生が少なくなる理由のひとつである。つまり、本発明は、高調波の発生が少なくなるような零相電圧指令を使用するので、零相電流が少なく、高調波や零相電流による消費電力およびノイズが低減する効果がある。特に、変調率が小さい場合に顕著である。 <Comparison of Supplementary Two-Phase Modulation Method of Comparative Example and Present Invention>
Patent Document 1 and Patent Document 2 describe a two-phase modulation method and a PWM control method for stopping switching of a transistor for a certain period as in the case of two-phase modulation.
Note that the two-phase modulation method does not distort the sinusoidal shape of the line voltage even if the modulation rate is increased to 2 / √3, which is larger than 1, so that the voltage utilization rate can be increased. I have.
However, the two-phase modulation method of the comparative example shown in FIGS. 18 and 19 is a method of fixing the voltage command value to +1 or −1 but not fixing it to 0.
On the other hand, in the PWM control method of the present invention, as shown in FIG. 4, the voltage command value is fixed to 0 within a predetermined phase angle range. This difference is one of the reasons why the present invention reduces the generation of higher harmonics than the comparative example, as shown in FIG. 12 (the present invention) and FIG. 13 (the comparative example). In other words, the present invention uses a zero-phase voltage command that reduces the generation of harmonics, so that there is little zero-phase current, and there is an effect of reducing power consumption and noise due to harmonics and zero-phase current. This is particularly noticeable when the modulation rate is small.
（その他の実施形態）
　以上、本発明の実施形態について図面を参照して詳述したが、本発明はこれら実施形態およびその変形に限定されるものではなく、本発明の要旨を逸脱しない範囲の設計変更等があってもよく、以下にその例をあげる。 (Other embodiments)
As mentioned above, although embodiment of this invention was explained in full detail with reference to drawings, this invention is not limited to these embodiment and its deformation | transformation, There exists a design change etc. of the range which does not deviate from the summary of this invention. Well, here are some examples:
《制御回路１７》
　図１において、インバータ主回路１５を制御する制御回路１７は、基本電圧指令発生器１１、電圧指令補正器１２、ＰＷＭパルス発生器１３、ゲートドライバ１４で構成する例を説明したが、この構成に限定されるものではない。
　例えば、ゲートドライバ１４は、ＰＷＭパルス発生器１３に含まれていてもよい。また、基本電圧指令発生器１１と電圧指令補正器１２は、一体化していてもよい。
　また、前記したように基本電圧指令発生器１１、電圧指令補正器１２、ＰＷＭパルス発生器１３は、それぞれ個別のハードの回路で構成してもよいし、また、ＭＰＵ（Micro-Processing Unit）やＣＰＵ（Central Processing Unit）などの制御用ＩＣを媒体としたソフトウェアプログラムによって、全体で一括して制御する構成にしてもよい。 << Control circuit 17 >>
In FIG. 1, the control circuit 17 that controls the inverter main circuit 15 has been described as being configured with the basic voltage command generator 11, the voltage command corrector 12, the PWM pulse generator 13, and the gate driver 14. It is not limited.
For example, the gate driver 14 may be included in the PWM pulse generator 13. Further, the basic voltage command generator 11 and the voltage command corrector 12 may be integrated.
Further, as described above, the basic voltage command generator 11, the voltage command corrector 12, and the PWM pulse generator 13 may be configured by individual hardware circuits, MPU (Micro-Processing Unit), A configuration may be adopted in which control is performed collectively by a software program using a control IC such as a CPU (Central Processing Unit) as a medium.
《トランジスタ》
　図９、図１７において、トランジスタはＩＧＢＴとして説明し、またＭＯＳＦＥＴを替わりに使用することの可能性についても説明したが、トランジスタは基本的にはスイッチング素子であればよいので、ＩＧＢＴやＭＯＳＦＥＴに限定されない。例えば、ＢＪＴ（Bipolar junction transistor）、ＢｉＣＭＯＳ（Bipolar Complementary Metal Oxide Semiconductor）を用いてもよい。
　また、ワイドギャップデバイスとして、ＳｉＣをあげたが、これに限定されない。例えば、ＧａＮ（gallium nitride、窒化ガリウム）やＧａ2Ｏ3（gallium oxide、酸化ガリウム）などの半導体デバイスを用いてもよい。 <Transistor>
9 and 17, the transistor is described as an IGBT, and the possibility of using a MOSFET instead has been described. However, since the transistor basically needs to be a switching element, it is limited to an IGBT or a MOSFET. Not. For example, BJT (Bipolar junction transistor) or BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) may be used.
Moreover, although SiC was mentioned as a wide gap device, it is not limited to this. For example, a semiconductor device such as GaN (gallium nitride) or Ga 2 O 3 (gallium oxide) may be used.
《ダイオード》
　図９、図１７において、ダイオード（Ｄ１１～Ｄ１４、Ｄ２１～Ｄ２４、Ｄ３１～Ｄ３４、Ｄ４１～Ｄ４４、Ｄ５１～Ｄ５４、Ｄ６１～Ｄ６４）は、トランジスタ（ＩＧＢＴ）に逆並列に接続すると説明したが、ダイオード素子として格別に付加せずに、トランジスタ（ＩＧＢＴ、ＭＯＳＦＥＴ）に内蔵された寄生のダイオードを用いてもよい。 "diode"
9 and 17, it has been described that the diodes (D11 to D14, D21 to D24, D31 to D34, D41 to D44, D51 to D54, D61 to D64) are connected in reverse parallel to the transistor (IGBT). A parasitic diode incorporated in a transistor (IGBT, MOSFET) may be used without being added as an element.
　１０　　電力変換装置、インバータ
　１１　　基本電圧指令発生器
　１２　　電圧指令補正器
　１３　　ＰＷＭパルス発生器
　１４　　ゲートドライバ
　１５、４５　　インバータ主回路（インバータ回路）
　１６　　バッファ回路
　２０、２６　　最大値選択器（Ｍａｘ）
　２１、２５　　最小値選択器（Ｍｉｎ）
　２２、２４、３２　　減算器
　２３、２７、２８、２９　　加算器
　２０１　　中央値選択器
　３１　　三角波発生器
　３３ｕ、３３ｖ、３３ｗ、３４ｕ、３４ｖ、３４ｗ　　コンパレータ
　３５ｕ、３５ｖ、３５ｗ、３６ｕ、３６ｖ、３６ｗ　　論理反転回路
　３７　　ＯＮディレイ回路
　Ｃ１～Ｃ４　　コンデンサ
　Ｄ１１～Ｄ１６、Ｄ２１～Ｄ２６、Ｄ３１～Ｄ３４、Ｄ４１～Ｄ４４、Ｄ５１～Ｄ５４、Ｄ６１～Ｄ６４　　ダイオード
　Ｌａｃ　　リアクトル
　Ｑ１１～Ｑ１４、Ｑ２１～Ｑ２４、Ｑ３１～Ｑ３４、Ｑ４１～Ｑ４４、Ｑ５１～Ｑ５４、Ｑ６１～Ｑ６４　　トランジスタ、スイッチングデバイス、ＩＧＢＴ
　Ｒａｃ　　抵抗 DESCRIPTION OF SYMBOLS 10 Power converter, inverter 11 Basic voltage command generator 12 Voltage command corrector 13 PWM pulse generator 14 Gate driver 15, 45 Inverter main circuit (inverter circuit)
16 Buffer circuit 20, 26 Maximum value selector (Max)
21, 25 Minimum value selector (Min)
22, 24, 32 Subtractor 23, 27, 28, 29 Adder 201 Median value selector 31 Triangular wave generator 33u, 33v, 33w, 34u, 34v, 34w Comparator 35u, 35v, 35w, 36u, 36v, 36w Logical inversion Circuit 37 ON delay circuit C1 to C4 capacitors D11 to D16, D21 to D26, D31 to D34, D41 to D44, D51 to D54, D61 to D64 Diode Lac reactor Q11 to Q14, Q21 to Q24, Q31 to Q34, Q41 to Q44 , Q51 to Q54, Q61 to Q64 Transistors, switching devices, IGBTs
Rac resistance

Claims (14)

  1. 　直流電圧＋Ｅｄ、－Ｅｄを電源とし、＋Ｅｄ、０、－Ｅｄの三段階のＰＷＭ電圧波形を出力する複数のスイッチングデバイスで構成されたインバータ回路と、
    　前記複数のスイッチングデバイスのＯＮ／ＯＦＦ制御を行い、前記インバータ回路の出力からＰＷＭ電圧波形を発生させる制御回路と、
    を備え、
    　前記制御回路は、所定の変調率Ｍに比例して前記ＰＷＭ電圧波形の基本周波数成分の振幅を制御し、前記基本周波数成分の一周期の間に、前記インバータ回路の出力電圧を、前記基本周波数成分の特定の位相角範囲に対して＋Ｅｄ、０、－Ｅｄのいずれかで固定させ、
    　前記変調率Ｍが２／３以上のときには、前記特定の位相角範囲において、前記インバータ回路の出力電圧を、＋Ｅｄ、０、および－Ｅｄの全ての電圧に固定させ、
    　前記変調率Ｍが２／３未満のときには、前記特定の位相角範囲において、前記インバータ回路の出力電圧を、０の電圧にのみ固定させ、
    　前記特定の位相角範囲以外の範囲では、前記インバータ回路の出力に振幅Ｅｄのパルス状電圧波形を発生させる３相出力の３レベルインバータであることを特徴とする電力変換装置。     An inverter circuit composed of a plurality of switching devices that outputs DC voltage waveforms of three stages of + Ed, 0, and -Ed using DC voltages + Ed and -Ed as power sources;
    A control circuit that performs ON / OFF control of the plurality of switching devices and generates a PWM voltage waveform from the output of the inverter circuit;
    With
    The control circuit controls the amplitude of the fundamental frequency component of the PWM voltage waveform in proportion to a predetermined modulation factor M, and outputs the output voltage of the inverter circuit during the one cycle of the fundamental frequency component. Fixed at + Ed, 0, or -Ed for a specific phase angle range of the component,
    When the modulation factor M is 2/3 or more, the output voltage of the inverter circuit is fixed to all the voltages + Ed, 0, and −Ed in the specific phase angle range,
    When the modulation factor M is less than 2/3, the output voltage of the inverter circuit is fixed only to a voltage of 0 in the specific phase angle range,
    3. A power conversion device characterized by being a three-phase output three-level inverter that generates a pulsed voltage waveform with an amplitude Ed at the output of the inverter circuit in a range other than the specific phase angle range.
  2. 　請求項１に記載の電力変換装置において、
    　前記特定の位相角範囲のうち、前記インバータ回路の出力電圧を＋Ｅｄおよび－Ｅｄの電圧に固定する回数は、前記基本周波数成分の一周期の間にそれぞれ１回であり、
    　前記インバータ回路の出力電圧を０の電圧に固定する回数は２回である
    ことを特徴とする電力変換装置。     The power conversion device according to claim 1,
    Of the specific phase angle range, the number of times that the output voltage of the inverter circuit is fixed to + Ed and −Ed is once during one period of the fundamental frequency component,
    The number of times that the output voltage of the inverter circuit is fixed to a voltage of 0 is two.
  3. 　請求項１に記載の電力変換装置において、
    　前記特定の位相角範囲のうち、前記インバータ回路の出力電圧を０の電圧に固定する位相角範囲は、
    　変調率Ｍが２／３未満のときには、変調率Ｍに関わらず一定であり、
    　変調率Ｍが２／３以上のときには、変調率Ｍの増加に従って単調に減少する
    ことを特徴とする電力変換装置。     The power conversion device according to claim 1,
    Of the specific phase angle range, the phase angle range for fixing the output voltage of the inverter circuit to 0 voltage is:
    When the modulation factor M is less than 2/3, it is constant regardless of the modulation factor M,
    When the modulation factor M is 2/3 or more, the power conversion device decreases monotonously as the modulation factor M increases.
  4. 　請求項１に記載の電力変換装置において、
    　基本周波数成分の位相角をθとすると、前記特定の位相角範囲は度数法による角度のパラメータφを用いて表され、
    　６０°＋φ＜θ＜１２０°－φの範囲で前記インバータ主回路の出力電圧を０の電圧に固定し、
    　２４０°－φ＜θ＜３００°－φの範囲で前記インバータ主回路の出力電圧を０の電圧に固定し、
    　０°＜θ＜φ、１８０°－φ＜θ＜１８０°＋φ、および３６０°－φ＜θ＜３６０°の範囲で前記インバータ回路の出力電圧を０の電圧に固定し、
    　変調率Ｍが２／３未満のときには、パラメータφは６０°で一定であり、
    　変調率Ｍが２／３より大きいときには、パラメータφは６０°と０°の間を変調率Ｍの増加に従って単調に減少する
    ことを特徴とする電力変換装置。     The power conversion device according to claim 1,
    When the phase angle of the fundamental frequency component is θ, the specific phase angle range is expressed using an angle parameter φ by a power method,
    In the range of 60 ° + φ <θ <120 ° −φ, the output voltage of the inverter main circuit is fixed to 0 voltage,
    In the range of 240 ° −φ <θ <300 ° −φ, the output voltage of the inverter main circuit is fixed to a voltage of 0,
    The output voltage of the inverter circuit is fixed to a voltage of 0 in the range of 0 ° <θ <φ, 180 ° −φ <θ <180 ° + φ, and 360 ° −φ <θ <360 °,
    When the modulation factor M is less than 2/3, the parameter φ is constant at 60 °,
    When the modulation factor M is greater than 2/3, the parameter φ monotonously decreases as the modulation factor M increases between 60 ° and 0 °.
  5. 　請求項４に記載の電力変換装置において、
    　前記パラメータφは、下記に示す変調率Ｍの関数であることを特徴とする電力変換装置。
    ０≦Ｍ≦２／３のとき、
    φ＝３０°
    ２／３＜Ｍ≦２／√３のとき、
    Figure JPOXMLDOC01-appb-M000001
         The power conversion device according to claim 4,
    The parameter φ is a function of a modulation factor M shown below, and a power converter.
    When 0 ≦ M ≦ 2/3,
    φ = 30 °
    When 2/3 <M ≦ 2 / √3,
    Figure JPOXMLDOC01-appb-M000001
  6. 　請求項１に記載の電力変換装置において、
    　前記制御回路は、
    　第１、第２、第３の基本正弦波を発生する基本電圧指令発生器と、
    　前記第１、第２、第３の基本正弦波の中央値からなる零相信号を、前記第１、第２、第３の基本正弦波にそれぞれ加算して第１、第２、第３の電圧指令を生成する電圧指令補正器と、
    　前記第１、第２、第３の電圧指令をそれぞれＰＷＭパルス論理信号に変換するＰＷＭパルス発生器と、
    を備えていることを特徴とする電力変換装置。     The power conversion device according to claim 1,
    The control circuit includes:
    A basic voltage command generator for generating first, second and third basic sine waves;
    A zero-phase signal having a median value of the first, second, and third basic sine waves is added to the first, second, and third basic sine waves, respectively. A voltage command corrector for generating a voltage command;
    A PWM pulse generator for converting each of the first, second and third voltage commands into a PWM pulse logic signal;
    A power conversion device comprising:
  7. 　請求項１に記載の電力変換装置において、
    　前記複数のスイッチングデバイスは、ＩＧＢＴまたはＭＯＳＦＥＴであることを特徴とする電力変換装置。     The power conversion device according to claim 1,
    The plurality of switching devices are IGBTs or MOSFETs.
  8. 　請求項７に記載の電力変換装置において、
    　前記ＩＧＢＴまたはＭＯＳＦＥＴは、シリコンよりもバンドギャップの大きい半導体を備えたワイドギャップデバイスであることを特徴とする電力変換装置。     The power conversion device according to claim 7,
    The IGBT or MOSFET is a wide gap device including a semiconductor having a larger band gap than silicon.
  9. 　請求項８に記載の電力変換装置において、
    　前記ワイドギャップデバイスは、シリコンカーバイトを備えたワイドギャップデバイスであることを特徴とする電力変換装置。     The power conversion device according to claim 8, wherein
    The wide gap device is a wide gap device including a silicon carbide.
  10. 　直流電圧＋Ｅｄ、－Ｅｄを電源とし、＋Ｅｄ、０、－Ｅｄの三段階のＰＷＭ電圧波形を出力する複数のスイッチングデバイスで構成されたインバータ回路と、
    　前記複数のスイッチングデバイスのＯＮ／ＯＦＦ制御を行い、前記インバータ回路の出力からＰＷＭ電圧波形を発生させる制御回路と、
    を備え、
    　前記制御回路を使用して、所定の変調率Ｍに比例して前記ＰＷＭ電圧波形の基本周波数成分の振幅を制御し、前記基本周波数成分の一周期の間に、前記インバータ回路の出力電圧を、前記基本周波数成分の特定の位相角範囲に対して＋Ｅｄ、０、－Ｅｄのいずれかで固定させ、
    　前記変調率Ｍが２／３以上のときには、前記特定の位相角範囲において、前記インバータ回路の出力電圧を、＋Ｅｄ、０、および－Ｅｄの全ての電圧に固定させ、
    　前記変調率Ｍが２／３未満のときには、前記特定の位相角範囲において、前記インバータ回路の出力電圧を、０の電圧にのみ固定させ、
    　前記特定の位相角範囲以外の範囲では、前記インバータ回路の出力に振幅Ｅｄのパルス状電圧波形を発生させる
    ことを特徴とするＰＷＭ制御方法。     An inverter circuit composed of a plurality of switching devices that outputs DC voltage waveforms of three stages of + Ed, 0, and -Ed using DC voltages + Ed and -Ed as power sources;
    A control circuit that performs ON / OFF control of the plurality of switching devices and generates a PWM voltage waveform from the output of the inverter circuit;
    With
    Using the control circuit, the amplitude of the fundamental frequency component of the PWM voltage waveform is controlled in proportion to a predetermined modulation factor M, and during one cycle of the fundamental frequency component, the output voltage of the inverter circuit is Fixed at + Ed, 0, or -Ed for a specific phase angle range of the fundamental frequency component,
    When the modulation factor M is 2/3 or more, the output voltage of the inverter circuit is fixed to all the voltages + Ed, 0, and −Ed in the specific phase angle range,
    When the modulation factor M is less than 2/3, the output voltage of the inverter circuit is fixed only to a voltage of 0 in the specific phase angle range,
    A PWM control method characterized by generating a pulsed voltage waveform with an amplitude Ed at the output of the inverter circuit in a range other than the specific phase angle range.
  11. 　第１、第２、第３の電圧指令とキャリア三角波を比較することでインバータ回路のスイッチを制御するパルスを生成し、
    　前記第１、第２、第３の電圧指令は、第１、第２、第３の基本正弦波にそれぞれ零相信号を加算することによって得られ、
    　前記第１、第２、第３の基本正弦波は、０から２／√３の間の値で可変できる変調率の振幅を持ち、互いに位相が１２０°異なる正弦波信号であり、
    　前記第１、第２、第３の基本正弦波の最大値と最小値をそれぞれＶａ、Ｖｂとしたとき、前記零相信号は、（１－Ｖａ）、（Ｖａ＋Ｖｂ）、（－１－Ｖｂ）から中央値を選んだ値である
    ことを特徴とするＰＷＭ制御方法。     A pulse for controlling the switch of the inverter circuit is generated by comparing the first, second, and third voltage commands with the carrier triangular wave,
    The first, second, and third voltage commands are obtained by adding zero-phase signals to the first, second, and third basic sine waves,
    The first, second, and third basic sine waves are sine wave signals having a modulation rate that can be varied by a value between 0 and 2 / √3 and having phases different from each other by 120 °.
    When the maximum value and minimum value of the first, second, and third basic sine waves are Va and Vb, respectively, the zero-phase signal is (1−Va), (Va + Vb), (−1−Vb). A PWM control method, wherein the median value is selected from
  12. 　請求項１１に記載のＰＷＭ制御方法において、
    　前記第１、第２、第３の電圧指令は、第１のキャリア三角波と第２のキャリア三角波と比較され、
    　前記第１のキャリア三角波は、電圧指令値０～＋１の間の値を取りうる三角波であり、
    　前記第２のキャリア三角波は、電圧指令値－１～０の間を取りうる三角波であって、
    　前記第１のキャリア三角波および前記第２のキャリア三角波の振幅は、１より所定の値、小さい
    ことを特徴とするＰＷＭ制御方法。     The PWM control method according to claim 11, wherein
    The first, second, and third voltage commands are compared with a first carrier triangular wave and a second carrier triangular wave,
    The first carrier triangular wave is a triangular wave that can take a voltage command value between 0 and +1,
    The second carrier triangular wave is a triangular wave that can take a voltage command value of −1 to 0,
    The PWM control method according to claim 1, wherein amplitudes of the first carrier triangular wave and the second carrier triangular wave are smaller than 1 by a predetermined value.
  13. 　請求項１１に記載のＰＷＭ制御方法で制御されることを特徴とする電力変換装置。 A power conversion device controlled by the PWM control method according to claim 11.
  14. 　請求項１２に記載のＰＷＭ制御方法で制御されることを特徴とする電力変換装置。 A power conversion device controlled by the PWM control method according to claim 12.
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016092603A1 (en) * 2014-12-08 2016-06-16 株式会社日立産機システム Power conversion device and method for controlling power conversion device
EP3382870A1 (en) * 2017-03-31 2018-10-03 Mitsubishi Heavy Industries Thermal Systems, Ltd. Inverter apparatus, air conditioner, method of controlling inverter apparatus, and program
JP6585872B1 (en) * 2018-10-30 2019-10-02 東芝三菱電機産業システム株式会社 Power converter

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0690564A (en) * 1991-08-21 1994-03-29 Hitachi Ltd Equipment and method for controlling series multiple inverter
JPH1052062A (en) * 1996-07-31 1998-02-20 Fuji Electric Co Ltd Controller for three-level inverter
JP2002238266A (en) * 2002-02-20 2002-08-23 Hitachi Ltd Controller for pulse width modulation system inverter
JP2005045846A (en) * 2003-07-22 2005-02-17 Hitachi Ltd Power conversion apparatus
JP2006254671A (en) * 2005-03-14 2006-09-21 Denso Corp Three-phase voltage type inverter system
JP2007282484A (en) * 2007-03-26 2007-10-25 Hitachi Ltd Three-level power conversion device
WO2010119929A1 (en) * 2009-04-16 2010-10-21 株式会社明電舎 Method of controlling power conversion device
JP2011160529A (en) * 2010-01-29 2011-08-18 Aisin Aw Co Ltd Device for control of rotary electric machine

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0690564A (en) * 1991-08-21 1994-03-29 Hitachi Ltd Equipment and method for controlling series multiple inverter
JPH1052062A (en) * 1996-07-31 1998-02-20 Fuji Electric Co Ltd Controller for three-level inverter
JP2002238266A (en) * 2002-02-20 2002-08-23 Hitachi Ltd Controller for pulse width modulation system inverter
JP2005045846A (en) * 2003-07-22 2005-02-17 Hitachi Ltd Power conversion apparatus
JP2006254671A (en) * 2005-03-14 2006-09-21 Denso Corp Three-phase voltage type inverter system
JP2007282484A (en) * 2007-03-26 2007-10-25 Hitachi Ltd Three-level power conversion device
WO2010119929A1 (en) * 2009-04-16 2010-10-21 株式会社明電舎 Method of controlling power conversion device
JP2011160529A (en) * 2010-01-29 2011-08-18 Aisin Aw Co Ltd Device for control of rotary electric machine

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016092603A1 (en) * 2014-12-08 2016-06-16 株式会社日立産機システム Power conversion device and method for controlling power conversion device
JPWO2016092603A1 (en) * 2014-12-08 2017-06-08 株式会社日立産機システム Power converter and control method of power converter
CN107112936A (en) * 2014-12-08 2017-08-29 株式会社日立产机系统 The control method of power inverter and power inverter
CN107112936B (en) * 2014-12-08 2019-08-16 株式会社日立产机系统 The control method of power inverter and power inverter
EP3382870A1 (en) * 2017-03-31 2018-10-03 Mitsubishi Heavy Industries Thermal Systems, Ltd. Inverter apparatus, air conditioner, method of controlling inverter apparatus, and program
JP6585872B1 (en) * 2018-10-30 2019-10-02 東芝三菱電機産業システム株式会社 Power converter
WO2020089990A1 (en) * 2018-10-30 2020-05-07 東芝三菱電機産業システム株式会社 Power conversion device

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