JPH1052062A - Controller for three-level inverter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the breakage of the semiconductor switching element of the main circuit and stably control the element, by providing a limiting value for limiting a voltage command so that the command cannot exceed the amplitude of carriers, and controlling the voltage command based on the limiting value. SOLUTION: A voltage command V* is generated by multiplying a signal outputted from a waveform generating circuit 51 based on the phase of a voltage command by a modulation factor λ* and a bias B is added to or subtracted form the command V* by means of adders 66 and 65. A PWM signal is generated based on voltage commands VA* and VB* thus obtained. When the modulation factor λ* does not exceed a limiting value (Lmax -B), the outputs of correction amount computing circuits 36 and 37 become '0'. In an area where the magnitude of the modulation factor λ* exceeds the limiting value (Lmax -B), on the other hand, the voltage command values VA* and VB* are limited to the limiting value Lmax , because the value obtained by adding or subtracting the bias B to the voltage command V* exceeds the limiting value Lmax . Then, the output meeting the voltage command is outputted by correcting the shortage with the other voltage command.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control device for a three-level inverter capable of outputting three values as output voltages of respective phases, and more particularly, to a three-level inverter control device using PWM (pulse width modulation) control.
The present invention relates to a level inverter control device.

[0002]

2. Description of the Related Art FIG. 16 shows an example of a main circuit configuration of a three-level inverter. In the figure, 101 is a positive side capacitor as a DC input capacitor, 102 is a negative side capacitor, 81 to 92 are reverse conducting gate turn-off thyristors (hereinafter simply referred to as GTO) as semiconductor switching elements, 93 to 98 are coupling diodes, 10
Reference numeral 3 denotes a motor as a load, and 110 denotes a DC power supply. The connection point O between the positive side capacitor 101 and the negative side capacitor 102 is a neutral point.

In this type of three-level inverter, assuming that the DC voltage applied to the series circuit of the capacitors 101 and 102 in the main circuit configuration of FIG. 16 is E _d , the output voltage of each of the R, S, and T phases is + E _d / 2. , 0 (zero potential), −E _d / 2
It has the feature of being able to output values. Therefore, as compared with a two-level inverter that outputs two values of + E _d / 2 and −E _d / 2 as the output voltage of each phase, the number of output levels of the output voltage is increased and the harmonics can be reduced. ing. The main circuit configuration of the three-level inverter is described in, for example, Japanese Patent Application Laid-Open No. 56-74088.

In a three-level inverter, there are various methods for generating a PWM signal for operating a switching element of a main circuit, and typical examples include a unipolar modulation method and a dipolar modulation method. The unipolar modulation method uses an output phase voltage, for example, R, as shown in FIG.
During one cycle of the waveform of the phase voltage V _R, a pulse train that repeats the zero potential and the positive potential (+ E _d / 2) for a half cycle is output, and the zero potential and the negative potential (−E _d / The feature is that a pulse train that repeats 2) is output. In addition,
FIG. 22A illustrates a voltage command, and FIG. 22B illustrates a principle of comparison between two R-phase voltage commands and a carrier (triangular wave).

On the other hand, the dipolar modulation method is shown in FIG.
As shown in (3), in the waveform of the output phase voltage V _R,
That a pulse train and outputs the positive potential (+ E _d / 2) and the lower voltage (-E _d / 2) are alternately while through the zero potential is characterized. Here, FIG. 18A is a diagram illustrating a voltage command, and FIG. 18B is a diagram illustrating a principle of comparison between two voltage commands and a carrier.

As a prior art relating to these modulation methods, “A NOVEL APPROACH TO THEGENERATION AND
OPTIMIZATION OF THREE-LEBEL PWM WAVE FORM
S ”(PESC '88 Record. April 1988)
Pp. 1255 to 1262 describes switching between dipolar modulation and unipolar modulation depending on the magnitude of the output voltage for the purpose of reducing harmonics of a three-level inverter.

FIGS. 24 and 25 are diagrams showing the principle of the PWM method of the dipolar modulation and the unipolar modulation described in the above reference 1. FIG. As is apparent from these figures, in the prior art of Document 1, the comparison method between the triangular wave and the voltage command is different between the dipolar modulation and the unipolar modulation. It must be strictly controlled.

Another prior art is disclosed in Japanese Patent Laid-Open No. 5-1461.
Japanese Patent Publication No. 62 (hereinafter referred to as Document 2) describes a shift from dipolar modulation to partial dipolar modulation. Here, in the partial dipolar modulation, as shown in FIG. 20 (3), zero potential and positive potential (+ E _d / 2) which are characteristics of unipolar modulation are repeated during one cycle of the waveform of the output phase voltage. It has a period during which a pulse train is output, a period during which a pulse train repeating a zero potential and a negative potential (−E _d / 2) is output, and a positive potential (+) which is a characteristic of dipolar modulation.
E _d / 2) and a negative potential (−E _d / 2) are alternately output while passing a zero potential. In addition,
FIG. 20A illustrates a voltage command, and FIG. 20B illustrates a principle of comparison between two voltage commands and a carrier.

As another prior art, Japanese Patent Laid-Open Publication No.
No. 6160 (hereinafter referred to as Document 3) and
Japanese Patent No. 30564 (hereinafter referred to as Reference 4) has a description showing a method of transition between modulation methods including the above-described dipolar modulation, partial dipolar modulation, and unipolar modulation. Among them, the explanatory diagram of the modulation method shown in Document 4 shows a method of generating a PWM signal by comparing two different voltage commands with two carrier waves having different phases.

The prior art described above attempts to control from a low output voltage range to a high output voltage range by shifting from dipolar modulation to another modulation method. Japanese Patent Application Publication No. 7-194133 (hereinafter referred to as Document 5) introduces a method of continuously controlling a voltage from a low voltage including zero voltage to a somewhat high voltage by dipolar modulation.

A conventional technique according to the document 5 will be described with reference to FIGS. FIG. 17 is a main circuit for one phase of the three-level inverter (for example, the R phase in FIG. 16) and its control block diagram. FIGS. 18 and 19 show dipolar modulation and asymmetric dipolar modulation for explaining a control method. FIG.

First, in FIG. 17, adders 66 and 65 respectively add / subtract the bias amount B output by the bias amount setting circuit 1 with respect to the voltage command V ^* of FIG. And correction amount calculation circuits 36 and 37
Lead to. The correction amount calculation circuits 36 and 37 calculate the correction amounts S ₁ and S ₂ , and these are added by the adders 68 and 67 to the limiting circuit 3.
Voltage commands V _B ^* and V _A ^* are respectively obtained by adding the outputs to the outputs 2 and 31.

The voltage command V _A ^* is guided to a comparator 61 and compared with a carrier wave from a carrier oscillator 52.
The PWM signal P ₁ for switching the O81. Further, the voltage command V _B ^* is guided to the comparator 62 and compared with the carrier, and the result is used as the PW for switching the GTO 82.
The M signal P _2. Further, the PWM signals P ₁ and P ₂ are led to inverting circuits 71 and 72, respectively, and their outputs are output to GTO8.
The PWM signals P ₃ and P ₄ for performing switching of ₃ , 84 are obtained. In FIG. 17, reference numeral 3 denotes a limit value setting circuit for limiting the amplitude of the voltage command V ^* .

[0014] The PWM signals are similarly applied to the other phases.
No. and switch GTO 85-92 shown in FIG.
To run. As described above, FIG.
Pressure V _RIt is a waveform of.

In general, a voltage command V ^* in an inverter
Is represented by the product of the modulation factor λ ^* and the function f (θ) indicating the waveform of the voltage command. For example, assuming that the waveform of the voltage command is a sine wave shown in Equation 1, the voltage command V ^* is as shown in Equation 2.

[0016]

F (θ) = sin θ

[0017]

## EQU2 ## V ^* = λ ^* · sin θ

Now, when the magnitude of the modulation factor λ ^* is 0 ≦ λ ^* ≦ ( _Lmax− B) as shown in FIG. 18A, the magnitude of the voltage command V ^* is ( _Lmax− B). Never exceed. Here, _Lmax is the limit value of the voltage command, and B is the bias amount. At this time, since the value obtained by adding or subtracting the bias amount B from the voltage command V ^* does not exceed the amplitude of the carrier C, the correction amount S ₁ = S ₂ = 0. Therefore, in FIG. 18, the voltage command V ^* to the constant bias amount B subtraction or those obtained by adding the intact voltage command V _A ^* or V _B ^*, and the
These relationships are as shown in Equations 3 and 4.

[0019]

## EQU3 ## _VA ^* = V ^* -B

[0020]

V _B ^* = V ^* + B

[0021] On the other hand, in the region beyond the modulation rate lambda ^* size as shown in FIG. 19 (1) of the (L _max -B), the voltage command V ^*
The value obtained by adding or subtracting the bias amount B from FIG.
The hatched portion 9 exceeds the limit value _Lmax . In such a case, the size of the hatched portion is limited so that the voltage command does not exceed the limit value. However, since not obtained the required output voltage in this state, only the shortage correcting the hatched portion of the V _B ^* in the shaded portion of the V _A ^* (correction: S ₁₎ and,
Obtain the output voltage according to the voltage command. At this time,
^* The voltage command V _A, V _B ^* is expressed by Equation 5, Equation 6.

[0022]

[Number 5] _{^{V A * = V * -B +}} S 1

[0023]

## EQU6 ## V _B ^* = L _max

Further, the correction amount S ₁ in the equation (5) is calculated by the equation (7).
Thus, the voltage command V _A ^* is represented by Expression 8.

[0025]

S ₁ = V ^* − (L _max −B)

[0026]

[Equation 8] V _A ^* = 2V ^* -L _max

[0027] Similarly, the shaded portion of the V _A ^* that exceeds the limit value L _max, the correction for the hatched portion of the V _B ^* as the output voltage of the voltage command as obtained (correction: S ₂₎ is added .
At this time, ^* the voltage command V, V _A ^*, the relationship V _B ^* is expressed by Equation 9, Equation 10.

[0028]

[Equation 9] V _A ^* = -L _max

[0029]

[Number 10] _{^{V B * = V * + B}} -S 2

Further, since the correction amount S ₂ in Expression 10 is expressed by Expression 11, the voltage command V _B ^* is expressed by Expression 12.

[0031]

S ₂ = V ^* + (L _max −B)

[0032]

[Number 12] _{^{V B * = 2V * + L}} max

In a region where the magnitude of the voltage command V ^* does not exceed ( _Lmax- B), the correction amount S ₁ = S ₂ =
0, this time, ^* the voltage command V _A, V _B ^*, respectively Equation 3 is expressed by Equation 4. Here, the correction amount calculation circuits 36 and 37 in FIG. 17 calculate the correction amounts S ₁ and S ₁ shown in Expressions 13 and 14, respectively, according to the magnitude of the voltage command.
Calculate ₂ .

[0034]

(Equation 13)

[0035]

[Equation 14]

In the prior art described above, the output voltage can be continuously controlled from zero to the maximum value with respect to the voltage command. However, when the correction amount is large, the two voltage commands overlap, and
A PWM signal for simultaneously turning on and off the main circuit switching elements (for example, GTOs 81 and 82 and GTOs 83 and 84 in the R phase in FIG. 16) is generated. Further, when the correction amount further increases, one voltage command fixed by the limit value exceeds the other corrected voltage command. As a result, the switching state prohibited by the three-level inverter (for example, the R-phase in FIG. 16). In this state, the GTOs 81 and 84 are turned on).

[0037]

In the prior art of the above-mentioned document 1, the comparison method between the triangular wave and the voltage command is different between the dipolar modulation and the unipolar modulation, and the phase of both the triangular wave and the voltage command is changed when the modulation method is switched. There is a problem that control and management must be strictly performed, and the control method becomes complicated.

In the prior arts of Documents 3 and 4, the comparison method between the voltage command and the triangular wave is the same, but the control method is complicated because two different voltage commands are compared with the two triangle waves having different phases. Problem. In addition, the voltage command is the amplitude (peak value) of the carrier at the time of the shift of the modulation method.
Since the pulse width of the PWM signal generated in the vicinity is not particularly considered, another problem as described below occurs.

That is, in general, the pulse width minimum value of the PWM signal for turning on (or off) the switching element is determined due to the restriction of the operation of the main circuit in the inverter. If a pulse having a width smaller than the minimum pulse width is given to the switching element, the element cannot be sufficiently turned on (or turned off), which may cause element destruction.

Although not described in the prior art,
Usually, in a region where a pulse having a width smaller than the minimum pulse width is generated in order to prevent the above-described element destruction, the pulse width is fixed to the minimum value by another means to prevent the element destruction. The pulse width is set to zero so that no pulse is generated. However, if the pulse width is fixed in this way, another pulse width cannot be obtained because a pulse width required for a voltage command cannot be obtained. Note that such a problem of the minimum pulse width is the same as in the related art of the above-mentioned Document 2.

Further, in the prior art of the document 5, since the entire region of the output voltage is realized by the dipolar modulation, the above-described problem of complicating the control method and the problem of the minimum pulse width do not occur. . However, there is a possibility that the switching state is prohibited in the three-level inverter as described at the end of the related art, and there is a risk that the element may be destroyed.

Therefore, the present invention solves the above-mentioned various problems, and can obtain a desired output voltage without complicating the control method and causing element destruction, and stably operate the three-level inverter. It is an object of the present invention to provide a control device for a three-level inverter capable of performing the following.

[0043]

In order to solve the above-mentioned problems, the present invention has a means for setting two kinds of limit values for a voltage command in, for example, dipolar modulation, so that switching prohibited in a three-level inverter is provided. It was decided to prevent the occurrence of the condition. Further, dipolar modulation and unipolar modulation can be realized only by switching between the bias amount and the modulation factor.

That is, the invention according to claim 1 includes a DC power supply circuit having a DC input capacitor connected between a positive potential point and a negative potential point at both ends of the DC power supply and a neutral point therebetween, Both ends of three series circuits composed of the first to fourth semiconductor switching elements are connected to the positive potential point and the negative potential point, respectively, and the interconnection point of the second and third semiconductor switching elements corresponds to one phase. And a first coupling diode is connected between the first and second semiconductor switching elements and the neutral point, and
Two voltages obtained by adding or subtracting a certain bias amount to or from each phase voltage command of an inverter having a second coupling diode connected between the third and fourth semiconductor switching elements and the neutral point. In a control device of a three-level inverter for generating a PWM signal by comparing each of the commands with a carrier, a means for setting a first limit value not exceeding the amplitude of the carrier, and a second means not exceeding the first limit value. Means for setting a limit value, means for limiting the voltage command to a first limit value when one of the two voltage commands exceeds a first limit value, and a voltage command for exceeding the first limit value. Means for adding a value obtained by subtracting the first limit value from the other as a correction amount to the other voltage command, and limiting the voltage command to the second limit value when the other voltage command exceeds the second limit value. Means for performing

The invention according to claim 2 is the third invention according to claim 1.
The level inverter control device includes means for changing the first and second limit values according to the inverter frequency.

According to a third aspect of the present invention, there is provided a DC power supply circuit having a DC input capacitor connected between a positive potential point and a negative potential point at both ends of a DC power supply and a neutral point therebetween, and Both ends of three series circuits including the first to fourth semiconductor switching elements are connected to the positive potential point and the negative potential point, respectively, and the interconnection point of the second and third semiconductor switching elements is connected to the output of one phase. Terminal, a first coupling diode connected between the first and second semiconductor switching elements and the neutral point, and a third coupling element between the third and fourth semiconductor switching elements and the neutral point. A three-level signal generating a PWM signal by comparing each of two voltage commands obtained by adding or subtracting a certain amount of bias to or from each phase voltage command of an inverter having a second coupling diode connected thereto with a carrier wave. In the control device of the inverter,
Means for setting a limit value that does not exceed the amplitude of the carrier, means for changing the limit value according to the magnitude of the modulation factor, and when one of the two voltage commands exceeds the limit value, Means for limiting to the limit value, and means for adding a value obtained by subtracting the limit value from the voltage command exceeding the limit value as a correction amount to the other voltage command.

According to a fourth aspect of the present invention, there is provided a DC power supply circuit having a DC input capacitor connected between a positive potential point and a negative potential point at both ends of the DC power supply and a neutral point therebetween, and Both ends of three series circuits including the first to fourth semiconductor switching elements are connected to the positive potential point and the negative potential point, respectively, and the interconnection point of the second and third semiconductor switching elements is connected to the output of one phase. Terminal, a first coupling diode connected between the first and second semiconductor switching elements and the neutral point, and a third coupling element between the third and fourth semiconductor switching elements and the neutral point. A three-level signal generating a PWM signal by comparing each of two voltage commands obtained by adding or subtracting a certain amount of bias to or from each phase voltage command of an inverter having a second coupling diode connected thereto with a carrier wave. In the control device of the inverter,
Means for setting a limit value that does not exceed the amplitude of the carrier, means for changing the limit value according to the inverter frequency,
A means for limiting the voltage command to the limit value when one of the two voltage commands exceeds the limit value; and a correction value obtained by subtracting the limit value from the voltage command exceeding the limit value. Means for adding to the voltage command.

The fifth aspect of the present invention provides the third aspect of the present invention.
In the level inverter control device, means for changing the limit value according to the inverter frequency is also provided.

According to a sixth aspect of the present invention, there is provided a DC power supply circuit having a DC input capacitor connected between a positive potential point and a negative potential point at both ends of the DC power supply and a neutral point therebetween, and Both ends of three series circuits including the first to fourth semiconductor switching elements are connected to the positive potential point and the negative potential point, respectively, and the interconnection point of the second and third semiconductor switching elements is connected to the output of one phase. Terminal, a first coupling diode connected between the first and second semiconductor switching elements and the neutral point, and a third coupling element between the third and fourth semiconductor switching elements and the neutral point. A three-level signal generating a PWM signal by comparing each of two voltage commands obtained by adding or subtracting a certain amount of bias to or from each phase voltage command of an inverter having a second coupling diode connected thereto with a carrier wave. In the control device of the inverter,
There is provided means for switching the amplitude of the voltage command and the bias amount according to the magnitude of the modulation factor.

According to a seventh aspect of the present invention, there is provided a DC power supply circuit having a DC input capacitor connected between a positive potential point and a negative potential point at both ends of a DC power supply and a neutral point therebetween, and Both ends of three series circuits including the first to fourth semiconductor switching elements are connected to the positive potential point and the negative potential point, respectively, and the interconnection point of the second and third semiconductor switching elements is connected to the output of one phase. Terminal, a first coupling diode connected between the first and second semiconductor switching elements and the neutral point, and a third coupling element between the third and fourth semiconductor switching elements and the neutral point. A three-level signal generating a PWM signal by comparing each of two voltage commands obtained by adding or subtracting a certain amount of bias to or from each phase voltage command of an inverter having a second coupling diode connected thereto with a carrier wave. In the control device of the inverter,
There is provided means for switching the amplitude of the voltage command and the bias amount according to the inverter frequency.

The invention according to claim 8 is provided with a DC power supply circuit having a DC input capacitor connected between a positive potential point and a negative potential point at both ends of the DC power supply and a neutral point therebetween, and Both ends of three series circuits including the first to fourth semiconductor switching elements are connected to the positive potential point and the negative potential point, respectively, and the interconnection point of the second and third semiconductor switching elements is connected to the output of one phase. Terminal, a first coupling diode connected between the first and second semiconductor switching elements and the neutral point, and a third coupling element between the third and fourth semiconductor switching elements and the neutral point. A three-level signal generating a PWM signal by comparing each of two voltage commands obtained by adding or subtracting a certain amount of bias to or from each phase voltage command of an inverter having a second coupling diode connected thereto with a carrier wave. In the control device of the inverter,
There is provided means for switching the amplitude of the voltage command and the bias amount according to the magnitude of the modulation factor and the inverter frequency.

According to a ninth aspect of the present invention, in the control device for a three-level inverter according to the sixth, seventh or eighth aspect, means for limiting the amplitude of the two voltage commands is provided.

According to a tenth aspect of the present invention, in the three-level inverter control device according to the ninth aspect, there is provided a means for changing a limit value of the amplitude of the two voltage commands according to an inverter frequency.

According to an eleventh aspect of the present invention, in the control device of the three-level inverter according to the third aspect, there is provided means for changing the bias amount in accordance with the magnitude of the modulation factor.

According to a twelfth aspect of the present invention, there is provided a DC power supply circuit having a DC input capacitor connected between a positive potential point and a negative potential point at both ends of a DC power supply and a neutral point therebetween, and Both ends of three series circuits including the first to fourth semiconductor switching elements are connected to the positive potential point and the negative potential point, respectively, and the interconnection point of the second and third semiconductor switching elements is connected to the output of one phase. Terminal, a first coupling diode connected between the first and second semiconductor switching elements and the neutral point, and a third coupling element between the third and fourth semiconductor switching elements and the neutral point. A PWM signal is generated by comparing each of the two voltage commands obtained by adding or subtracting a certain amount of bias to or from each phase voltage command of an inverter having a second coupling diode connected therebetween with a carrier wave. The control device le inverter,
Means for setting a limit value that does not exceed the amplitude of the carrier, means for changing the limit value according to the inverter frequency,
Means for changing the bias amount according to the magnitude of the modulation factor; means for limiting the voltage command to the limit value when one of the two voltage commands exceeds the limit value; Means for adding a value obtained by subtracting the limit value from the applied voltage command to the other voltage command as a correction amount.

According to a thirteenth aspect of the present invention, in the control device of the three-level inverter according to the twelfth aspect, there is further provided a means for changing the limit value according to the magnitude of the modulation factor.

According to the fourteenth aspect of the present invention, there is provided an eleventh aspect.
14. The control device for a three-level inverter according to item 2 or 13, further comprising means for limiting the amplitude of the two voltage commands after the correction amount has been added.

According to a fifteenth aspect of the present invention, in the three-level inverter control device according to the fourteenth aspect, there is provided a means for changing a limit value of the amplitude of the two voltage commands according to an inverter frequency.

[0059]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is an embodiment of the first aspect of the present invention, and is a control block diagram of one phase (R phase in FIG. 16) of a main circuit of a three-level inverter. In FIG. 1, the same components as those in FIG. 17 are denoted by the same reference numerals.

In FIG. 1, reference numeral 51 denotes the phase θ of the voltage command.
Generates a voltage command waveform such as a sine wave
Road 1, a bias amount setting circuit for setting a bias amount B,
3 is a first control for the voltage command which does not exceed the amplitude of the carrier wave.
Limit value L_maxLimit value setting circuit for setting
Command V_A ^*, V_B ^*With the second limit value L_sLimit value to set
The setting circuits 31 and 32 are voltage commands V^*To the bias amount B
The result of the subtraction or addition is the limit value L_maxLimit to
Circuits 33 and 34 are outputs of the limiting circuits 31 and 32 and correction amounts.
S₁, S_TwoIs added to the limit value L_sLimited to voltage
Command V_A ^*, V_B ^*Output limit circuit, 36 and 37 are corrected
Quantity S₁, S_TwoThe correction amount calculation circuit 52 calculates the carrier wave
The generated carrier oscillators 61 and 62 have two voltage commands V
_A ^*, V_B ^*And GTO81, 82
PWM signal P for performing switching₁, P_TwoA comparator that computes
Reference numerals 71 and 72 denote PWM signals output from the comparators 61 and 62.
No.P ₁, P_TwoTo GTO83, 84
PWM signal P_Three, P_FourIs output. What
Here, 64 is a multiplier, and 65 to 68 are adders.

Next, the operation of this embodiment will be described. The signal output from the waveform generation circuit 51 is multiplied by the modulation factor λ ^* based on the phase θ of the voltage command to obtain a voltage command V ^* , and the adders 66 and 65 add or subtract the bias amount B to or from the voltage command V ^*. . Voltage command V _A ^* thus obtained, by the V _B ^* on the basis to generate a PWM signal.

If the modulation factor λ ^* does not exceed ( _Lmax− B) as shown in FIG.
The outputs of S37 and S37 are S ₁ = S ₂ = 0, and the voltage command V _A ^* ,
V _B ^* is represented by Equations 15 and 16, respectively.
Note that the bias amount B is an arbitrary constant value. Further, for example, limit value L _max is the magnitude of the modulation index to generate a pulse width minimum value, the limit value L _s may be smaller than the L _max.

[0063]

## EQU15 ## _VA ^* = V ^* -B

[0064]

[Number 16] V _B ^* = V ^* + _B

Here, if the voltage command waveform is a sine wave, V ^* in Expressions 15 and 16 becomes Expression 17.

[0066]

V ^* = λ ^* · sin θ

[0067] On the other hand, in the region beyond the modulation rate lambda ^* size as shown in FIG. 19 (1) of the (L _max -B), the voltage command V ^*
The value obtained by adding or subtracting the bias amount B from FIG.
The limit value _Lmax is exceeded at the hatched portion 9 (2). In this case, the voltage command V _A ^* by the shaded portion, part of, limits the V _B ^* to limit L _max. Then, the insufficient shaded portion is corrected by the other voltage command as in the shaded portion (correction amount: S ₁ ), and an output according to the voltage command is obtained. At this time, the voltage command V _A ^*, V _B ^*, respectively Equation 1
8, represented by Equation 19.

[0068]

[Number 18] _{^{V A * = V * -B +}} S 1

[0069]

[Equation 19] V _B ^* = L _max

Incidentally, the correction amount S ₁ in Expression 18 is represented by Expression 20. Therefore, the voltage command V _A ^* is as shown in Expression 21.

[0071]

S ₁ = V ^* − (L _max −B)

[0072]

[Number 21] V _A ^* = 2V ^* -L _max

Similarly, limit value L_maxShaded area beyond
Is shaded so that the output voltage as specified by the voltage command can be obtained.
To correct (correction amount: S_Two). At this time, the voltage command
V_A ^*, V_B ^*Are represented by Equations 22 and 23, respectively.
It is.

[0074]

[Number 22] V _A ^* = -L _max

[0075]

V _B ^* = V ^* + B-S ₂

The correction amount S ₂ in Expression 23 is represented by Expression 24, whereby the voltage command V _B ^* becomes Expression 25.

[0077]

S ₂ = V ^* + (L _max −B)

[0078]

[Number 25] _{^{V B * = 2V * + L}} max

[0079] Next, when the modulation factor lambda ^* further increases, eventually the two voltage command V _A ^*, so that V _B ^* overlap. To prevent this, as shown in principle diagram of an asymmetric dipolar overmodulation of Figure 21, if the hatched portion as shown in FIG. 21 (2) exceeds the limit value L _s limits this to L _s.
At this time, the voltage command V _A ^* is given by Equation 26, and the voltage command V _A ^*
_{Since B} ^* has already reached the limit value, Equation 19 is obtained.

[0080]

[Equation 26] V _A ^* = L _s

[0081] Similarly, in the shaded portion of FIG. 21 (2), limits the voltage command V _B ^* as shown in Equation 27 -L _s.
Since the voltage command V _A ^* has already reached the limit value,
It becomes 2.

[0082]

V _B ^* = − L _s

In the other sections than the above, the voltage command V _A ^*
Are the above-described equations 15, 21, and 22, and the voltage command V _B ^* is the above-described equations 16, 19, and 25.

Next, an embodiment of the present invention will be described. FIG. 2 is a control block diagram of one phase of the main circuit of the three-level inverter (for example, the R phase in FIG. 16) as in FIG. 3 to 15 also show control block diagrams for one R-phase of the main circuit. In FIG.
4a is a first limit value L according to the inverter frequency _finv.
limit value calculation circuit for calculating the _max, 6a is a limit value calculation circuit for calculating a second limit value L _s in accordance with the inverter frequency f _inv, the same reference numerals for the other parts is the same as FIG. 1 The description is omitted here.

When the inverter frequency f _inv is high,
Ratio NN the inverter frequency f _inv and the carrier frequency f _c
It is good to adopt synchronous PWM which makes the constant as shown in Expression 28. In this case, the carrier frequency f _c by increasing the inverter frequency f _inv is also increased.

[0086]

F _c = NN · f _inv

For this reason, when the inverter frequency increases in a state where the limit value is fixed and the voltage command is limited to the limit value, the period of the triangular wave as a carrier wave is shortened, The width of the PWM signal may be shorter than the minimum pulse width. Therefore, in the invention of claim 2, by changing the limit values L _max and L _{s according} to the inverter frequency f _inv , the width of the PWM signal is prevented from becoming shorter than the minimum pulse width.

The operation will be described below. In limit value calculation circuit 4a of FIG. 2, operations such as Equation 29 to determine the limit value L _max and an inverter frequency f _inv and the pulse width minimum value T _{m in} is performed.

[0089]

L _max = 1-2 · _finv · NN · T _min

[0090] In the limit value calculation circuit 6a of FIG. 2, operations such as Equation 30 to determine the limit value L _s from the inverter frequency f _inv and the pulse width minimum value T _min is performed.
In this equation 30, T ₀ is two voltage commands V _A ^* , V _B ^*
Is an arbitrary numerical value for preventing overlapping.

[0091]

L _s = 1-2 · _finv · NN · (2 · T ₀ + T _min )

Next, an embodiment of the third aspect of the present invention will be described. In FIG. 3, reference numeral 4b denotes a limit value calculation circuit for switching the size of the limit value L between _Lmax and 1.0 according to the size of the modulation factor λ ^* , and the other parts are the same as those in FIG.

This operation will be described ^{. If} the magnitude of the modulation factor λ ^* does not exceed ( _Lmax− B), the correction amount calculation circuit 3
6 and 37 are S ₁ = S ₂ = 0, and the voltage commands V _A ^* ,
V _B ^* is expressed by the above formulas 15 and 16, and a waveform comparison diagram is as shown in FIG. Also, when the modulation factor lambda ^* size exceeds (L _max -B) is represented by the voltage command V _A ^*, V _B ^*, and the correction amount S _1, S ₂ each Equation 18 Equation 25 FIG. 19 is a waveform comparison diagram.

Modulation rate λ^*Is further increased, and (1.0−
In case of exceeding B), as shown in FIG.
Pressure command V_A ^*, V_B ^*Is set to 1.0. Shown in FIG.
As shown, the modulation factor λ^*Is greater than (1.0-B)
In the shaded area, the voltage command V _A ^*, V_B ^*To the limit of 1.0
(Amplitude of carrier wave). However, it is necessary as it is
Since the output voltage cannot be obtained, V_B ^*Missing diagonal lines
Part V_A ^*(Correction amount: S₁). this
When the voltage command V _A ^*, V_B ^*And correction amount S₁, S_TwoIs Equation 31
To 34.

[0095]

[Number 31] _{^{V A * = V * -B +}} S 1

[0096]

V _B ^* = 1.0

[0097]

S ₁ = V ^* − (1.0−B)

[0098]

[Expression 34] S ₂ = 0

Similarly, the correction (correction amount: S ₂ ) is performed from the hatched portion of V _A ^{* to} the hatched portion of V _B ^* to obtain an output voltage according to the voltage command. At this time, the voltage command V _A ^* ,
V _B ^* and the correction amounts S ₁ and S ₂ are represented by Expressions 35 to 38.

[0100]

V _A ^* = − 1.0

[0101]

V _B ^* = V ^* + B + S ₂

[0102]

[Number 37] ^{_{S 2 = V * + (1.0}} -B)

[0103]

[Formula 38] S ₁ = 0

Here, in a section where the magnitude of the voltage command V ^* other than the above does not exceed (1.0−B), the correction amount S ₁ = S ₂
= 0, and the voltage commands V _A ^* and V _B ^* are expressed by Equations (15) and (16).
It is represented by Output L of limit value calculation circuit 4b in FIG.
Can be switched between L _max and 1.0 by an arbitrary modulation factor λ ^* . The switching condition is, for example, not to be overlapped with the hatched portion in FIG. The output L of the limit value calculation circuit 4b according to the magnitude of the modulation factor λ ^* is as shown in Expression 39.

[0105]

[Equation 39]

Further, the correction amount calculation circuits 36 and 37 calculate the correction amounts S ₁ and S _{2 according} to Expressions 40 and 41 according to the magnitude of the voltage command.

[0107]

(Equation 40)

[0108]

[Equation 41]

Next, an embodiment of the present invention will be described. In FIG. 4, reference numeral 4c denotes a limit value calculation circuit for calculating a limit value L from the inverter frequency _finv . The other parts are the same as those in FIG.

[0110] As described above, the synchronous PWM, also increases the carrier frequency f _c by increasing the inverter frequency f _inv, which may cause a short pulse than the pulse width minimum value when the predetermined limit value. Therefore, it is necessary to change the limit value according to the inverter frequency f _inv . In the limit value calculation circuit 4c of FIG. 4, for example, a calculation such as Expression 42 is performed, and the limit value L is switched between _Lmax and 1.0. In this equation 42, L _max is not a constant value,
It is calculated from the inverter frequency f _inv by Expression 29 shown above.

[0111]

(Equation 42)

An embodiment of the invention will be described. In FIG. 5, reference numeral 4d denotes a limit value calculation circuit that calculates a limit value L based on the magnitude of the modulation factor λ ^* and the inverter frequency f _inv , and the other parts are the same as those in FIG. This embodiment has both the method of calculating from the modulation factor λ ^{* in the} embodiment of FIG. 3 and the method of calculating from the inverter frequency f _{inv in the} embodiment of FIG. The operation can be easily understood from the embodiment shown in FIGS.

Next, an embodiment of the invention will be described.
You. In FIG. 6, 2a is a modulation factor λ. ^*By the size of
A bias amount calculation circuit for calculating the assembling amount B, 7a is a modulation rate
λ^*Voltage command V according to the magnitude of^*Switch the amplitude S of
It is an amplitude switching circuit. Other parts are the same as those in FIGS.
Although one component is given the same number,
In the state, the outputs of the adders 65 and 66 are directly used as the voltage command V
_A ^*, V_B ^*Are input to the comparators 61 and 62.

The operation will be described below.
Is multiplied by the output S of the amplitude switching circuit 7a to obtain the voltage command V ^* .
Then, a bias amount calculation circuit 2a bias amount B output from, by adding or subtracting to the voltage command V ^* by the adder 66, 65, the new voltage command V _A ^*, to obtain a V _B ^*.

Here, the amplitude S of the voltage command and the bias amount B
The switching condition modulation factor lambda ^* of the parts in the case of (L _max -B) does not exceed the case of exceeding the modulation factor lambda ^* is (L _max -B)
Voltage command V _A ^* when not exceeding, V _B ^* The formula 43, the formula 44. The waveform comparison diagram is the same as that in FIG.

[0116]

(43) _VA ^* = V ^* -B

[0117]

[Number 44] V _B ^* = V ^* + _B

In the equations 43 and 44, the voltage command V ^* is as shown in the equation 2. When the modulation factor λ ^* exceeds ( _Lmax− B), the equations are as shown in Equations 45 and 46, and the waveform comparison diagram is as shown in FIG. The voltage command V ^* in these equations is as shown in equation 47.

[0119]

V _A ^* = V ^* −1.0

[0120]

[Equation 46] V _B ^* = V ^* + 1.0

[0121]

V ^* = 2 · λ ^* · sin θ

When the amplitude S of the voltage command and the magnitude of the bias amount B according to the magnitude of the modulation factor λ ^* are arranged, Equation 4 is obtained.
8. Equation 49 is obtained.

[0123]

[Equation 48]

[0124]

[Equation 49]

Next, an embodiment of the present invention will be described. In FIG. 7, reference numeral 2b denotes a bias amount calculation circuit for calculating a bias amount B according to the inverter frequency f _inv ;
Is an amplitude switching circuit for switching the amplitude S of the voltage command from the inverter frequency f _inv as described later. The other parts are the same as those in FIG.

This embodiment is different from the embodiment of FIG.
The amplitude S and the bias amount B are converted to the modulation rate λ. ^*According to the size of
What has been switched to the inverter frequency f_invAccording to
The voltage command V_A ^*, V_B
^*, V^*Is represented by Expressions 43 to 47. Also,
Inverter frequency at switching point of width S and bias amount B
Number f_pMay be set arbitrarily. In this embodiment,
The amplitude S and the bias amount B of the pressure command are determined by the inverter frequency.
f_invEquations 50 and 51 are obtained according to

[0127]

[Equation 50]

[0128]

(Equation 51)

An embodiment of the present invention will be described. In FIG. 8, 2c inverter frequency f _inv and the bias amount calculation circuit for calculating a bias amount B according to the modulation factor lambda ^* size, 7c inverter frequency f _inv and the modulation factor lambda ^* of the voltage in accordance with the size This is an amplitude switching circuit that switches the amplitude S of the command. The other parts are the same as in FIG.
Description is omitted. In this embodiment, the amplitude S and the bias amount B are calculated from both the inverter frequency f _inv and the modulation factor λ ^* .

Next, embodiments of the present invention will be described. FIG. 9 shows an embodiment of the ninth aspect of the present invention. Reference numerals 2a and 7a denote a bias amount calculation circuit and an amplitude switching circuit similar to those shown in FIG. 38 and 39 are voltage commands V, respectively.
_A ^*, a limiting circuit of the V _B ^*, acts to limit the voltage command V _A ^*, limit V _B ^* value L _max. Figure 10 shows an embodiment of the invention of claim 10 wherein, 4a is a limit value calculation circuit for calculating a limit value L _max of the same an inverter frequency f _inv and FIG. The other parts of FIGS. 9 and 10 are the same as in the embodiment of FIG.

The operation of these embodiments is basically the same as that of the embodiment shown in FIG. 6. When the output of the adder 65 or 66 does not exceed the limit value _Lmax , the voltage command V _A ^* , V _B ^* , V ^* , amplitude S, and bias amount B are given by Equation 43
Equation 51 is obtained, and waveform comparison diagrams are also shown in FIGS. However, when the output of FIG. 23 (2) of the adder 65 or 66 as exceeds the limit value L _max, ^* voltage command V _A, V _B ^* becomes as Equation 52, Equation 53.

[0132]

V _A ^* = L _max (V _A ^* > L _max )

[0133]

[Number 53] ^{_{V B * = -L max (V}} B * <-L max)

[0134] In the portion where the voltage command V _A ^* other than the above, V _B ^* does not exceed the limit value L _max, ^* voltage command V _A, V _B ^*, respectively Equation 45 becomes Equation 46. Further, in the embodiment of FIG. 10, the limit value _Lmax is changed as in the embodiment of FIG. Here, the embodiment of FIG. 9 and FIG.
7 and 8 are also applicable.

Next, an embodiment of the present invention will be described. In FIG. 11, reference numerals 2a and 7a denote a bias amount calculation circuit and an amplitude switching circuit similar to that of FIG. 6, and 4b a limit value calculation circuit similar to that of FIG. 3, and the other parts are the same as those of the embodiment of FIG.

This operation will be described ^{. If} the magnitude of the voltage command V ^* does not exceed (L _max -B), the outputs of the correction amount calculation circuits 36 and 37 are S ₁ = S ₂ = 0, and the voltage command V ^* _a ^*, V _B ^* is represented by equation 15, equation 16, waveform comparison diagram is as shown in Figure 18. If the voltage command V ^* size exceeds (L _max -B), ^* voltage command V _A, V _B ^*, and the correction amount S _1, S ₂ is represented by equation 18 to equation 25, waveform comparison diagram Figure It looks like 19.

Modulation rate λ^*Becomes larger, and V_A ^*, V_B ^*But
If they overlap, the voltage command V _A ^*, V_B ^*Equation 5
4, as shown in Equation 55. In these equations,
Pressure command V^*Is represented by Equation 56, and the waveform comparison diagram is shown in FIG.
It becomes 2.

[0138]

V _A ^* = V ^* -1.0

[0139]

V _B ^* = V ^* + 1.0

[0140]

V ^* = 2 · λ ^* · sin θ

Here, the amplitude S of the voltage command and the bias amount B
Equations 57 and 58 are obtained by rearranging the sizes of

[0142]

[Equation 57]

[0143]

[Equation 58]

The output L of the limit value calculation circuit 4b in FIG.
Figure 3 and according to the same manner as the modulation index lambda ^* is switched to the L _{m ax} and 1.0. For example, the output L of the limit value calculation circuit 4b is set as shown in Expression 59, provided that the hatched portion in FIG.

[0145]

[Equation 59]

The correction amount calculation circuits 36 and 37 calculate the correction amounts S ₁ and S ₂ according to the equations 60 and 61 according to the magnitude of the voltage command.

[0147]

[Equation 60]

[0148]

[Equation 61]

Next, an embodiment of the present invention will be described. In FIG. 12, reference numeral 4c denotes a limit value calculation circuit similar to that of FIG. 4, and the other parts are the same as those of the embodiment of FIG. This embodiment includes a limit value calculation circuit 4c for calculating a limit value L based on the inverter frequency f _inv , instead of the limit value calculation circuit 4b in FIG. The content of the operation in this operation circuit 4c is expressed by the above-mentioned equation (4).
According to 2.

An embodiment of the invention will be described.
In FIG. 13, reference numeral 4d denotes a limit value calculation circuit similar to that of FIG. 5, and the other parts are the same as those of the embodiment of FIG.
In this embodiment, as a method of calculating the limit value L, FIG.
A method of calculating the modulation rate lambda ^* shown in, in which both of a method of calculating the inverter frequency f _inv shown in FIG.

Finally, an embodiment of the invention according to claims 14 and 15 will be described. Figure 14 shows an embodiment of the invention according to claim 14, this embodiment, in the embodiment of FIG. 11, the voltage command V _A ^*, limiting circuit in order to limit the limit value L ₂ of the V _B ^* 38 , 39 are added to generate the limit value L ₂ from the limit value setting circuit 3.

[0152] Figure 15 shows an embodiment of the invention according to claim 15, 4e is a limit value calculation circuit for calculating a limit value L _2. This embodiment is to vary as Equation 62 the limit values L ₂ in accordance with the inverter frequency f _inv. In this formula 62, NN is the ratio of the inverter frequency f _inv and the carrier frequency f _c, T _min represents the pulse width minimum.

[0153]

[Number 62] _{L 2 = 1.0-2 · f inv ·} NN · T min

The operation of the embodiment shown in FIGS. 14 and 15 is basically the same as that of the embodiment shown in FIG. Therefore, when the output of the adder 67 or 68 does not exceed the limit value L _max, the voltage command ^{_{V A *, V B *,}} V *, the amplitude S and the bias amount B
Are as shown in Expressions 15 to 25 and Expressions 54 to 61, and the waveform comparison diagrams are also as shown in FIGS. 18, 19, and 22.

However, when the output of the adder 67 or 68 exceeds the limit value L ₂ (L _max ) as shown in FIG. 23, the voltage commands V _A ^* and V _B ^* are expressed by the following equations 63 and 64. Become.

[0156]

V _A ^* = L _max (V _A ^* > L _max )

[0157]

[Number 64] ^{_{V B * = -L max (V}} B * <-L max)

It is to be noted that the voltage command other than the above is applied to the limit value L ₂ (L
In the portion not exceeding the _max), the voltage command V _A ^*, V _B ^* The formula 4
5. Equation 46 is obtained. Here, the embodiments of FIGS. 14 and 15 are also applicable to the embodiments of FIGS.

[0159]

As described above, according to the present invention, a limit value for limiting the amplitude of the carrier wave is not provided, and the voltage command is controlled so as not to exceed the limit value. The switching element can be prevented from being destroyed, and at the same time, the three-level inverter can be stably controlled by eliminating the uncontrollable period of the output voltage. Further, by switching the limit value, the amplitude, the bias amount, and the like, it is possible to smoothly transition between different modulation schemes.

[Brief description of the drawings]

FIG. 1 is a control block diagram showing an embodiment of the invention described in claim 1.

FIG. 2 is a control block diagram showing an embodiment of the invention described in claim 2;

FIG. 3 is a control block diagram showing an embodiment of the invention described in claim 3;

FIG. 4 is a control block diagram showing an embodiment of the invention described in claim 4;

FIG. 5 is a control block diagram showing an embodiment of the invention described in claim 5;

FIG. 6 is a control block diagram showing an embodiment of the invention described in claim 6;

FIG. 7 is a control block diagram showing an embodiment of the invention described in claim 7;

FIG. 8 is a control block diagram showing an embodiment of the invention described in claim 8;

FIG. 9 is a control block diagram showing an embodiment of the invention described in claim 9;

FIG. 10 is a control block diagram showing an embodiment of the invention described in claim 10;

FIG. 11 is a control block diagram showing an embodiment of the invention described in claim 11;

FIG. 12 is a control block diagram showing an embodiment of the invention described in claim 12;

FIG. 13 is a control block diagram showing an embodiment of the invention described in claim 13;

FIG. 14 is a control block diagram showing an embodiment of the invention described in claim 14;

FIG. 15 is a control block diagram showing an embodiment of the invention described in claim 15;

FIG. 16 is a configuration diagram of a main circuit of a three-level inverter.

FIG. 17 is a main circuit and control block diagram for one phase of a three-level inverter.

FIG. 18 is a principle diagram of a dipolar modulation method.

FIG. 19 is a diagram illustrating the principle of asymmetric dipolar modulation.

FIG. 20 is a diagram illustrating the principle of partial dipolar modulation.

FIG. 21 is a diagram illustrating the principle of asymmetric dipolar overmodulation.

FIG. 22 is a principle diagram of a unipolar modulation method.

FIG. 23 is a diagram illustrating the principle of the unipolar overmodulation method.

FIG. 24 is a diagram showing P of dipolar modulation described in Reference 1.
It is a principle diagram of a WM system.

FIG. 25 shows P of unipolar modulation described in Reference 1.
It is a principle diagram of a WM system.

[Explanation of symbols]

 1 Bias amount setting circuit 2a, 2b, 2c Bias amount calculation circuit 3, 5 Limit value setting circuit 4a, 4b, 4c, 4d, 4e, 6a Limit value calculation circuit 7a, 7b, 7c Amplitude switching circuit 31-34, 38, 39 Limiting circuit 36,37 Correction amount calculating circuit 51 Waveform generating circuit 52 Carrier oscillator 61,62 Comparator 64 Multiplier 65-68 Adder 71,72 Inverting circuit 81-84 GTO 93,94 Diode

Claims (15)

[Claims] A DC power supply circuit having a DC input capacitor connected between a positive potential point and a negative potential point at both ends of a DC power supply and a neutral point therebetween, and wherein first to fourth semiconductor switching circuits are provided. Both ends of three series circuits composed of elements are connected to the positive potential point and the negative potential point, respectively, and the interconnection point of the second and third semiconductor switching elements is one.
The first coupling diode is connected between the first and second semiconductor switching elements and the neutral point, and the third and fourth semiconductor switching elements are connected to the neutral terminals between the first and second semiconductor switching elements and the neutral point. The two voltage commands obtained by adding or subtracting a certain amount of bias to or from each phase voltage command of the inverter in which the second coupling diode is connected to the carrier point are compared with a carrier wave to convert the PWM signal. In the control device for a three-level inverter generated, a means for setting a first limit value not exceeding the amplitude of the carrier, a means for setting a second limit value not exceeding the first limit value, and the two voltages Means for limiting the voltage command to the first limit value when one of the commands exceeds the first limit value, and correcting a value obtained by subtracting the first limit value from the voltage command exceeding the first limit value. As the other voltage command And a means for limiting the voltage command to a second limit value when the other voltage command exceeds a second limit value. . 2. The control device for a three-level inverter according to claim 1, further comprising: means for changing the first and second limit values in accordance with the inverter frequency. 3. A first to fourth semiconductor switching device comprising a DC power supply circuit having a DC input capacitor connected between a positive potential point and a negative potential point at both ends of a DC power supply and a neutral point therebetween. Both ends of three series circuits composed of elements are connected to the positive potential point and the negative potential point, respectively, and the interconnection point of the second and third semiconductor switching elements is one.
The first coupling diode is connected between the first and second semiconductor switching elements and the neutral point, and the third and fourth semiconductor switching elements are connected to the neutral terminals between the first and second semiconductor switching elements and the neutral point. The two voltage commands obtained by adding or subtracting a certain amount of bias to each phase voltage command of an inverter in which a second coupling diode is connected to the inverter and comparing each of the two voltage commands with a carrier wave to generate a PWM signal. In the control device for the generated three-level inverter, means for setting a limit value that does not exceed the amplitude of the carrier wave, means for changing the limit value according to the magnitude of the modulation factor, and one of the two voltage commands is Means for limiting the voltage command to the limit value when the limit value is exceeded; means for adding a value obtained by subtracting the limit value from the voltage command exceeding the limit value to the other voltage command as a correction amount A control device for a three-level inverter, comprising: 4. A first to fourth semiconductor switching device comprising a DC power supply circuit having a DC input capacitor connected between a positive potential point and a negative potential point at both ends of a DC power supply and a neutral point therebetween. Both ends of three series circuits composed of elements are connected to the positive potential point and the negative potential point, respectively, and the interconnection point of the second and third semiconductor switching elements is one.
The first coupling diode is connected between the first and second semiconductor switching elements and the neutral point, and the third and fourth semiconductor switching elements are connected to the neutral terminals between the first and second semiconductor switching elements and the neutral point. The two voltage commands obtained by adding or subtracting a certain amount of bias to or from each phase voltage command of the inverter in which the second coupling diode is connected to the carrier point are compared with a carrier wave to convert the PWM signal. In the control device of the generated three-level inverter, a means for setting a limit value that does not exceed the amplitude of the carrier, a means for changing the limit value according to the inverter frequency, and one of the two voltage commands sets the limit value Means for limiting the voltage command to the limit value when the voltage command exceeds the limit value, and adding a value obtained by subtracting the limit value from the voltage command exceeding the limit value to the other voltage command as a correction amount A control device for a three-level inverter, comprising: a stage; 5. The control device for a three-level inverter according to claim 3, further comprising means for changing the limit value according to an inverter frequency. 6. A first to fourth semiconductor switching device comprising a DC power supply circuit having a DC input capacitor connected between a positive potential point and a negative potential point at both ends of a DC power supply and a neutral point therebetween. Both ends of three series circuits composed of elements are connected to the positive potential point and the negative potential point, respectively, and the interconnection point of the second and third semiconductor switching elements is one.
The first coupling diode is connected between the first and second semiconductor switching elements and the neutral point, and the third and fourth semiconductor switching elements are connected to the neutral terminals between the first and second semiconductor switching elements and the neutral point. The two voltage commands obtained by adding or subtracting a certain amount of bias to each phase voltage command of an inverter in which a second coupling diode is connected to the inverter and comparing each of the two voltage commands with a carrier wave to generate a PWM signal. A control device for a three-level inverter, comprising: means for switching the amplitude of a voltage command and the bias amount according to the magnitude of a modulation factor. 7. A first to fourth semiconductor switching device comprising a DC power supply circuit having a DC input capacitor connected between a positive potential point and a negative potential point at both ends of a DC power supply and a neutral point therebetween. Both ends of three series circuits composed of elements are connected to the positive potential point and the negative potential point, respectively, and the interconnection point of the second and third semiconductor switching elements is one.
The first coupling diode is connected between the first and second semiconductor switching elements and the neutral point, and the third and fourth semiconductor switching elements are connected to the neutral terminals between the first and second semiconductor switching elements and the neutral point. The two voltage commands obtained by adding or subtracting a certain amount of bias to or from each phase voltage command of the inverter in which the second coupling diode is connected to the carrier point are compared with a carrier wave to convert the PWM signal. A control device for a three-level inverter, comprising: means for switching the amplitude of a voltage command and the amount of bias according to the inverter frequency. 8. A first to fourth semiconductor switching device comprising a DC power supply circuit having a DC input capacitor connected between positive and negative potential points at both ends of the DC power supply and a neutral point therebetween. Both ends of three series circuits composed of elements are connected to the positive potential point and the negative potential point, respectively, and the interconnection point of the second and third semiconductor switching elements is one.
The first coupling diode is connected between the first and second semiconductor switching elements and the neutral point, and the third and fourth semiconductor switching elements are connected to the neutral terminals between the first and second semiconductor switching elements and the neutral point. The two voltage commands obtained by adding or subtracting a certain amount of bias to or from each phase voltage command of the inverter in which the second coupling diode is connected to the carrier point are compared with a carrier wave to convert the PWM signal. A control device for a three-level inverter, comprising: means for switching the amplitude of a voltage command and the bias amount according to the magnitude of a modulation factor and the inverter frequency. 9. The control device for a three-level inverter according to claim 6, further comprising: means for limiting an amplitude of the two voltage commands. 10. The control device for a three-level inverter according to claim 9, further comprising means for changing a limit value of the amplitude of the two voltage commands according to an inverter frequency. apparatus. 11. The control device for a three-level inverter according to claim 3, further comprising: means for changing the amount of bias according to the magnitude of a modulation factor. 12. A first to fourth semiconductor switching device comprising a DC power supply circuit having a DC input capacitor connected between positive and negative potential points at both ends of the DC power supply and a neutral point therebetween. Both ends of three series circuits composed of elements are connected to the positive potential point and the negative potential point, respectively.
An interconnection point between the second and third semiconductor switching elements is connected to an output terminal for one phase, and a first coupling diode is connected between the first and second semiconductor switching elements and the neutral point. And a bias amount is obtained by adding or subtracting a certain bias amount to or from each phase voltage command of an inverter in which a second coupling diode is connected between the third and fourth semiconductor switching elements and the neutral point. In a control device of a three-level inverter that generates a PWM signal by comparing each of two voltage commands with a carrier, means for setting a limit value that does not exceed the amplitude of the carrier, and changing the limit value according to the inverter frequency Means for changing the bias amount in accordance with the magnitude of the modulation factor; and when one of the two voltage commands exceeds the limit value, the voltage command is controlled to the limit value. And a means for adding a value obtained by subtracting the limit value from the voltage command exceeding the limit value to the other voltage command as a correction amount. 13. The control device for a three-level inverter according to claim 12, further comprising: means for changing the limit value according to the magnitude of a modulation factor. 14. The method according to claim 11, 12 or 13.
A control device for a three-level inverter, comprising: means for limiting the amplitude of the two voltage commands after the correction amount is added. 15. The control device for a three-level inverter according to claim 14, further comprising means for changing a limit value of the amplitude of the two voltage commands according to an inverter frequency. apparatus.