JP2010199348A - Semiconductor memory and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a variable resistance semiconductor memory for reducing a forming process load and dispersion of a memory bit. <P>SOLUTION: A variable resistance memory bit part 1 composed of a first electrode section 12, a second electrode section 13, a variable resistance layer 14 and a third electrode section 15 is three-dimensionally constituted on a conductor 10, an insulator 20 and an insulating layer 11, and a conductor 16 is disposed at the upper part. The conductor 10 or the conductor 16 is made a bit line 32, and the first electrode section 12 is made a word line 33 to apply voltage or an electric current to the variable resistance layer 14 containing a metal oxide as a main component, thus achieving the resistance change of the memory bit part 1. To form the variable resistance semiconductor memory, a through-hole part is formed in the insulating layer 11, and the exposed surface of the conductive layer 12 is provided with an electrode 13 made of metal nano particles using ferritin containing a metal compound. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method of manufacturing a resistance change type semiconductor memory.

  In recent years, there is an increasing demand for miniaturization of memory elements. Accordingly, a semiconductor memory element (nonvolatile memory element) that records information by a change in electric resistance rather than a charge capacity has attracted attention as a memory element that is not easily affected by miniaturization.

  The resistance change type memory element includes a resistance change layer and two electrodes arranged so as to sandwich the resistance change layer. This element can take a plurality of states having different electric resistances, and the state can be changed by applying a predetermined voltage or current between the electrodes. One selected state is basically maintained (that is, non-volatile) unless a predetermined operation is applied. Such an effect is called a giant resistance change effect (CER). Since there is no size problem in these CER effects and the resistance change is insignificant, semiconductor memory elements are highly expected as next-generation nonvolatile memories that are required to be miniaturized. According to a report described in J. Appl. Phys., Vol.88 pp.2805, 2000 (Non-Patent Document 1) by Hick Mott, hysteresis is observed in current-voltage characteristics of various oxides. It has been pointed out that the so-called CER effect may appear. As a semiconductor memory element, Japanese Patent Publication No. 2002-537627 (Patent Document 1) discloses an element using various oxides. Nonvolatile memories formed by using these elements are called resistance change random access memories (Resistance RAM: ReRAM) and have attracted attention. In particular, these nonvolatile memory elements that record information by a change in electric resistance value have high expectations for ultra-high integration due to small size restrictions. Examples of materials that promote resistance change applied to ReRAM include perovskite materials disclosed in Patent Document 1 and International Electron Device Meeting 2004 (Tech. Dig.-Int. Electron Devices Meet. 2004, by Bek et al. 587) The oxides of nickel, titanium, hafnium, zirconium shown in (Non-patent Document 2), and Japanese Patent No. 3919205 (Patent Document 2) include iron oxides, international electron devices by Way et al. Tantalum oxides shown in Meeting 2008 (Tech. Dig.-Int. Electron Devices Meet. 2008, 293) (Non-Patent Document 3) have been studied.

  In recent years, an operation mechanism showing such a large resistance change has also been clarified. According to a report described in Odagawa's Applied Physics Letter (Appl. Phys. Lett., Vol.91, 133503, 2007) (Non-Patent Document 4), the resistance change layer and the electrode can be applied by applying a drive voltage or current. Oxidation-reduction reaction occurs at the interface, and a resistance change is caused by electrically detecting a high-resistance metal oxide generated at that time. By selecting a memory structure and a manufacturing method based on the above operation mechanism, a semiconductor memory that can operate stably can be realized.

  In order to achieve high integration in the ReRAM, as described in Japanese Patent Application Laid-Open No. 2003-197877 (Patent Document 3), efforts are made to stack and configure semiconductor memories. In order to further improve the degree of integration, a new structure in which a memory function part is provided on the side surface of a through hole has been proposed as disclosed in JP-A-2008-181978 (Patent Document 4). According to this structure, when forming the multi-layer stack structure described in Patent Document 2, it is possible to eliminate problems such as disconnection of wiring due to lack of flatness due to global steps caused when stacking each layer, and to realize the possibility of highly integrated memory. It is expected that it can be further improved.

  In addition, the multilayer stack type as shown in Patent Document 3 requires a technique for uniformly producing a variable resistance layer made of a metal oxide in which the amount of oxygen contained to determine the resistance value is accurately controlled. However, in the structure as shown in Patent Document 4 in which the memory function part is provided on the side surface of the through hole, the resistance change layer can be formed by a single deposition process, which is more effective in realizing an ultra-high integrated memory. It is considered to be the target.

However, according to the operation mechanism shown in Non-Patent Document 4, the resistance value in the high resistance state greatly depends on each memory bit even for the difference in the generation degree of the high resistance metal oxide caused by the oxidation-reduction reaction. Will be. In order to effectively reduce variations in memory bits whose resistance value is memory information, it is necessary to control the oxidation-reduction reaction. To control the oxidation-reduction reaction, it is better to control the amount of electrons and oxygen ions supplied to the interface between the resistance change layer and the electrode, and for this purpose, a current that restricts excessively excessive electrons from flowing locally. It is effective to provide a narrow path uniformly at the interface between the resistance change layer and the electrode. Several techniques have already been published for the advantage of providing a current confinement structure. According to the pamphlet of International Publication No. 2005/041303 (Patent Document 5), a structure in which concave protrusions are provided at the interface between the resistance change layer and the electrode, or a structure in which metal fine particles are arranged, Japanese Patent Application Laid-Open No. 2006-203178 (Patent Document 6). ) According to Japanese Patent Application Laid-Open No. 2007-180174 (Patent Document 7), a structure provided with ultrafine protrusions (nanochips), according to Japanese Patent Application Laid-Open No. 2007-180473 (Patent Document 7), and structure provided with protrusions on the electrode side. According to 8), a structure in which metal fine particles are used as crystal growth nuclei, and according to Japanese Patent Application Laid-Open No. 2006-210639 (Patent Document 9), fine particles are deposited on columnar conductors embedded in a dielectric using ferritin. Arranged structures and the like are disclosed respectively.
JP 2002-537627 A Japanese Patent No. 3919205 JP 2003-197877 A JP 2008-181978 A International Publication No. 2005/041303 Pamphlet JP 2006-203178 A JP 2007-180473 A JP 2007-180174 A JP 2006-210639 A TW Hickmott, J. Appl. Phys., Vol.88 pp.2805, 2000. IG Baek et al., Tech. Dig.- Int. Electron Devices Meet. 2004, 587. Z. Wei et al., Tech. Dig.- Int. Electron Devices Meet. 2008, 293. A. Odagawa et al., Appl. Phys. Lett., Vol.91, 133503, 2007.

  In order to realize a highly integrated semiconductor memory, a structure in which a memory function part is provided on the side surface of the through hole is promising, and the resistance change layer can be formed by a single deposition process, thereby minimizing process variations. be able to. In order to reduce the variation in the memory bit caused by the oxidation-reduction reaction, it is effective to uniformly provide a current constriction path at the interface between the resistance change layer and the electrode to restrict excessively excessive electrons from flowing locally. .

  However, Patent Documents 5-7 disclose current confinement structures, but not only a high-precision process technique is required, but it is quite difficult to produce a three-dimensional structure such as a side wall of a through hole. is there. Also, Patent Documents 8 to 9 disclose a structure using fine particles, but it is quite difficult to form a structure by arranging it on a three-dimensional structure such as a side wall of a through hole. SUMMARY OF THE INVENTION The present invention solves the above-described conventional problems, and an object thereof is to provide a manufacturing method for realizing an ultra-highly integrated memory using simple and easy processes.

  In order to solve the above problems, a method for manufacturing a semiconductor memory according to the present invention forms a multilayer structure including a conductive layer and an insulating layer for constituting at least two first electrode portions, and a part of the multilayer structure. A hole portion is formed so as to penetrate the first electrode portion, and ferritin containing a metal compound containing an element different from the first electrode portion as a main component with respect to the first electrode portion exposed on the side wall portion. A second electrode that is disposed on the first electrode part, and thereafter the ferritin protein is removed, and the metal compound encapsulated in ferritin is electrically connected to the first electrode part as metal nanoparticles. A variable resistance layer is provided thereon, a third electrode part is provided thereon, and the resistance change layer is driven between the second electrode part and the third electrode part in contact with the first electrode part. Resistance change by applying voltage or current To form a semiconductor memory. When arranging ferritin in the hole portion, it is preferable to include a step of introducing ferritin into the hole portion by setting the hole portion to a negative pressure from the semiconductor memory forming atmosphere. Further, it is preferable to form a strip-shaped wiring electrode electrically connected to the first electrode portion and further form a strip-shaped wiring electrode electrically connected to the third electrode portion. Further, it is preferable to form the bottom of the hole portion as a conductor. The first electrode portion is mainly composed of a conductive material containing at least titanium (Ti), the second electrode portion is mainly composed of a conductive material containing at least platinum (Pt) or gold (Au), and the insulating layer is at least silicon. It is preferable that the main component is an insulating material containing (Si).

  According to the present invention, an ultra-highly integrated semiconductor memory can be realized simply and easily.

  Hereinafter, embodiments of the present invention will be described. In addition, this invention is not limited to description of the following embodiment and an Example. In the following description, specific numerical values and specific materials may be exemplified, but other numerical values and other materials may be applied as long as the effect of the present invention is obtained.

  A part of the semiconductor memory according to the present invention is shown in FIG. FIG. 1 shows a cross-sectional view (b-b 'cross section shown in the top view of FIG. 3). On the conductor 10, the insulator 20, and the insulating layer 11, a resistance change type memory bit part 1 including a first electrode part 12, a second electrode part 13, a resistance change layer 14, and a third electrode part 15 is provided. Is three-dimensionally configured with the conductor 16 disposed on the top. The conductor 10 or the conductor 16 is configured to be connected to the bit line 32, the first electrode portion 12 is configured to be connected to the word line 33, and by applying a desired voltage or current to the resistance change layer 14, The resistance change of the memory bit unit 1 can be realized, and the semiconductor memory 100 can be realized by the manufacturing method of the present invention. 2A to 2H show an example of a method for manufacturing the semiconductor memory 100 shown in FIG. 2A to 2H show cross-sectional views.

In FIG. 2A, the conductor 10 is formed on a part of the insulator 20. The conductor 10 is preferably a strip-shaped wiring, but may be electrically connected to another strip-shaped wiring in a plug shape. The insulator 20 may be an insulator. For example, a SiO ₂ film using TEOS (Tetra ethyl orthosilicate) as a raw material, thermally oxidized Si (SiO ₂ ), SiOC, or other organic material having a low dielectric constant may be used. The conductor 10 basically has only to have conductivity with a resistivity of 100 mΩcm or less. For example, copper (Cu), aluminum (Al), platinum (Pt), tantalum (Ta), tungsten (W), tantalum nitride (Ta-N), titanium nitride (Ti-N), aluminum titanium nitride (Ti-Al) -N) or the like. In the example shown in FIG. 2A, the conductor 10 is formed in a shape embedded in a part of the insulator 20, and when Cu is used for the conductor 10, it is formed using a technique such as a Cu damascene process. . It is not necessary for Cu to be exposed on the surface of the conductor 10, and for example, a conductive coating such as Ta-N may be provided. For damascene process applications, hybrid dual damascenes that simultaneously form wiring and connection vias in low dielectric insulating laminated films with different properties, dual damascenes that simultaneously form wiring and connection vias in a single layer of low dielectric insulation film, Any method such as single damascene for performing damascene on each of wiring and connection vias may be used. In addition, a standard technique for the damascene process can be used for each elemental technique such as insulating film formation, groove processing, and metal filling. For example, a semiconductor substrate (for example, a silicon substrate) can be used as a base (not shown) on which the semiconductor memory according to the present invention is disposed. In the case of using a semiconductor substrate, the semiconductor memory according to the present invention and other semiconductor elements and circuits can be easily formed on the same substrate. Note that the structure shown in FIG. 2A may be formed over a semiconductor substrate, and further includes a substrate on which a transistor, a contact plug, and the like are formed in advance.

  Next, as shown in FIG. 2B, a multilayer film in which the insulating layer 11 and the first electrode portion 12 are stacked is formed on the structure of FIG. 2A.

  Next, as shown in FIG. 2C, a hole portion 21 having a depth until the conductor 10 is exposed is formed. A part of the insulating layer 11 and the first electrode part 12 is exposed in the formed hole part. Although not shown in the figure, the hole portion 21 shown in FIG. 2C may be formed after the multilayer film shown in FIG. 2B is processed into a wiring shape in advance. In the case where the conductor 10 is a strip-like wiring, it is preferable to provide the hole portion 21 near the intersection center between the conductor 10 and the multilayer film by forming a multilayer film wiring in a direction not parallel to the extending direction. . Standard lithography and etching techniques can be used for processing at this time. The insulating layer 11 at this time preferably contains an insulating material containing at least silicon (Si) as a main component. Moreover, it is preferable that the 1st electrode part 12 has as a main component a conductive material containing at least titanium (Ti).

Next, as shown in FIG. 2D, ferritin containing a metal compound containing as a main component an element different from the first electrode portion is disposed on the surface of the first electrode portion 12 exposed in the hole portion 21, and then ferritin is disposed. The protein is removed by, for example, UV light / ozone treatment, and a second electrode part is provided in which the metal compound encapsulated in ferritin is electrically connected to the first electrode part as metal nanoparticles. When metal sulfide is used as the encapsulated metal as a starting material, sulfur is removed from the metal sulfide simultaneously with protein removal by UV light / ozone treatment, and metal nanoparticles can be obtained. In some cases, for example, after performing UV light / ozone treatment, a reduction heat treatment (typically, in a gas atmosphere containing at least hydrogen (H ₂ ) in order to improve the conductivity of the first electrode portion and the second electrode portion. 100-600 ° C.).

  When introducing ferritin into the hole portion 21, the chip serving as a semiconductor memory is previously placed in an atmosphere of a negative pressure compared to the atmospheric pressure, and a solution containing ferritin is disposed on the upper portion of the hole portion and then placed under the atmospheric pressure. By doing so, it is possible to introduce into the deep part of the hole. Also, after placing a solution containing ferritin in the atmosphere under atmospheric pressure at the top of the hole part, it may be treated in a pressurized atmosphere. In the atmosphere where the hole part is under negative pressure than the atmosphere outside the hole. It is possible to introduce ferritin into the hall. The metal nanoparticles serving as the second electrode part preferably have a conductive material containing at least platinum (Pt) or gold (Au) as a main component. The formation of the metal compound encapsulated in ferritin will be described later. Further, when introducing ferritin into the hole portion 21, it is preferable to improve the selective arrangement on the surface of the first electrode portion 12 as compared with the surface of the insulating layer 11 by applying a surface treatment to the inside of the hole in advance. The process will be described later.

Next, as illustrated in FIG. 2E, the resistance change layer 14 is formed so as to be in contact with the side wall of the hole portion 21. The resistance change layer 14 is preferably composed of a metal oxide as a main component. Iron oxide (FeO _x ), titanium oxide (TiO _x ), tungsten oxide (WO _x ), tantalum oxide (TaO _x). ) And hafnium oxide (HfO _x ) as a main component. The metal oxide MO _x constituting the main component (M is a metal element and is selected from Fe, Ti, W, Ta, Hf, etc.) is preferably formed by oxidizing a metal base material. As a base material, an oxide (MO), a nitride (MN), a metal (M), or a mixture thereof may be contained as a main component. For example _FeO x0 as a base material of FeO _x with _{(x 0 = 4/3)} , preferred as _{FeO x (3/2 ≧ x} > 4/3) the resistance change layer 14 obtained by subsequent oxidation. Further, for example, by using the TiN as a base material of TiO _x, preferred _{TiO x N y (0.5 ≦ x} <2,0 <y <1) the resistance change layer 12 obtained by subsequent oxidation. Further, for example, using TaN as the base material of the TaO _x, preferably as _{TaO x N y (1 ≦ x} <2.5,0 <y <1) the resistance change layer 12 obtained by subsequent oxidation. Further, when TaO _x is directly formed on the side wall portion, if the aspect ratio (α = height / opening diameter) of the hole portion 21 is small (for example, α is 5 or less), a film forming method such as a magnetron sputtering method is used. When the aspect ratio of the hole portion 21 is large (for example, α is 1 or more), it is preferable to use a film forming method such as a CVD (chemical vapor deposition) method. For example, in the case of TaO _x , deposition under the condition of α ≧ 1000 is possible by the CVD method.

  Next, as shown in FIG. 2F, unnecessary resistance change layer adhering portions are removed by an etching technique. In this case, it is preferable to use a dry etching method with good directivity. Furthermore, a two-step process such as pre-planarizing the surface using a CMP method and then using an ion etching method at this time is effective in reducing the global step that is the unevenness of the entire chip. Is preferable.

  Next, as shown in FIG. 2G, the third electrode portion 15 is formed so as to fill the inside of the hole portion so as to be in contact with the resistance change layer 14.

  Finally, as shown in FIG. 2H, the conductor 16 is formed as a strip-like wiring connected from the third electrode portion 15. At this time, it is preferable to form it so as to run in parallel with the extending direction of the strip-like wiring made of the conductor 10. The third electrode portion 15 and the conductor 16 may basically have conductivity with a resistivity of 100 mΩcm or less. For example, copper (Cu), aluminum (Al), platinum (Pt), tantalum (Ta), tungsten (W), tantalum nitride (Ta-N), titanium nitride (Ti-N), aluminum titanium nitride (Ti-Al) -N), etc., and these may be formed into a film (for example, about 10 nm or less) and then filled with tungsten (W) or the like.

  1 and 2A to 2H, the via plug is connected from the conductor 16 because the conductor 10 is arranged in the lower portion so that it can be easily connected to a transistor or a wiring formed in advance below the conductor 10 layer. The connection alone has the advantage of simplifying the redundant wiring.

  Each of the steps shown in FIGS. 2A to 2H can be performed by applying a known technique, for example, a technique used in a semiconductor element manufacturing process, a thin film forming process, or a microfabrication process. The formation of each layer includes, for example, atomic layer deposition (ALD), pulse laser deposition (PLD), ion beam deposition (IBD), cluster ion beam, and RF, DC, electron cycloton resonance (ECR), helicon. Various sputtering methods such as inductively coupled plasma (ICP) and a counter target, molecular beam epitaxial method (MBE), ion plating method, and the like can be applied. In addition to the PVD (Physical Vapor Deposition) method, a CVD (Chemical Vapor Deposition) method, a MOCVD (Metalorganic Chemical Vapor Deposition) method, a plating method, a MOD (Metalorganic Decomposition) method, or a sol-gel method may be used. In particular, the CVD method is preferable because the variable resistance layer 12 can be easily formed on the side wall portion of the three-dimensional structure.

  For microfabrication of each layer, for example, a method used in a semiconductor element manufacturing process or a magnetic device (such as a magnetoresistive element such as GMR or TMR) can be applied. For example, physical or chemical etching methods such as ion milling, RIE (Reactive Ion Etching), and FIB (Focused Ion Beam) may be used. Further, a stepper for forming a fine pattern, a lithography technique using an EB (Electron Beam) method, or the like may be used in combination. The planarization of the interlayer insulating layer and the surface of the conductor deposited in the contact hole can be performed by, for example, CMP or cluster ion beam etching. In addition, the oxidation treatment at the time of manufacturing the electrode and the resistance change layer is performed in an appropriate atmosphere containing, for example, oxygen atoms, molecules, ions or radicals. The oxidation treatment may change the atmosphere, temperature, time, and reactivity. As means for generating plasma and radicals, for example, known means such as ECR discharge, glow discharge, RF discharge, helicon or ICP can be applied. Nitriding using nitrogen can be performed by the same method.

  3 is a top view of the semiconductor memory of FIG. 1 that can be formed by the manufacturing method shown in FIGS. 2A to 2H, and FIG. 4 is a cross-sectional view in the direction perpendicular to the paper surface of FIG. 1 (shown in the top view of FIG. 3). An example of the cross section of c-c 'is shown.

  FIG. 5 shows another example of the semiconductor memory according to the present invention. 2A to 2F, the third electrode part 15 is formed on the side wall inside the hole part so as to be in contact with the resistance change layer 14, and the conductor 16 This is realized by processing the wiring shape to be formed and depositing the insulator 17 thereon. At this time, after the third electrode portion 15 is formed on the side wall inside the hole portion, the insulator 17 may be immediately deposited and processed so as to have a desired shape as the wiring of the conductor 16.

  FIG. 6 shows an example of the memory bit unit 1 shown in the semiconductor memory of FIG. By providing the semiconductor 25 between the first electrode part 12 and the second electrode part 13, a nonlinear conduction part can be formed. 7 (diode operation + memory bit operation) as shown in FIG. 7 is ensured through the conduction path of the first electrode unit 12 / semiconductor 25 / second electrode unit 13 / resistance change layer 14 / third electrode unit 15. This is preferable in improving the selectivity between memory bits. The semiconductor 25 is preferably mainly composed of an oxide of titanium (Ti). As a manufacturing method, it can obtain by performing the oxidation process with respect to the 1st electrode part 12 surface exposed to the hole part 21, after passing through the same process as shown to FIG. 2A-FIG. 2C. Further, it can be obtained by oxidation treatment (including ozone treatment) and UV light treatment used when removing the protein by introducing ferritin into the hole portion in FIG. 2D.

  FIG. 8 shows an example of a semiconductor memory as shown in FIG. 1 and a semiconductor memory in which a large number of memory bits shown in FIGS. 6 and 7 are integrated. The conductor 10 can be arranged to function as the word line 32, and the first electrode unit 12 can be arranged to function as the bit line 33. For example, by applying a positive or negative voltage or current having a desired magnitude from the bit line 33 side to the word line 32 side, the semiconductor memory according to the present invention in which the resistance change appears in a nonvolatile manner can be realized. . In addition, each memory bit is formed with a diode-operated non-linear conducting portion, so that one bit line and one word line can be selected and written / read, thereby realizing a semiconductor memory having random accessibility. be able to.

Memory information of the semiconductor memory according to the present invention is represented by resistance change characteristics. The resistance change ratio is a numerical value serving as an index of the memory bit. Specifically, the resistance value in the high resistance state indicated by the memory bit is R _High and the resistance value in the low resistance state is R _Low . Sometimes it is the value obtained by the following equation.

[Resistance change ratio] = (R _High −R _Low ) / R _Low
A specific state indicating a specific electric resistance value is maintained until a predetermined voltage or current necessary for writing is applied to the memory bit portion again. The applied voltage or current is preferably pulsed. The shape of the pulse is not particularly limited, and may be, for example, at least one shape selected from a sine wave shape, a rectangular wave shape, and a triangular wave shape. The width of the pulse may usually be in the range of several nanoseconds to several milliseconds.

  Hereinafter, a method for changing the state of the element by applying a voltage will be described. For example, by applying two kinds of bias voltages (positive bias voltage) between the electrodes so that the potential of the word line 32 becomes positive with respect to the potential of the bit line 33, the low resistance state is changed to the high resistance state or It can be changed from a high resistance state to a low resistance state. For example, it is possible to change from a low resistance state to a high resistance state by applying a Reset pulse of voltage V1, and to change from a low resistance state to a high resistance state by applying a Set pulse of voltage V2 (> V1). Such an operation is called a unipolar operation, and Set / Reset is written by applying two types of pulses having the same polarity. Also, the operation with the polarity reversed can be performed in the same procedure by applying a negative bias. The drive with positive bias application or negative bias application may be selected according to the characteristics of the memory bit part. Further, for example, by applying a positive / negative bias voltage, the low resistance state can be changed to the high resistance state, or the high resistance state can be changed to the low resistance state. Such an operation is called a bipolar operation, and Set / Reset writing is performed by applying two types of pulses having different polarities. For example, it is possible to change from a low resistance state to a high resistance state by applying a reset pulse of a negative voltage V1, and to change from a low resistance state to a high resistance state by applying a set pulse of a positive voltage V2. In this case, there may be an operation in which the polarities of V1 and V2 are reversed.

  It is preferable to read the memory bit based on the difference between the resistance value (or output current value) and the resistance value (or reference output current value) of a specific reference bit. The reference resistance value of the reference bit is prepared separately from the memory bit, and is obtained by applying a read voltage to the reference bit in the same manner as the memory bit. An example of a circuit configuration for measuring by such a method is shown in FIG.

  In the method shown in FIG. 9, an output 93 obtained by amplifying the output 91 from the memory bit 300 by the negative feedback amplifying circuit 92a and an output 96 obtained by amplifying the output 95 from the reference bit 94 by the negative feedback amplifying circuit 92b are differentiated. Input to the amplifier circuit 97. Then, the resistance of the memory bit is obtained using the output signal 98 obtained from the differential amplifier circuit 97.

FIG. 10 shows an example of the operation of a single memory bit. Assume that the memory bit is initially in a low resistance state. When a pulsed positive bias voltage V ₁ is applied so that the potential of the conductor 10 becomes positive with respect to the potential of the first electrode portion 12, the state of the memory bit portion 1 changes from the low resistance state to the high resistance state. (Reset operation) Here, by applying a positive bias voltage having a magnitude of less than V ₁ to the memory bit unit 1, the electric resistance value is obtained from the current output. These voltages are referred to as a read voltage (Read voltage: V _RE ). The polarity of the V _RE is not may be positive or negative. The read voltage is preferably pulsed as shown in FIG. By using the pulsed read voltage, it is possible to reduce the power consumption and improve the switching efficiency in the operation of the memory bit (the same applies to the read voltage described below). Even if the read voltage is applied, the state of the memory bit unit 1 does not change, so even if the read voltage is applied a plurality of times, the same electric resistance value is detected (the same applies to the read voltage described below). Is).

Then, upon application of a set voltage V ₂ is a pulsed negative bias voltage is changed from the high resistance state to the low resistance state (set operation). Here, by applying the read voltage V _RE to the memory bit unit 1, the electric resistance value is obtained from the current output.

  In this manner, information can be recorded and read from the memory bit unit 1 by applying a pulsed voltage. The magnitude of the output current of the memory bit unit 1 at the time of reading varies depending on the state. Here, if the relatively small output current state (OUTPUT1 in FIG. 10) is “1” and the relatively large output current state (OUTPUT2 in FIG. 10) is “0”, the information “1” is set by the reset voltage. "Is recorded, and information" 0 "is recorded by the set voltage (information" 1 "is deleted).

  The magnitude of the read voltage is usually preferably in the range of about 1/2 to 1/1000 of the set voltage and the reset voltage. Although the specific values of the set voltage and the reset voltage depend on the configuration of the memory bit unit 1 and the semiconductor memory, they are usually in the range of 0.1V to 20V, and preferably in the range of 0.5V to 10V.

  FIG. 11 is a block diagram showing a configuration of a nonvolatile semiconductor memory according to the present invention. As shown in FIG. 11, a semiconductor memory 400 according to the present invention includes a memory main body 401 on a semiconductor substrate. The memory main body 401 includes a memory array 402, a row selection circuit / driver 403, A column selection circuit / driver 404, a write circuit 405 for writing information, a sense amplifier 406 that detects the amount of current flowing through the selected bit line and determines data “1” or “0”, and a terminal DQ And a data input / output circuit 407 for performing input / output processing of the input / output data. The semiconductor memory 400 further includes an address input circuit 408 that receives an address signal input from the outside, and a control circuit 409 that controls the operation of the memory body 401 based on a control signal input from the outside. Yes.

  As shown in FIG. 11, the memory array 402 includes a plurality of word lines WL0, WL1, WL2,... Formed in parallel with each other on a semiconductor substrate, and a plurality of word lines WL0, WL1, WL2,. A plurality of bit lines BL0, BL1, BL2,... Formed above and parallel to each other in a plane parallel to the main surface of the semiconductor substrate and three-dimensionally intersecting the plurality of word lines WL0, WL1, WL2,. And.

  Further, a semiconductor memory according to the present invention is provided which is provided in a matrix corresponding to the three-dimensional intersections between the plurality of word lines WL0, WL1, WL2,... And the plurality of bit lines BL0, BL1, BL2,. A plurality of memory bits M111, M112, M113, M121, M122, M123, M131, M132, M133,... (Hereinafter referred to as “memory cells M111, M112,...”) Are arranged.

  The address input circuit 408 receives an address signal from an external circuit (not shown), outputs a row address signal to the row selection circuit / driver 403 based on the address signal, and outputs a column address signal to the column selection circuit / driver 404. Output to. Here, the address signal is a signal indicating the address of a specific memory cell selected from among the plurality of memory cells M111, M112,. The row address signal is a signal indicating a row address among the addresses indicated by the address signal, and the column address signal is a signal indicating a column address among the addresses indicated by the address signal.

  In the information write cycle, the control circuit 409 outputs a write signal instructing application of a write voltage to the write circuit 405 in accordance with the input data Din input to the data input / output circuit 407. On the other hand, in the information read cycle, the control circuit 409 outputs a read signal instructing application of the read voltage to the column selection circuit / driver 404.

  The row selection circuit / driver 403 receives the row address signal output from the address input circuit 408, and selects any of the plurality of word lines WL0, WL1, WL2,. A predetermined voltage is applied to the selected word line.

  Further, the column selection circuit / driver 404 receives the column address signal output from the address input circuit 408, and selects one of the plurality of bit lines BL0, BL1, BL2,... According to the column address signal. Then, a write voltage or a read voltage is applied to the selected bit line.

  When the write circuit 405 receives the write signal output from the control circuit 409, the write circuit 405 outputs a signal for instructing the row selection circuit / driver 403 to apply a voltage to the selected word line, and the column selection circuit / A signal for instructing the driver 404 to apply a write voltage to the selected bit line is output.

  Further, the sense amplifier 406 detects the amount of current flowing through the selected bit line to be read in the information read cycle, and determines the data to be “1” or “0”. The output data DO obtained as a result is output to an external circuit via the data input / output circuit 407.

  According to the present invention, the memory array 402 shown in FIG. 11 can be realized as a three-dimensionally stacked memory array shown in FIG.

  Hereinafter, the present invention will be described in more detail with reference to examples.

Example 1
In Example 1, Sample 1-1 was manufactured using the method for manufacturing a semiconductor memory shown in FIGS. 2A to 2H, and its resistance change characteristic was evaluated.

First, an insulator 20 having a TEOS film (SiO ₂ film) formed on the surface was prepared. And the conductor 10 of the strip | belt-shaped wiring shape was produced on the insulator 20 using copper (Cu) as a main component. For the production, a standard copper damascene wiring formation method was used, and Ta / TaN was arranged on the bottom and side walls of the wiring. Furthermore, after forming the copper wiring part of the conductor 10, Ta / TaN was distribute | arranged to the upper part, and it was set as the conductor 10. FIG. A typical wiring width was 1 μm. Next, a TEOS film is formed as the insulating layer 11 and titanium nitride (TiN) is stacked as the first electrode portion 12 to form a multilayer film composed of ([insulating layer 11 / first electrode portion 12] _twice / insulating layer 11). did. The film thickness of the TEOS film was 500 nm, and the film thickness of the TiN layer was 50 nm. The TiN layer was deposited by magnetron sputtering using a Ti target. Sputtering is performed in an atmosphere (pressure: 0.1 Pa) of a mixed gas of nitrogen gas and argon gas (nitrogen gas: argon gas volume ratio is approximately 4: 1) in a range of 0 to 400 ° C. (mainly To 350 ° C.), and the applied power was set to DC 4 kW. The thickness of the TEOS film that is an insulating film formed on the first electrode portion 12 was 500 nm. The multilayer film portion in which the insulating layer 11 and the first electrode portion 12 were laminated was processed into a strip-like wiring shape using standard lithography and etching techniques. The wiring width was 5 μm. Next, a hole portion 21 having a depth until the conductor 10 is exposed is formed at the intersection of the multilayer film including the strip-shaped conductor 10 and the strip-processed first electrode portion 12. The size of the hole 21 was set to 0.4 μmφ. Thereafter, oxygen and ozone gas were supplied while irradiating UV light at a substrate temperature of 110 ° C. for 5 minutes using a UV light / ozone treatment apparatus to oxidize and hydrophilize the substrate surface. In this step, the exposed surface of the titanium nitride film inside the hole portion 21 was oxidized, and a titanium oxynitride layer was formed on the surface.

  Next, preparation of metal-encapsulated ferritin formed by introducing a gold sulfide core into the cavity inside apoferritin will be described. To form metal-encapsulated ferritin, first add 17 mL of thiourea to 1 mL of 20 mM potassium chloroaurate (KAuCl4) solution, and after a few minutes, a yellow solution of Au (III) ions becomes Au (I Since the thiourea complex turned colorless and transparent, this was used as a 20 mM gold thiourea complex solution. Next, the purified horse-derived apoferritin solution and the gold thiourea complex solution were mixed in a phosphate buffer (pH 8). Here, the phosphate buffer concentration of the final mixed solution was 50 mM, the thiourea concentration was 3 mM, and the equine-derived apoferritin concentration was 0.5 mg / mL. In order to complete the reaction of incorporating gold sulfide into apoferritin, the mixed solution was allowed to stand overnight. By this operation, gold sulfide was introduced into the apoferritin holding part, and gold sulfide ferritin (a complex of apoferritin and gold sulfide fine particles) was generated. Next, the mixed solution was put in a container and centrifuged using a centrifuge at 10,000 rpm for 15-30 minutes to remove precipitates. Subsequently, the supernatant after removing the precipitate was further centrifuged at 10,000 rpm for 30 minutes. At this time, soluble gold sulfide ferritin is dispersed in the supernatant, and the aggregated gold sulfide ferritin precipitates as an aggregate. The solvent of the supernatant of the ferritin solution containing the metal sulfide thus obtained was concentrated using an ultrafiltration membrane [Amicon Ultra-15 (NMWL: 50,000)], and this concentrated ferritin fraction was further added to 25%. Column chromatography was performed by running on Sephacryl S-300 (gel filtration column) equilibrated with 50 mmol / L Tris (2-Amino-2- (hydroxymethyl) -1,3-propanediol) buffer (pH 8) at ℃. Purified by performing. Thereby, the eluate from which the aggregate of the ferritin particle was removed by the gel filtration column was obtained. For the eluate, ferritin in the solution was further concentrated using an ultrafiltration membrane and an ultracentrifugation apparatus, and then 110 mM MES (2- (4-Morpholino) ethanesulfonic acid) and 110 mM Tris (2-Amino) were concentrated. The solution was diluted with a pH 7 buffer solution containing -2- (hydroxymethyl) -1,3-propanediol). This concentration and dilution operation was repeated 3 to 7 times, and finally a ferritin solution in which 0.2 mg / mL of ferritin as a protein concentration was dispersed in water could be obtained.

  A ferritin solution containing about 1% of a surfactant (TWEEN 20: a derivative consisting of mono-9-octadecanoate poly (oxy-1,2-ethanediyl)) prepared by purifying ferritin as described above is compared with atmospheric pressure. It was dripped at the upper part of the hole part 21 of the sample 1-1 placed under a negative pressure atmosphere, and then returned to atmospheric pressure and allowed to stand at room temperature for 30 minutes. By this operation, the ferritin solution is introduced into the hole portion, and ferritin is adsorbed on the side wall inside the hole portion. Sample 1-1 was washed with water and then baked at 110 ° C. for 3 minutes as a drying treatment, and the adsorbed ferritin was fixed on the first electrode portion 12. After that, it was placed in a UV light / ozone treatment apparatus, and oxygen and ozone gas were supplied for 5 minutes while irradiating UV light at a substrate temperature of 110 ° C., and the outer protein of ferritin was removed. At the same time, the gold sulfide core with a diameter of 6 nm inside ferritin was reduced, and gold nanoparticles with a diameter of 5 nm could be formed.

Next, Fe ₃ O ₄ was deposited by a magnetron sputtering method as a base material of the resistance change film. The deposition of the base material Fe ₃ O ₄ uses FeO _0.75 as a target, and the film forming temperature ranges from room temperature to 400 ° C. (mainly 300 ° C.) in a argon atmosphere at a pressure of 0.6 Pa by magnetron sputtering. The applied power was RF100W. The specific resistance of the Fe ₃ O ₄ layer prepared separately under these conditions is about 5-50 mΩcm (typically 10 mΩcm), and it is confirmed that it is an Fe ₃ O ₄ layer by X-ray diffraction, infrared absorption, Raman spectroscopy, and the like. Identified. Thereafter, a resistance change layer 14 was formed on the side wall of the hole portion 21 through heat treatment during oxidation (300 ° C. for 1 minute). The resistance change layer 14 can be made to be FeO _x (3/2 ≧ x> 4/3) by heat treatment under the same conditions for the solid film. The film thickness of Fe—O on the side wall portion that is the resistance change layer 14 was about 20 nm.

  Next, Pt / TaN / W was deposited as a conductive film for forming the third electrode portion 15. Pt was 10 nm, TaN was 20 nm, and W was deposited so as to fill the hole 21. On top of that, TaN was deposited to a thickness of 50 nm to form a conductor 16, and the conductor 16 was processed into a strip-like wiring shape. The wiring width was 5 μm.

  The produced Sample 1-1 exhibited a bias applicability as non-linear conduction as an initial characteristic. This is considered to be caused by the conduction of the metal / semiconductor / metal portion where titanium oxynitride that becomes the semiconductor 25 is formed between the first electrode portion 12 and the second electrode portion 13.

  Next, the pulsed voltage shown in FIG. 10 was applied to the produced sample 1-1, and the resistance change ratio was evaluated. The resistance change ratio was evaluated as follows. Using a pulse generator, a pulse voltage is applied between the first electrode portion 12 and the conductor 10 of the sample 1-1, and 2.5V is read as the reset voltage and -2.5V is read as the set voltage. A voltage of 0.05 V (positive bias voltage) was applied. The pulse width of each voltage was 10 ms (milliseconds). In each of the states after applying the set voltage and after applying the reset voltage, the electric resistance value of the element was calculated from the output current value when the read voltage was applied.

The resistance change ratio was calculated from the following formula, where the calculated value of the high resistance state of the electric resistance was R _High and the value of the low resistance state was R _High .

[Resistance change ratio] = (R _High −R _Low ) / R _Low
As a result, the two memory bit parts 1 formed by the two first electrode parts 12 included in the sample 1-1 each exhibited a resistance change ratio of 10 times or more.

  This example shows that the semiconductor memory according to the present invention exhibits good resistance change characteristics, and the manufacturing method of the present invention can be applied to a highly integrated memory capable of miniaturizing elements.

(Example 2)
In Example 2, a sample 2-1 was manufactured using the method for manufacturing a semiconductor memory shown in FIGS. 2A to 2H, and its resistance change characteristics were evaluated.

  In Sample 2-1, platinum nanoparticles formed using platinum sulfide ferritin were formed as the second electrode portion. Other portions were formed in the same manner as Sample 1-1 in Example 1. The introduction of ferritin into the hole 21 is the same as in Example 1.

  The operation for introducing the platinum sulfide core into apoferritin is described below.

  First, 0.85 mL of 100 mg / mL thiourea solution, 1 mL of 100 mM potassium platinum (II) chloride (K2 (PtCl4)) solution, and 0.15 mL of pure water were mixed, and this was mixed with 50 mM platinum thiourea complex solution. did. Next, the purified horse-derived apoferritin solution and the above platinum thiourea complex solution were mixed in a phosphate buffer (pH 8). Here, the phosphate buffer concentration of the final mixed solution was 50 mM, the thiourea concentration was 3 mM, and the equine-derived apoferritin concentration was 0.5 mg / mL. In order to complete the reaction of incorporating the platinum sulfide into apoferritin, the mixed solution was allowed to stand overnight. By this operation, platinum sulfide was introduced into the holding portion of apoferritin, and platinum sulfide ferritin (a complex of apoferritin and platinum sulfide fine particles) was generated. Next, the mixed solution was put in a container and centrifuged using a centrifuge at 10,000 rpm for 15-30 minutes to remove precipitates. Subsequently, the supernatant after removing the precipitate was further centrifuged at 10,000 rpm for 30 minutes. At this time, the dissolvable platinum sulfide ferritin is dispersed in the supernatant, and the aggregated platinum sulfide ferritin precipitates as an aggregate.

  The solvent of the supernatant of the ferritin solution containing platinum sulfide obtained as described above is concentrated using an ultrafiltration membrane [Amicon Ultra-15 (NMWL: 50,000)], and the concentrated ferritin fraction is further purified. Column chromatography by flowing through Sephacryl S-300 (gel filtration column) equilibrated with 50 mmol / L Tris (2-Amino-2- (hydroxymethyl) -1,3-propanediol) buffer (pH 8) at 25 ° C Was purified by performing Thereby, the eluate from which the aggregate of the ferritin particle was removed by the gel filtration column was obtained. For the eluate, ferritin in the solution is further concentrated using an ultrafiltration membrane and an ultracentrifugation device, and then 20 mM MES (2- (4-Morpholino) ethanesulfonic acid) and 6 mM Tris (2-Amino) are concentrated. Dilution was carried out with a pH 5.8 buffer solution containing -2- (hydroxymethyl) -1,3-propanediol). This concentration and dilution operation was repeated 3 to 7 times to finally obtain a ferritin solution in which 0.2 mg / mL ferritin as a protein concentration was dispersed in water.

  A ferritin solution containing about 1% of a surfactant (TWEEN 20: a derivative consisting of mono-9-octadecanoate poly (oxy-1,2-ethanediyl)) prepared by purifying ferritin as described above is compared with atmospheric pressure. It was dripped at the upper part of the hole part 21 of the sample 2-1 placed under a negative pressure atmosphere, and then returned to atmospheric pressure and allowed to stand at room temperature for 30 minutes. By this operation, the ferritin solution is introduced into the hole portion, and ferritin is adsorbed on the side wall inside the hole portion. Sample 2-1 was washed with water, and then baked at 110 ° C. for 3 minutes as a drying treatment, so that the adsorbed ferritin was fixed on the first electrode portion 12. After that, it was placed in a UV light / ozone treatment apparatus, and oxygen and ozone gas were supplied for 5 minutes while irradiating UV light at a substrate temperature of 110 ° C., and the outer protein of ferritin was removed. At the same time, a platinum sulfide core with a diameter of 6 nm inside ferritin was reduced, and platinum nanoparticles with a diameter of 5 nm could be formed.

  The pulsed voltage shown in FIG. 10 was applied to the produced sample 2-1, and the resistance change ratio was evaluated. The resistance change ratio was evaluated as follows. Using a pulse generator, a pulse voltage is applied between the first electrode portion 12 and the conductor 10 of the sample 2-1, and the reset voltage is 2.5V and the set voltage is -2.5V. A voltage of 0.05 V (positive bias voltage) was applied. The pulse width of each voltage was 10 ms (milliseconds). In each of the states after applying the set voltage and after applying the reset voltage, the electric resistance value of the element was calculated from the output current value when the read voltage was applied.

The resistance change ratio was calculated from the following formula, where the calculated value of the high resistance state of the electric resistance was R _High and the value of the low resistance state was R _High .

[Resistance change ratio] = (R _High −R _Low ) / R _Low
As a result, the two memory bit portions 1 formed by the two first electrode portions 12 included in the sample 2-1 each exhibited a resistance change ratio of 10 times or more.

  This example shows that the semiconductor memory according to the present invention exhibits good resistance change characteristics, and the manufacturing method of the present invention can be applied to a highly integrated memory capable of miniaturizing elements.

(Example 3)
Samples 3-1 to 3-4 were manufactured using the method for manufacturing the semiconductor memory shown in FIGS. 2A to 2H, and the resistance change characteristics were evaluated.

In Example 3, as a material of the resistance change layer 14,
Sample 3-1: Tantalum oxide Ta-O
Sample 3-2: Titanium oxide Ti-O
Sample 3-3: Tungsten oxide WO
Sample 3-4: Hafnium oxide Hf-O
Were formed using each.

  In Samples 3-1 to 3-4, platinum nanoparticles formed using platinum sulfide ferritin were formed as the second electrode portion. Other portions were formed in the same manner as Sample 1-1 in Example 1. The introduction of ferritin into the hole 21 is the same as in Example 1.

  When Ta-O was formed as the resistance change layer 14 in the sample 3-1, it was deposited by an RF magnetron sputtering method using a Ta target. Sputtering is performed in an atmosphere of a mixed gas of oxygen gas and argon gas (oxygen flow ratio is 0.1-10%) (pressure is 0.2-5 Pa), and the substrate temperature is in the range of 20 to 400 ° C. (mainly 300 ° C.), the applied power was 150 to 300 W, and Ta—O (20 nm) was deposited. By forming Ta—O on the solid film under the same conditions, a film having an oxygen content (O / (Ta + O)) of about 0.5 to 0.7 can be manufactured.

When Ti-O was formed as the resistance change layer 14 in the sample 3-2, it was deposited by a magnetron sputtering method using a Ti target. Sputtering is performed in an atmosphere of a mixed gas of oxygen gas and argon gas (oxygen flow ratio is 0.1-10%) (pressure is 0.2-5 Pa), and the substrate temperature is in the range of 20 to 400 ° C. (mainly and 300 ° C.), subjected to applied power as _RF150-300W, was deposited TiO x (0.5 ≦ x <2 ).

In forming the resistance change layer 14 in the sample 3-3, W—O was deposited by magnetron sputtering using a W target. Sputtering is performed in an atmosphere of a mixed gas of oxygen gas and argon gas (oxygen flow ratio is 0.1-10%) (pressure is 0.2-5 Pa), and the substrate temperature is in the range of 20 to 400 ° C. (mainly 300 [deg.] C.), the applied power was RF 150-300 W, and WO _x (0.5 ≦ x <3) was deposited.

When Hf-O was formed as the resistance change layer 14 in the sample 3-4, it was deposited by a magnetron sputtering method using an Hf target. Sputtering is performed in an atmosphere of a mixed gas of oxygen gas and argon gas (oxygen flow ratio is 0.1-10%) (pressure is 0.2-5 Pa), and the substrate temperature is in the range of 20 to 400 ° C. (mainly and 300 ° C.), subjected to applied power as _RF150-300W, was deposited HfO x (0.5 ≦ x <2 ).

  The pulse voltage shown in FIG. 10 was applied to the produced samples 3-1 to 3-4, and the resistance change ratio was evaluated. The resistance change ratio was evaluated as follows. Using a pulse generator, a pulse voltage is applied between the first electrode portion 12 and the conductor 10 of each sample, and 2.5V is set as a reset voltage, -2.5V is set as a set voltage, and a lead voltage is set. 0.05 V (positive bias voltage) was applied. The pulse width of each voltage was 10 ms (milliseconds). In each of the states after applying the set voltage and after applying the reset voltage, the electric resistance value of the element was calculated from the output current value when the read voltage was applied.

The resistance change ratio was calculated from the following formula, where the calculated value of the high resistance state of the electric resistance was R _High and the value of the low resistance state was R _High .

[Resistance change ratio] = (R _High −R _Low ) / R _Low
As a result, the two memory bit portions 1 formed by the two first electrode portions 12 included in each sample each exhibited a resistance change ratio of 10 times or more. The results are as shown in Table 1.

  This example shows that the semiconductor memory according to the present invention exhibits good resistance change characteristics, and the manufacturing method of the present invention can be applied to a highly integrated memory capable of miniaturizing elements.

Example 4
In the fourth embodiment, by using the method for manufacturing a semiconductor memory shown in FIGS. 2A to 2H, a memory of 2 bits per hole portion is arranged from a 64 × 2 = 128 bit memory in a matrix (8 × 8). Sample 4-1 was prepared and evaluated for its characteristics. As a result of confirming the individual operation of each element of the memory array, the operation as a random access type semiconductor memory was confirmed.

  As shown in each of the above embodiments, a semiconductor memory exhibiting good resistance change characteristics can be realized by using the method for manufacturing a semiconductor memory of the present invention, so that it can be applied to highly integrated memories that require element miniaturization. Is possible.

  The present invention can be applied to a semiconductor memory and an electronic device including the semiconductor memory. The semiconductor memory according to the present invention can be miniaturized and densified, and can be applied to various electronic devices. Examples of the electronic device using the semiconductor memory of the present invention include a non-volatile RAM, a switching element, a sensor, an image display device, a digital home appliance, a mobile phone, and a PC used for an information communication terminal.

Sectional drawing which shows typically an example of the semiconductor memory concerning this invention Process drawing which shows typically an example of the manufacturing method of the semiconductor memory of this invention The figure which shows the process following the process of FIG. 2A The figure which shows the process following the process of FIG. 2B The figure which shows the process following the process of FIG. 2C The figure which shows the process following the process of FIG. 2D The figure which shows the process following the process of FIG. 2E. The figure which shows the process following the process of FIG. 2F The figure which shows the process following the process of FIG. 2G. FIG. 1 is a top view schematically showing an example of the semiconductor memory of FIG. Sectional drawing which looked at the example of the semiconductor memory of FIG. 1 in another direction Sectional drawing which shows typically another example of the semiconductor memory concerning this invention Sectional drawing which shows typically the memory bit part of the semiconductor memory concerning this invention Schematic diagram using equivalent circuit of memory bit part of FIG. Schematic diagram showing an example of a semiconductor memory (memory array) according to the present invention. The figure for demonstrating an example of the reading method of the information in the semiconductor memory concerning this invention The figure for demonstrating an example of the recording and the reading method of the information in the semiconductor memory concerning this invention The figure which shows an example of the block diagram which shows the structure of the semiconductor memory of this invention

DESCRIPTION OF SYMBOLS 1 Memory bit part 10 Conductor 11 Insulating layer 12 1st electrode part 13 2nd electrode part 14 Resistance change layer 15 3rd electrode part 16 Conductor 17 Insulator 20 Insulator 21 Hole part 25 Semiconductor 32 Bit line 33 Word line 91 Output 92a Negative feedback amplifier circuit 92b Negative feedback amplifier circuit 93 Output 94 Reference bit 95 Output 96 Output 97 Differential amplifier circuit 98 Output signal 100 Semiconductor memory 200 Semiconductor memory 300 Memory bit 400 Semiconductor memory 401 Memory body 402 Memory array 403 Row selection Circuit / driver 404 Column selection circuit / driver 405 Write circuit 406 Sense amplifier 407 Data input / output circuit 408 Address input circuit 409 Control circuit BL0, BL1, ... Bit lines M111, M112, ... Memory cells WL0, WL1, ... Lead wire

Claims (9)

(1) forming a multilayer structure comprising a conductive layer and an insulating layer for constituting at least two first electrode portions;
(2) forming a hole part in a part of the multilayer structure so as to penetrate the first electrode part;
(3) The first electrode unit using ferritin containing a metal compound whose main component is different from the first electrode unit with respect to the first electrode unit exposed at least on the side wall of the hole unit. A second electrode portion disposed on the ferritin, wherein the metal compound encapsulated in the ferritin is electrically connected to the first electrode portion as metal nanoparticles. ,
(4) A variable resistance layer electrically connected to at least the second electrode part is provided on at least the side wall part of the hole part,
(5) forming a third electrode portion, which is disposed apart from the first electrode portion and the second electrode portion, electrically connected to the resistance change layer;
A plurality of different electric resistance values by applying a driving voltage or current through the resistance change layer between the second electrode portion and the third electrode portion electrically connected to the first electrode portion. A method of manufacturing a resistance change type semiconductor memory that can be changed between different states. The step (3) further includes the step of introducing the ferritin into the hole portion by placing the ferritin in the hole portion so that the hole portion has a negative pressure compared to a semiconductor memory forming atmosphere. The method of manufacturing a semiconductor memory according to claim 1. 2. The semiconductor memory according to claim 1, further comprising a step of forming a strip-shaped wiring electrode electrically connected to the first electrode portion in any of the steps (1) to (5). Manufacturing method. 4. The semiconductor memory according to claim 3, further comprising a step of forming a strip-shaped wiring electrode electrically connected to the third electrode portion in any of the steps (1) to (5). Manufacturing method. 2. The method of manufacturing a semiconductor memory according to claim 1, further comprising a step of forming the bottom of the hole portion as a conductor in any of the steps (1) to (5). The method of manufacturing a semiconductor memory according to claim 1, wherein the first electrode portion includes a conductive material containing at least titanium (Ti) as a main component. 3. The method of manufacturing a semiconductor memory according to claim 1-2, wherein the second electrode portion is mainly composed of a conductive material containing at least platinum (Pt) or gold (Au). 2. The method of manufacturing a semiconductor memory according to claim 1, wherein the insulating layer contains an insulating material containing at least silicon (Si) as a main component. The method of manufacturing a semiconductor memory according to claim 1, comprising a plurality of said semiconductor memories arranged in a matrix.

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