JP2008028248A - Resistance changing element, and resistance changing memory using the same - Google Patents

Resistance changing element, and resistance changing memory using the same Download PDF

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JP2008028248A
JP2008028248A JP2006201043A JP2006201043A JP2008028248A JP 2008028248 A JP2008028248 A JP 2008028248A JP 2006201043 A JP2006201043 A JP 2006201043A JP 2006201043 A JP2006201043 A JP 2006201043A JP 2008028248 A JP2008028248 A JP 2008028248A
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electrode
resistance change
current
resistance
bonding surface
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Mitsuo Sugiura
三津夫 杉浦
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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<P>PROBLEM TO BE SOLVED: To provide a resistance changing element which contains first and second electrodes and a resistance changing layer clamped by the respective electrodes, and in which two or more states exist that electric resistance values are different between the respective electrodes, and a drive voltage or current is applied to the resistance changing layer through the respective electrodes, whereby one state selected from the two or more states changes to the other state, making it possible to mitigate a concentration of a partial current on the resistance changing layer upon application of the drive voltage or current, and to suppress a deterioration of the resistance changing layer. <P>SOLUTION: There is provided this element in which a shape of a joint face is rectangular with a first electrode in the resistance changing layer. When seeing from a direction perpendicular to the joint face, an application face which applies the drive voltage or current to the electrode is provided in a portion which is not overlapped with the joint face in the first electrode, and the joint face has a long side in a direction substantially perpendicular to a direction of a current flowing in the first electrode from the application face to the joint face, upon application of the drive voltage or current. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、駆動電圧または駆動電流の印加により電気抵抗値が変化する抵抗変化素子と、これを用いた抵抗変化型メモリとに関する。   The present invention relates to a resistance change element whose electric resistance value changes when a drive voltage or drive current is applied, and a resistance change memory using the resistance change element.

メモリ素子は、情報化社会を支える重要な基幹電子部品として、幅広い分野に用いられている。近年、情報携帯端末の普及に伴い、メモリ素子の微細化の要求が高まっており、不揮発性メモリ素子においても例外ではない。しかし、素子の微細化がナノメーターの領域に及ぶにつれ、従来の電荷蓄積型のメモリ素子(代表的には、DRAM[Dynamic Random Access Memory]および強誘電体メモリ等)では、情報単位(ビット)あたりの電荷容量Cの低下が問題となりつつあり、この問題を回避するために様々な改善等がなされているものの、将来的な技術的限界が懸念されている。   Memory elements are used in a wide range of fields as important basic electronic components that support the information society. In recent years, with the widespread use of portable information terminals, there has been an increasing demand for miniaturization of memory elements, and nonvolatile memory elements are no exception. However, as device miniaturization reaches the nanometer range, conventional charge storage type memory devices (typically DRAM [Dynamic Random Access Memory] and ferroelectric memory, etc.) have information units (bits). The reduction of the perimeter charge capacity C is becoming a problem, and various improvements have been made to avoid this problem, but there are concerns about future technical limitations.

微細化の影響を受けにくいメモリ素子として、電荷容量Cではなく、電気抵抗値Rの変化により情報を記録する不揮発性メモリ素子(抵抗変化型メモリ素子)が注目されており、このような抵抗変化型メモリ素子として、駆動電圧または電流の印加により電気抵抗値が変化する抵抗変化素子の開発が進められている(例えば、特許文献1を参照)。
特開2003−68983号公報
As a memory element that is not easily affected by miniaturization, not a charge capacity C but a nonvolatile memory element (resistance change type memory element) that records information by a change in electric resistance value R has been attracting attention. As a type memory element, development of a resistance change element in which an electric resistance value is changed by application of a driving voltage or current is underway (see, for example, Patent Document 1).
Japanese Patent Laid-Open No. 2003-68983

電荷蓄積型のメモリ素子は、一般に、コンデンサ(DRAM)、強誘電体層(強誘電体メモリ)等からなる容量記憶層を上部電極および下部電極により狭持した多層構造を有する。このような多層構造を有する電荷蓄積型のメモリ素子では、情報の記録および読出のために上部電極と下部電極との間に電圧を印加した場合においても、両者の間に配置された容量記憶層を介して一方の電極から他方の電極へと電流が流れることはない。またこのとき、容量記憶層全体に均一に電圧が印加される。   A charge storage type memory element generally has a multilayer structure in which a capacitor storage layer composed of a capacitor (DRAM), a ferroelectric layer (ferroelectric memory), etc. is held between an upper electrode and a lower electrode. In the charge storage type memory element having such a multilayer structure, even when a voltage is applied between the upper electrode and the lower electrode for recording and reading of information, the capacity storage layer disposed between the two electrodes No current flows from one electrode to the other through the electrode. At this time, a voltage is uniformly applied to the entire capacity storage layer.

一方、抵抗変化素子は、電気抵抗値Rが異なる2以上の状態を有する抵抗変化層を上部電極および下部電極により狭持した多層構造を有する。上部電極と下部電極との間に駆動電圧または電流を印加することにより、抵抗変化層の電気抵抗値を変化させることができるが、このとき、抵抗変化層を介して一方の電極から他方の電極へと電流が流れる。ここで、抵抗変化層は導体または半導体であり、抵抗変化層および電極の形状ならびに両者の位置関係等により、当該電流の流れ方が大きく影響を受ける。   On the other hand, the resistance change element has a multilayer structure in which a resistance change layer having two or more states having different electric resistance values R is sandwiched between an upper electrode and a lower electrode. By applying a driving voltage or current between the upper electrode and the lower electrode, the electrical resistance value of the resistance change layer can be changed. At this time, from one electrode to the other electrode via the resistance change layer Current flows into the. Here, the resistance change layer is a conductor or a semiconductor, and the flow of the current is greatly influenced by the shape of the resistance change layer and the electrode, the positional relationship between the two, and the like.

素子の構成によっては、駆動電圧または電流の印加時に抵抗変化層の一部に電流が集中することがある。電流が集中した部分では、電流が集中していない部分に比べて早く電気抵抗値が変化するため、周囲よりも低抵抗となることがあり、この場合、さらなる電流の集中が生じて抵抗変化層が劣化することがある。   Depending on the configuration of the element, the current may concentrate on a part of the resistance change layer when the drive voltage or current is applied. In the portion where the current is concentrated, the electric resistance value changes faster than the portion where the current is not concentrated, so the resistance may be lower than that of the surroundings. May deteriorate.

そこで本発明は、駆動電圧または電流の印加時における抵抗変化層への部分的な電流の集中を緩和でき、使用時における抵抗変化層の劣化が抑制された耐久性に優れる抵抗変化素子を提供することを目的とする。   Therefore, the present invention provides a resistance change element that can alleviate partial current concentration on the resistance change layer when a drive voltage or current is applied, and has excellent durability in which deterioration of the resistance change layer during use is suppressed. For the purpose.

本発明の抵抗変化素子(第1の抵抗変化素子)は、第1の電極と、第2の電極と、前記第1および第2の電極に狭持された抵抗変化層とを含み、前記第1および第2の電極間の電気抵抗値が異なる2以上の状態が存在し、前記抵抗変化層に、前記第1および第2の電極を介して駆動電圧または駆動電流を印加することにより、前記2以上の状態から選ばれる1つの状態から他の状態へと変化する素子である。第1の抵抗変化素子では、前記抵抗変化層における前記第1の電極との接合面の形状が長方形である。また、前記接合面に垂直な方向から見たときに、前記第1の電極の前記接合面と重複しない部分に、前記第1の電極に前記駆動電圧または駆動電流を印加する印加面があり、かつ、前記接合面は、前記駆動電圧または駆動電流の印加時に前記印加面から前記接合面へと前記第1の電極を流れる電流の方向に実質的に垂直な方向に長辺を有する。   The variable resistance element (first variable resistance element) of the present invention includes a first electrode, a second electrode, and a variable resistance layer sandwiched between the first and second electrodes. There are two or more states having different electrical resistance values between the first and second electrodes, and by applying a driving voltage or a driving current to the resistance change layer via the first and second electrodes, An element that changes from one state selected from two or more states to another state. In the first variable resistance element, the shape of the joint surface with the first electrode in the variable resistance layer is a rectangle. Further, when viewed from a direction perpendicular to the bonding surface, there is an application surface that applies the driving voltage or driving current to the first electrode in a portion that does not overlap with the bonding surface of the first electrode, The bonding surface has a long side in a direction substantially perpendicular to a direction of a current flowing through the first electrode from the application surface to the bonding surface when the driving voltage or driving current is applied.

上記とは別の側面から見た本発明の抵抗変化素子(第2の抵抗変化素子)は、第1の電極と、第2の電極と、前記第1および第2の電極に狭持された抵抗変化層とを含み、前記第1および第2の電極間の電気抵抗値が異なる2以上の状態が存在し、前記抵抗変化層に、前記第1および第2の電極を介して駆動電圧または駆動電流を印加することにより、前記2以上の状態から選ばれる1つの状態から他の状態へと変化する素子である。第2の抵抗変化素子では、前記第1の電極に、当該電極に前記駆動電圧または駆動電流を印加する印加面があり、前記第2の電極における前記抵抗変化層との接合面の形状が長方形である。また、前記接合面に垂直な方向から見たときに、前記第1の電極の印加面と前記第2の電極の接合面とが重複せず、前記印加面と前記接合面との間に前記抵抗変化層があるとともに、前記接合面は、前記駆動電圧または駆動電流の印加時に前記印加面から前記接合面へと前記第1の電極および前記抵抗変化層を流れる、前記方向から見た電流の方向に対して、実質的に垂直な方向に長辺を有する。   The variable resistance element (second variable resistance element) of the present invention viewed from a different aspect from the above is sandwiched between the first electrode, the second electrode, and the first and second electrodes. A variable resistance layer, and there are two or more states having different electric resistance values between the first and second electrodes, and a drive voltage or a voltage is applied to the variable resistance layer via the first and second electrodes. It is an element that changes from one state selected from the two or more states to another state by applying a driving current. In the second resistance change element, the first electrode has an application surface for applying the drive voltage or drive current to the electrode, and the shape of the joint surface of the second electrode with the resistance change layer is rectangular. It is. Further, when viewed from a direction perpendicular to the bonding surface, the application surface of the first electrode and the bonding surface of the second electrode do not overlap, and the application surface and the bonding surface The junction surface has a resistance change layer, and the junction surface flows the first electrode and the resistance change layer from the application surface to the junction surface when the drive voltage or drive current is applied. It has a long side in a direction substantially perpendicular to the direction.

本発明の抵抗変化型メモリは、上記本発明の抵抗変化素子をメモリ素子として備える。   The resistance change type memory according to the present invention includes the resistance change element according to the present invention as a memory element.

本発明の抵抗変化素子では、電極と抵抗変化層との接合面の形状を規定するとともに、上記接合面の配置を、駆動電圧または電流の印加時に印加面と上記接合面との間を流れる電流に対して規定することにより、素子に駆動電圧または駆動電流を印加したときの抵抗変化層への部分的な電流の集中を緩和でき、使用時における抵抗変化層の劣化を抑制できる。   In the variable resistance element of the present invention, the shape of the bonding surface between the electrode and the variable resistance layer is defined, and the arrangement of the bonding surface is a current flowing between the application surface and the bonding surface when a driving voltage or current is applied. With respect to the above, it is possible to alleviate partial current concentration on the resistance change layer when a drive voltage or drive current is applied to the element, and to suppress deterioration of the resistance change layer during use.

以下、図面を参照しながら、本発明の実施の形態について説明する。以下の説明において、同一の部材に同一の符号を付して、重複する説明を省略することがある。   Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the same reference numerals may be given to the same members, and overlapping descriptions may be omitted.

図1、2に、第1の抵抗変化素子の一例を示す。図2は、図1に示す抵抗変化素子1を、上部電極13における抵抗変化層12との接合面15に垂直な方向(図1に示す矢印Aの方向)から見た平面図である。   1 and 2 show an example of the first variable resistance element. FIG. 2 is a plan view of the resistance change element 1 shown in FIG. 1 as seen from a direction perpendicular to the bonding surface 15 of the upper electrode 13 with the resistance change layer 12 (direction of arrow A shown in FIG. 1).

図1に示す素子1は、基板10と、下部電極(第2の電極)11および上部電極(第1の電極)13からなる一対の電極と、下部電極11および上部電極13により狭持された抵抗変化層12とを有する。下部電極11、抵抗変化層12および上部電極13は、多層構造体(積層体)14として、互いに接するように、上記順に基板10上に配置されている。   The element 1 shown in FIG. 1 is sandwiched between a substrate 10, a pair of electrodes including a lower electrode (second electrode) 11 and an upper electrode (first electrode) 13, and the lower electrode 11 and the upper electrode 13. And a resistance change layer 12. The lower electrode 11, the resistance change layer 12, and the upper electrode 13 are arranged on the substrate 10 in the above order so as to be in contact with each other as a multilayer structure (laminated body) 14.

素子1には、下部電極11と上部電極13との間の電気抵抗値が異なる2以上の状態が存在する。駆動電圧または電流を素子1に、具体的には下部電極11と上部電極13との間に印加することにより、素子1は、上記2以上の状態から選ばれる1つの状態から他の状態へと変化する。素子1に電気抵抗値が異なる2つの状態(相対的に高抵抗の状態を状態Aとし、相対的に低抵抗の状態を状態Bとする)が存在する場合、駆動電圧または電流の印加により、素子1は、状態Aから状態Bへ、あるいは、状態Bから状態Aへと変化する。   In the element 1, there are two or more states in which the electric resistance value between the lower electrode 11 and the upper electrode 13 is different. By applying a driving voltage or current to the element 1, specifically, between the lower electrode 11 and the upper electrode 13, the element 1 changes from one state selected from the two or more states to another state. Change. When the element 1 has two states having different electrical resistance values (a state having a relatively high resistance is a state A and a state having a relatively low resistance is a state B), by applying a driving voltage or a current, Element 1 changes from state A to state B or from state B to state A.

素子1では、図2に示すように、上部電極13における接合面15と重複しない部分に、上部電極13に駆動電圧または電流を印加する印加面16がある。印加面16には、通常、上部電極13に駆動電圧または電流を供給する部材51(例えば、コンタクトプラグ等)が接続される(図1、2参照)。   In the element 1, as shown in FIG. 2, there is an application surface 16 for applying a driving voltage or current to the upper electrode 13 in a portion that does not overlap with the bonding surface 15 in the upper electrode 13. A member 51 (for example, a contact plug) that supplies a driving voltage or current to the upper electrode 13 is normally connected to the application surface 16 (see FIGS. 1 and 2).

抵抗変化素子をメモリデバイス等の電子デバイスに組み込む際に、ビット線、ワード線等の配線の取り回しから、上部電極における接合面と重複しない部分に印加面が設けられることは十分に考えられる。そして、印加面と接合面とがこのように配置された素子では、下部電極に対して上部電極の電位が正である駆動電圧(正バイアス電圧)または駆動電流(正バイアス電流)を印加した場合、上部電極を流れる電流が接合面の片側(例えば、図2における接合面15の左側)に集中する、即ち、抵抗変化層の一部に電流が集中することになる。   When the variable resistance element is incorporated in an electronic device such as a memory device, it is sufficiently conceivable that an application surface is provided in a portion that does not overlap with the bonding surface in the upper electrode from the wiring of the bit line, the word line, and the like. In the element in which the application surface and the bonding surface are arranged in this way, when a driving voltage (positive bias voltage) or a driving current (positive bias current) in which the potential of the upper electrode is positive with respect to the lower electrode is applied. The current flowing through the upper electrode is concentrated on one side of the bonding surface (for example, the left side of the bonding surface 15 in FIG. 2), that is, the current is concentrated on a part of the resistance change layer.

本発明の素子1では、図2に示すように、上部電極13における抵抗変化層12との接合面15の形状(接合面15に垂直な方向から見た形状)を長方形とするとともに、接合面15の長辺を、素子1に駆動電圧または電流を印加した際に印加面16から接合面15へと上部電極13を流れる電流17の方向に実質的に垂直な方向とする。素子1では、駆動電圧または電流の印加時における抵抗変化層12への部分的な電流の集中を緩和でき、使用時における抵抗変化層12の劣化を抑制できる。   In the element 1 of the present invention, as shown in FIG. 2, the shape of the bonding surface 15 (the shape viewed from the direction perpendicular to the bonding surface 15) of the upper electrode 13 with the resistance change layer 12 is rectangular, and the bonding surface The long side of 15 is set to a direction substantially perpendicular to the direction of the current 17 flowing through the upper electrode 13 from the application surface 16 to the bonding surface 15 when a driving voltage or current is applied to the element 1. In the element 1, partial concentration of current on the resistance change layer 12 when a drive voltage or current is applied can be alleviated, and deterioration of the resistance change layer 12 during use can be suppressed.

本明細書における「実質的に垂直」とは、角度にして90°を中心に、本発明の効果が得られる範囲で多少の幅を許容する趣旨であり、例えば、抵抗変化素子として一般的な設計上の許容範囲、あるいは、素子製造時における製造方法上の誤差範囲を反映した値である、90°±10°程度の角度であればよい。   The term “substantially vertical” in the present specification means that a slight width is allowed within a range where the effect of the present invention can be obtained around 90 ° as an angle. The angle may be an angle of about 90 ° ± 10 °, which is a value reflecting an allowable range in design or an error range in the manufacturing method at the time of manufacturing the element.

上部電極13を流れる電流17の方向は、素子1を接合面15に垂直な方向から見たときに、上部電極13における印加面16と接合面15とを最短距離で結ぶ線分の方向とすればよい。   The direction of the current 17 flowing through the upper electrode 13 is the direction of a line segment connecting the application surface 16 and the bonding surface 15 of the upper electrode 13 with the shortest distance when the element 1 is viewed from a direction perpendicular to the bonding surface 15. That's fine.

素子1における抵抗変化層12への部分的な電流の集中を緩和する効果は、下部電極11に対して上部電極13の電位が負である駆動電圧(負バイアス電圧)または駆動電流(負バイアス電流)を印加した場合にも上記と同様に得ることができる。   The effect of alleviating partial current concentration on the resistance change layer 12 in the element 1 is that a driving voltage (negative bias voltage) or a driving current (negative bias current) in which the potential of the upper electrode 13 is negative with respect to the lower electrode 11. ) Can also be obtained in the same manner as described above.

図1、2に示す素子1では、接合面15に垂直な方向から見た上部電極13の形状は長方形であるが、接合面15および印加面16が上述した規定を満たす限り当該形状は特に限定されず、例えば正方形であってもよい。   In the element 1 shown in FIGS. 1 and 2, the shape of the upper electrode 13 viewed from the direction perpendicular to the bonding surface 15 is rectangular, but the shape is particularly limited as long as the bonding surface 15 and the application surface 16 satisfy the above-described regulations. For example, it may be a square.

図1、2に示す素子1では、上部電極13における抵抗変化層12との接合面15の形状および配置等が規定されているが、素子1がこのような規定を有するかどうかに依らず、下部電極11における抵抗変化層12との接合面(接合面A)の形状および配置が、接合面15と同様に規定されていてもよい。即ち、下部電極11(第2の電極)における抵抗変化層12との接合面Aの形状が、接合面Aに垂直な方向から見て長方形であり、当該方向から見たときに、下部電極11における接合面Aと重複しない部分に、下部電極11に駆動電圧または電流を印加する印加面(印加面A)があり、かつ、接合面Aは、駆動電圧または電流の印加時に印加面Aから接合面Aへと下部電極11を流れる電流の方向に実質的に垂直な方向に長辺を有していてもよい。このような素子においても、素子1と同様の効果を得ることができる。   In the element 1 shown in FIGS. 1 and 2, the shape and arrangement of the bonding surface 15 of the upper electrode 13 with the resistance change layer 12 are defined. Regardless of whether the element 1 has such a definition, The shape and arrangement of the joint surface (joint surface A) with the resistance change layer 12 in the lower electrode 11 may be defined similarly to the joint surface 15. That is, the shape of the bonding surface A with the resistance change layer 12 in the lower electrode 11 (second electrode) is a rectangle when viewed from the direction perpendicular to the bonding surface A, and when viewed from the direction, the lower electrode 11 There is an application surface (application surface A) for applying a driving voltage or current to the lower electrode 11 in a portion that does not overlap with the bonding surface A, and the bonding surface A is joined from the application surface A when the driving voltage or current is applied. You may have a long side in the direction substantially perpendicular | vertical to the direction of the electric current which flows into the surface A through the lower electrode 11. FIG. Even in such an element, the same effect as the element 1 can be obtained.

上部電極13における抵抗変化層12との接合面15、および、下部電極11における抵抗変化層12との接合面Aの双方の形状および配置が、各々上述した規定を満たすことが好ましい。   It is preferable that the shape and the arrangement of both the bonding surface 15 of the upper electrode 13 with the resistance change layer 12 and the bonding surface A of the lower electrode 11 with the resistance change layer 12 satisfy the above-mentioned regulations.

駆動電圧または電流の印加時における抵抗変化層12への部分的な電流の集中を緩和する効果は、図3に示す素子1においてより顕著となる。   The effect of relieving partial current concentration on the resistance change layer 12 when a drive voltage or current is applied becomes more prominent in the element 1 shown in FIG.

図3は、第1の抵抗変化素子の別の一例を、上部電極13における抵抗変化層12との接合面15に垂直な方向から見た平面図である。図3に示す素子1は、基本的に図1、2に示す素子1と同様の構成を有するが、さらに、接合面15に垂直な方向から見た上部電極13の形状が長方形であり、上部電極13をその短辺に平行な分割線18で2つに等分割したときに、等分割した一方の部分19に接合面15があり(抵抗変化層12が接合しており)、他方の部分20に印加面16がある。   FIG. 3 is a plan view of another example of the first variable resistance element as viewed from a direction perpendicular to the bonding surface 15 of the upper electrode 13 with the variable resistance layer 12. The element 1 shown in FIG. 3 basically has the same configuration as the element 1 shown in FIGS. 1 and 2, but the shape of the upper electrode 13 viewed from the direction perpendicular to the bonding surface 15 is rectangular, When the electrode 13 is equally divided into two by a dividing line 18 parallel to the short side thereof, the equally divided portion 19 has the bonding surface 15 (the resistance change layer 12 is bonded), and the other portion. There is an application surface 16 at 20.

図3に示す素子1では、長方形の上部電極13における長辺方向の一端に接合面15があり、他端に印加面16がある、ともいえる。   In the element 1 shown in FIG. 3, it can be said that the rectangular upper electrode 13 has the bonding surface 15 at one end in the long side direction and the application surface 16 at the other end.

図1〜3に示す素子1において、接合面15の短辺と長辺との比(縦横比)は、例えば、短辺:長辺=1:1.5〜1:5である。   In the element 1 shown in FIGS. 1 to 3, the ratio (aspect ratio) of the short side to the long side of the bonding surface 15 is, for example, short side: long side = 1: 1.5 to 1: 5.

基板10は、例えば、シリコン(Si)基板であればよく、この場合、基板10における下部電極11に接する表面が酸化されていてもよい(基板10の表面に酸化膜が形成されていてもよい)。基板10がSi基板である場合、本発明の抵抗変化素子と半導体素子との組み合わせが容易となる。なお、トランジスタやコンタクトプラグ(以下、単に「プラグ」ともいう)等を形成した加工済みの基体も、基板に含めることができる。   The substrate 10 may be, for example, a silicon (Si) substrate. In this case, the surface of the substrate 10 in contact with the lower electrode 11 may be oxidized (an oxide film may be formed on the surface of the substrate 10). ). When the substrate 10 is a Si substrate, the combination of the variable resistance element and the semiconductor element of the present invention becomes easy. Note that a processed substrate on which a transistor, a contact plug (hereinafter also simply referred to as “plug”), or the like is formed can be included in the substrate.

下部電極11および上部電極13は基本的に導電性を有していればよく、例えば、Au(金)、Pt(白金)、Ru(ルテニウム)、Ir(イリジウム)、Ti(チタン)、Al(アルミニウム)、Cu(銅)、Ta(タンタル)、Fe(鉄)、Rh(ロジウム)、イリジウム−タンタル合金(Ir−Ta)、スズ添加インジウム酸化物(ITO)等、あるいは、これらの合金、酸化物、窒化物、弗化物、炭化物、硼化物等からなればよい。   The lower electrode 11 and the upper electrode 13 are basically required to have conductivity. For example, Au (gold), Pt (platinum), Ru (ruthenium), Ir (iridium), Ti (titanium), Al ( Aluminum), Cu (copper), Ta (tantalum), Fe (iron), Rh (rhodium), iridium-tantalum alloy (Ir-Ta), tin-added indium oxide (ITO), etc., or alloys thereof, oxidation It may be made of a material, nitride, fluoride, carbide, boride or the like.

抵抗変化層12は、抵抗変化素子として一般的な構成であればよく、例えば、抵抗変化材料として、(Pr,Ca)MnOz等のペロブスカイト化合物、あるいは、Fe23、Fe34、NiO等の遷移金属酸化物を含む抵抗変化層12であればよい。 The resistance change layer 12 may have a general configuration as a resistance change element. For example, as a resistance change material, a perovskite compound such as (Pr, Ca) MnO z , Fe 2 O 3 , Fe 3 O 4 , Any variable resistance layer 12 including a transition metal oxide such as NiO may be used.

上部電極13の印加面16に接続される、当該電極に駆動電圧または電流を供給する部材51は特に限定されず、例えば、コンタクトプラグであればよい。部材51は、基本的に導電性を有していればよい。   The member 51 connected to the application surface 16 of the upper electrode 13 and supplying a driving voltage or current to the electrode is not particularly limited, and may be a contact plug, for example. The member 51 should just have electroconductivity fundamentally.

図4、5に第2の抵抗変化素子の一例を示す。図5は、図4に示す抵抗変化素子21を、下部電極11における抵抗変化層12との接合面22に垂直な方向(図4に示す矢印Bの方向)から見た平面図である。   4 and 5 show an example of the second variable resistance element. FIG. 5 is a plan view of the resistance change element 21 shown in FIG. 4 as seen from the direction (direction of arrow B shown in FIG. 4) perpendicular to the bonding surface 22 of the lower electrode 11 with the resistance change layer 12.

図4に示す素子21は、基板10と、下部電極11(第2の電極)および上部電極13(第1の電極)からなる一対の電極と、下部電極11および上部電極13により狭持された抵抗変化層12とを有する。下部電極11、抵抗変化層12および上部電極13は、多層構造体(積層体)14として、互いに接するように、上記順に基板10上に配置されている。   The element 21 shown in FIG. 4 is sandwiched between the substrate 10, a pair of electrodes including a lower electrode 11 (second electrode) and an upper electrode 13 (first electrode), and the lower electrode 11 and the upper electrode 13. And a resistance change layer 12. The lower electrode 11, the resistance change layer 12, and the upper electrode 13 are arranged on the substrate 10 in the above order so as to be in contact with each other as a multilayer structure (laminated body) 14.

素子21には、下部電極11と上部電極13との間の電気抵抗値が異なる2以上の状態が存在する。駆動電圧または電流を素子1に、具体的には下部電極11と上部電極13との間に印加することにより、素子1は、上記2以上の状態から選ばれる1つの状態から他の状態へと変化する。素子1に電気抵抗値が異なる上記状態A、Bが存在する場合、駆動電圧または電流の印加により、素子1は、状態Aから状態Bへ、あるいは、状態Bから状態Aへと変化する。   In the element 21, there are two or more states in which the electric resistance value between the lower electrode 11 and the upper electrode 13 is different. By applying a driving voltage or current to the element 1, specifically, between the lower electrode 11 and the upper electrode 13, the element 1 changes from one state selected from the two or more states to another state. Change. When the states A and B having different electric resistance values exist in the element 1, the element 1 changes from the state A to the state B or from the state B to the state A by applying a driving voltage or current.

図4に示すように、素子21では、上部電極13に、当該電極に駆動電圧または電流を印加する印加面16がある。印加面16には、通常、上部電極13に駆動電圧または電流を供給する部材51が接続される。素子21では、また、下部電極11における抵抗変化層12との接合面22に垂直な方向から見たときに、印加面16と接合面22とが重複せず、かつ、印加面16と接合面22との間に抵抗変化層12がある(図5参照)。   As shown in FIG. 4, in the element 21, the upper electrode 13 has an application surface 16 that applies a driving voltage or current to the electrode. A member 51 for supplying a driving voltage or current to the upper electrode 13 is normally connected to the application surface 16. In the element 21, the application surface 16 and the bonding surface 22 do not overlap when viewed from a direction perpendicular to the bonding surface 22 of the lower electrode 11 with the resistance change layer 12, and the application surface 16 and the bonding surface are not overlapped. There is a resistance change layer 12 between them (see FIG. 5).

抵抗変化素子をメモリデバイス等の電子デバイスに組み込む際に、印加面、接合面ならびに素子を構成する各層がこのような配置となることは十分に考えられ、このような素子では、正バイアス電圧または正バイアス電流を印加した場合、上部電極における印加面から下部電極における接合面へと抵抗変化層を流れる電流が接合面の片側(例えば、図5における接合面22の左側)に集中する、即ち、抵抗変化層の一部に電流が集中することになる。   When the resistance change element is incorporated in an electronic device such as a memory device, it is fully possible that the application surface, the joint surface, and the layers constituting the element have such an arrangement. In such an element, a positive bias voltage or When a positive bias current is applied, the current flowing through the resistance change layer from the application surface of the upper electrode to the bonding surface of the lower electrode is concentrated on one side of the bonding surface (for example, the left side of the bonding surface 22 in FIG. 5). Current concentrates on a part of the resistance change layer.

本発明の素子21では、図5に示すように、下部電極11における抵抗変化層12との接合面22の形状(接合面22に垂直な方向から見た形状)を長方形とするとともに、接合面22の長辺を、素子1に駆動電圧または電流を印加した際に印加面16から接合面22へと上部電極13および抵抗変化層12を流れる、接合面22に垂直な方向から見た電流23の方向に実質的に垂直な方向とする。素子21では、駆動電圧または電流の印加時における抵抗変化層12への部分的な電流の集中を緩和でき、使用時における抵抗変化層3の劣化を抑制できる。   In the element 21 of the present invention, as shown in FIG. 5, the shape of the bonding surface 22 (the shape seen from the direction perpendicular to the bonding surface 22) of the lower electrode 11 and the resistance change layer 12 is rectangular, and the bonding surface When the driving voltage or current is applied to the element 1, the long side 22 flows through the upper electrode 13 and the resistance change layer 12 from the application surface 16 to the bonding surface 22, and the current 23 viewed from the direction perpendicular to the bonding surface 22. The direction is substantially perpendicular to the direction. In the element 21, partial concentration of current on the resistance change layer 12 when a drive voltage or current is applied can be alleviated, and deterioration of the resistance change layer 3 during use can be suppressed.

上部電極13および抵抗変化層12を流れる電流23の方向は、素子1を接合面22に垂直な方向から見たときに、上部電極における印加面16と下部電極における接合面22とを最短距離で結ぶ線分の方向とすればよい。   The direction of the current 23 flowing through the upper electrode 13 and the resistance change layer 12 is such that when the element 1 is viewed from the direction perpendicular to the bonding surface 22, the application surface 16 of the upper electrode and the bonding surface 22 of the lower electrode are at the shortest distance. The direction of connecting line segments may be used.

素子21における抵抗変化層12への部分的な電流の集中を緩和する効果は、負バイアス電圧または負バイアス電流を素子21に印加した場合にも上記と同様に得ることができる。   The effect of relieving partial current concentration on the resistance change layer 12 in the element 21 can be obtained in the same manner as described above even when a negative bias voltage or a negative bias current is applied to the element 21.

図4、5に示す素子21では、接合面22に垂直な方向から見た上部電極13および抵抗変化層12の形状は長方形であるが、上述した規定を満たす限り当該形状は特に限定されず、例えば正方形であってもよい。また、当該方向から見た下部電極11の形状は、接合面22が上述した規定を満たす限り、特に限定されない。   In the element 21 shown in FIGS. 4 and 5, the shapes of the upper electrode 13 and the resistance change layer 12 viewed from the direction perpendicular to the bonding surface 22 are rectangular. However, the shapes are not particularly limited as long as the above-described regulations are satisfied. For example, it may be a square. Further, the shape of the lower electrode 11 viewed from the direction is not particularly limited as long as the bonding surface 22 satisfies the above-described regulations.

また素子21では、接合面22に垂直な方向から見た上部電極13および抵抗変化層12の形状が等しいが、上述した規定を満たす限り、両者の形状は必ずしも等しくなくてもよい(実施例の図7を参照)。   In the element 21, the shapes of the upper electrode 13 and the resistance change layer 12 as viewed from the direction perpendicular to the bonding surface 22 are the same. (See FIG. 7).

図4、5に示す素子21では、下部電極11における抵抗変化層12との接合面22の形状および配置等が規定されているが、素子21がこのような規定を有するかどうかに依らず、上部電極13における抵抗変化層12との接合面(接合面B)の形状および配置が、接合面22と同様に規定されていてもよい。即ち、下部電極11(第2の電極)に、当該電極に駆動電圧または電流を印加する印加面(印加面B)があり、上部電極13(第1の電極)における抵抗変化層12との接合面Bの形状が、接合面Bに垂直な方向から見て長方形であり、当該方向から見たときに、印加面Bと接合面Bとが重複せず、印加面Bと接合面Bとの間に抵抗変化層12があり、かつ、接合面Bは、駆動電圧または電流の印加時に印加面Bから接合面Bへと下部電極11および抵抗変化層12を流れる、当該方向から見た電流の方向に実質的に垂直な方向に長辺を有していてもよい。このような素子においても、素子21と同様の効果を得ることができる。   4 and 5, the shape and arrangement of the bonding surface 22 of the lower electrode 11 with the resistance change layer 12 are defined. Regardless of whether the element 21 has such a definition, The shape and arrangement of the joint surface (joint surface B) with the resistance change layer 12 in the upper electrode 13 may be defined similarly to the joint surface 22. That is, the lower electrode 11 (second electrode) has an application surface (application surface B) for applying a driving voltage or current to the electrode, and the upper electrode 13 (first electrode) is joined to the resistance change layer 12. The shape of the surface B is a rectangle when viewed from the direction perpendicular to the bonding surface B. When viewed from the direction, the application surface B and the bonding surface B do not overlap, and the application surface B and the bonding surface B are not overlapped. There is a resistance change layer 12 between them, and the junction surface B flows through the lower electrode 11 and the resistance change layer 12 from the application surface B to the junction surface B when a driving voltage or current is applied. You may have a long side in the direction substantially perpendicular | vertical to a direction. Even in such an element, the same effect as the element 21 can be obtained.

下部電極11における抵抗変化層12との接合面22、および、上部電極13における抵抗変化層12との接合面Bの双方の形状および配置が、各々上述した規定を満たすことが好ましい。   It is preferable that both the shape and the arrangement of the joint surface 22 of the lower electrode 11 with the resistance change layer 12 and the joint surface B of the upper electrode 13 with the resistance change layer 12 satisfy the above-mentioned regulations.

図4、5に示す素子21において、接合面22の短辺と長辺との比は、例えば、短辺:長辺=1:1.5〜1:5である。   4 and 5, the ratio of the short side to the long side of the bonding surface 22 is, for example, short side: long side = 1: 1.5 to 1: 5.

駆動電圧または電流は、下部電極11および上部電極13を介して、素子1、21に印加すればよい。駆動電圧または電流の印加により、素子1、21における上記状態が変化する(例えば、状態Aから状態Bへ)が、変化後の状態(例えば、状態B)は、素子1、21に駆動電圧または電流が再び印加されるまで保持され、上記電圧または電流の印加により、再び変化する(例えば、状態Bから状態Aへ)。   A driving voltage or current may be applied to the elements 1 and 21 via the lower electrode 11 and the upper electrode 13. When the driving voltage or current is applied, the above-described state in the elements 1 and 21 changes (for example, from the state A to the state B). It is held until the current is applied again, and changes again by applying the voltage or current (for example, from state B to state A).

素子1、21に印加される駆動電圧または電流は、素子1が状態Aにあるときと、状態Bにあるときとの間で必ずしも同一でなくてもよく、その大きさ、極性、流れる方向等は、素子1、21の状態により異なっていてもよい。即ち、本明細書における駆動電圧および駆動電流とは、素子1、21がある状態にあるときに、当該状態とは異なる他の状態へ変化できる電圧および電流であればよい。   The driving voltage or current applied to the elements 1 and 21 does not necessarily have to be the same between when the element 1 is in the state A and when it is in the state B, and its size, polarity, flow direction, etc. May differ depending on the state of the elements 1 and 21. That is, the drive voltage and drive current in this specification may be any voltage and current that can change to another state different from the state when the elements 1 and 21 are in a certain state.

素子1、21へは、素子の消費電力をより低減できることから、電圧を印加することが好ましく、パルス状の電圧を印加することが特に好ましい。   Since the power consumption of the element can be further reduced, it is preferable to apply a voltage to the elements 1 and 21, and it is particularly preferable to apply a pulsed voltage.

上述したように、素子1、21では、その電気抵抗値を、素子1、21に駆動電圧または電流を印加するまで保持できるため、素子1、21と、素子1、21における上記状態を検出する機構(即ち、素子1、21の電気抵抗値を検出する機構)とを組み合わせ、上記各状態に対してビットを割り当てる(例えば、状態Aを「0」、状態Bを「1」とする)ことにより、不揮発性の抵抗変化型メモリ(メモリ素子、あるいは、2以上のメモリ素子が配列したメモリアレイ)を構築できる。また、素子1、21では、このような状態の変化を少なくとも2回以上繰り返し行うことができ、不揮発性のランダムアクセスメモリを構築できる。その他、上記各状態に対してONまたはOFFを割り当てることにより、素子1、21をスイッチング素子へ応用することも可能である。   As described above, since the electrical resistance value of the elements 1 and 21 can be maintained until a drive voltage or current is applied to the elements 1 and 21, the above-described states of the elements 1 and 21 and the elements 1 and 21 are detected. Combining a mechanism (that is, a mechanism for detecting the electric resistance value of the elements 1 and 21) and assigning a bit to each of the above states (for example, state A is set to “0” and state B is set to “1”). Thus, a nonvolatile resistance change type memory (memory element or memory array in which two or more memory elements are arranged) can be constructed. Further, in the elements 1 and 21, such a change in state can be repeated at least twice, and a nonvolatile random access memory can be constructed. In addition, it is also possible to apply the elements 1 and 21 to switching elements by assigning ON or OFF to the above states.

素子1、21の電気抵抗値の検出は、例えば、素子1、21に、当該素子における上記状態が変化しない程度の電圧(読出電圧)を印加し、その際、素子1、21に流れる電流値を検出することにより行えばよい。読出電圧としては、素子の消費電力をより低減できることから、パルス状の電圧を印加することが好ましい。読出電圧の大きさは、通常、駆動電圧の大きさの1/4〜1/1000程度である。   For detecting the electric resistance values of the elements 1 and 21, for example, a voltage (read voltage) that does not change the state of the elements is applied to the elements 1 and 21, and the current value flowing through the elements 1 and 21 at that time is detected. May be performed by detecting. As the read voltage, it is preferable to apply a pulse voltage because the power consumption of the element can be further reduced. The magnitude of the read voltage is usually about 1/4 to 1/1000 of the magnitude of the drive voltage.

本発明の抵抗変化素子を用いて抵抗変化型メモリを構築するためには、本発明の素子を半導体素子、例えば、ダイオード、あるいは、MOS電界効果トランジスタ等のトランジスタ等、と組み合わせればよい。   In order to construct a resistance change type memory using the resistance change element of the present invention, the element of the present invention may be combined with a semiconductor element, for example, a diode or a transistor such as a MOS field effect transistor.

本発明の抵抗変化素子は、半導体の製造プロセスを応用し、一般的な薄膜形成プロセスおよび微細加工プロセスにより形成できる。例えば、パルスレーザーデポジション(PLD)、イオンビームデポジション(IBD)、クラスターイオンビーム、およびRF、DC、電子サイクロトン共鳴(ECR)、ヘリコン、誘導結合プラズマ(ICP)、対向ターゲット等の各種スパッタリング法、分子線エピタキシャル法(MBE)等の蒸着法、イオンプレーティング法等を用いればよい。これらPVD(Physical Vapor Deposition)法の他に、CVD(Chemical Vapor Deposition)法、MOCVD(Metal Organic Chemical Vapor Deposition)法、メッキ法、MOD(Metal Organic Decomposition)法、あるいは、ゾルゲル法等を用いてもよい。   The resistance change element of the present invention can be formed by a general thin film forming process and a fine processing process by applying a semiconductor manufacturing process. For example, pulsed laser deposition (PLD), ion beam deposition (IBD), cluster ion beam, and various sputtering such as RF, DC, electron cycloton resonance (ECR), helicon, inductively coupled plasma (ICP), and counter target For example, a vapor deposition method such as molecular beam epitaxy (MBE) or an ion plating method may be used. In addition to these PVD (Physical Vapor Deposition) methods, CVD (Chemical Vapor Deposition) methods, MOCVD (Metal Organic Chemical Vapor Deposition) methods, plating methods, MOD (Metal Organic Decomposition) methods, or sol-gel methods may also be used. Good.

各層の微細加工には、例えば、半導体製造プロセスや磁性デバイス(GMRやTMR等の磁気抵抗素子等)製造プロセスに用いられるイオンミリング、RIE(Reactive Ion Etching)、FIB(Focused Ion Beam)等の物理的あるいは化学的エッチング法、および、微細パターン形成のためのステッパー、EB(Electron Beam)法等を用いたフォトリソグラフィー技術を組み合わせて用いればよい。各層の表面の平坦化には、例えば、CMP(Chemical Mechanical Polishing)、クラスター−イオンビームエッチング等を用いればよい。   For microfabrication of each layer, for example, physical processes such as ion milling, RIE (Reactive Ion Etching), and FIB (Focused Ion Beam) used in semiconductor manufacturing processes and magnetic device (magnetoresistive elements such as GMR and TMR) manufacturing processes. A combination of a photolithography technique using a chemical etching method, a stepper for forming a fine pattern, an EB (Electron Beam) method, or the like may be used. For planarizing the surface of each layer, for example, CMP (Chemical Mechanical Polishing), cluster-ion beam etching, or the like may be used.

以下、実施例により、本発明をより詳細に説明する。本発明は、以下に示す実施例に限定されない。   Hereinafter, the present invention will be described in more detail with reference to examples. The present invention is not limited to the examples shown below.

(実施例1)
実施例1では、図4、5に示すような抵抗変化素子21を接合面22の形状を変化させて複数作製し、作製した各素子への駆動電圧の印加により上記状態を繰り返し変化させた場合における素子の抵抗変化特性の変動を評価した。
(Example 1)
In Example 1, a plurality of variable resistance elements 21 as shown in FIGS. 4 and 5 are manufactured by changing the shape of the bonding surface 22, and the above state is repeatedly changed by applying a drive voltage to each of the manufactured elements. The variation of the resistance change characteristic of the element was evaluated.

評価した各素子サンプルの具体的な形状を図6に示す。   The specific shape of each evaluated element sample is shown in FIG.

図6に示す抵抗変化素子21は、基板10であるSi基板上に、下部電極11、抵抗変化層12および上部電極13が順に積層された積層体14が配置された構造を有する。基板10上の符号31は分離層であり、符号32は上部電極13の引き出しに用いる不純物多結晶シリコン層であり、符号33は下部電極11の引き出しに用いる不純物拡散層である。不純物多結晶シリコン層32および不純物拡散層33と、コンタクトプラグ(以下、単に「プラグ」)34、35および36との間には、スパッタリングによりコバルトを堆積させた後、さらに熱処理して形成したコバルトシリサイド層37を配置した。不純物多結晶シリコン層32および不純物拡散層33は、公知の方法により形成した。   The variable resistance element 21 shown in FIG. 6 has a structure in which a stacked body 14 in which a lower electrode 11, a variable resistance layer 12, and an upper electrode 13 are stacked in this order is disposed on a Si substrate that is the substrate 10. Reference numeral 31 on the substrate 10 is a separation layer, reference numeral 32 is an impurity polycrystalline silicon layer used for extracting the upper electrode 13, and reference numeral 33 is an impurity diffusion layer used for extracting the lower electrode 11. Cobalt formed between the impurity polycrystalline silicon layer 32 and the impurity diffusion layer 33 and the contact plugs (hereinafter simply “plugs”) 34, 35 and 36 by depositing cobalt by sputtering and then further heat-treating. A silicide layer 37 was disposed. The impurity polycrystalline silicon layer 32 and the impurity diffusion layer 33 were formed by a known method.

不純物拡散層33と下部電極11とを電気的に接続するプラグ34、上部電極13と不純物多結晶シリコン層32とを電気的に接続するプラグ35、ならびに、不純物多結晶シリコン層32と、抵抗変化型メモリにおいてビット線またはワード線に相当するメタル配線38とを電気的に接続するプラグ36の各々は、チタン膜と窒化チタン膜とからなるバリアメタルを堆積した後に、タングステンからなるプラグメタルをさらに堆積して形成した。各プラグの形状は、フォトリソグラフィー法およびCMP法により制御した。メタル配線38は、タングステンからなるプラグメタルの代わりにアルミニウムまたは銅を堆積させた以外は、上記各プラグと同様に形成した。   The plug 34 that electrically connects the impurity diffusion layer 33 and the lower electrode 11, the plug 35 that electrically connects the upper electrode 13 and the impurity polycrystalline silicon layer 32, and the resistance change between the impurity polycrystalline silicon layer 32 and Each of the plugs 36 for electrically connecting the metal wiring 38 corresponding to a bit line or a word line in the type memory is formed by depositing a barrier metal made of a titanium film and a titanium nitride film, and further adding a plug metal made of tungsten. Deposited and formed. The shape of each plug was controlled by a photolithography method and a CMP method. The metal wiring 38 was formed in the same manner as the above plugs except that aluminum or copper was deposited instead of the plug metal made of tungsten.

各プラグ間、基板10と下部電極11との間、基板10と抵抗変化層12との間、ならびに、基板10と上部電極13との間には、層間絶縁層39としてTEOS膜を配置した。一対の層間絶縁層39により狭持された符号40で示される部材は、Si34膜からなる水素バリア膜40である。TEOS膜は、TEOS(テトラエチルオルトシリケート)とO3(オゾン)から形成したSiO2膜であり、水素バリア膜40とともに公知の方法により形成した。 Between each plug, between the substrate 10 and the lower electrode 11, between the substrate 10 and the resistance change layer 12, and between the substrate 10 and the upper electrode 13, a TEOS film was disposed as an interlayer insulating layer 39. A member indicated by reference numeral 40 sandwiched between the pair of interlayer insulating layers 39 is a hydrogen barrier film 40 made of a Si 3 N 4 film. The TEOS film is a SiO 2 film formed from TEOS (tetraethylorthosilicate) and O 3 (ozone), and is formed together with the hydrogen barrier film 40 by a known method.

下部電極11は、チタンアルミナイトライドおよび白金をスパッタリング法により堆積させて形成した。上部電極13は、白金をスパッタリング法により堆積させて形成した。下部電極11および上部電極13を形成するスパッタリング条件は、チタンアルミナイトライドおよび白金を堆積するための一般的な条件とした。   The lower electrode 11 was formed by depositing titanium aluminum nitride and platinum by sputtering. The upper electrode 13 was formed by depositing platinum by a sputtering method. The sputtering conditions for forming the lower electrode 11 and the upper electrode 13 were general conditions for depositing titanium aluminum nitride and platinum.

抵抗変化層12は、遷移金属酸化物である酸化鉄(FeOx)をスパッタリング法により堆積させて形成した。酸化鉄の組成は、スパッタリングの条件(主としてスパッタリング雰囲気における酸素分圧比)を変化させることにより、x=3/2〜1の範囲(典型的にはx=4/3)で変化させた。抵抗変化層12を形成する具体的なスパッタリングの条件は、スパッタリング雰囲気がアルゴン−酸素混合雰囲気(典型的には、x=4/3のとき、アルゴン:酸素(分圧比)=8:1)、Si基板温度が150℃、印加電力がRF100W、とした。 The resistance change layer 12 was formed by depositing iron oxide (FeO x ), which is a transition metal oxide, by a sputtering method. The composition of the iron oxide was changed in the range of x = 3/2 to 1 (typically x = 4/3) by changing the sputtering conditions (mainly the oxygen partial pressure ratio in the sputtering atmosphere). Specific sputtering conditions for forming the variable resistance layer 12 are as follows: a sputtering atmosphere is an argon-oxygen mixed atmosphere (typically, when x = 4/3, argon: oxygen (partial pressure ratio) = 8: 1), The Si substrate temperature was 150 ° C. and the applied power was RF 100 W.

積層体14上には、TEOS膜からなる保護絶縁層41、水素バリア膜42、および、BPSG(Boro-Phospho Silicate Glass)膜からなる保護絶縁層43を配置した。これらの各層は公知の方法により形成し、水素バリア膜42は、積層体14全体を被覆するように形成した。   On the stacked body 14, a protective insulating layer 41 made of a TEOS film, a hydrogen barrier film 42, and a protective insulating layer 43 made of a BPSG (Boro-Phospho Silicate Glass) film were arranged. Each of these layers was formed by a known method, and the hydrogen barrier film 42 was formed so as to cover the entire laminate 14.

図6に示す素子21を、下部電極11における抵抗変化層12との接合面22に垂直な方向(図6に示す矢印Cの方向)から見た平面図を図7に示す。なお、図7では、下部電極11、抵抗変化層12、上部電極13およびプラグ35(図4における部材51に相当)以外の各部材の図示を省略し、上部電極13を実線で、下部電極11、抵抗変化層12およびプラグ35を破線で示す。図7に示すように、図6の素子21では、正バイアス電圧の印加により、上部電極13におけるプラグ35との接続部分(即ち、印加面16)から、下部電極11における抵抗変化層12との接合部分(即ち、接合面22)に向かって、上部電極13および抵抗変化層12を電流23が流れると考えられる。   FIG. 7 shows a plan view of the element 21 shown in FIG. 6 as seen from the direction perpendicular to the bonding surface 22 of the lower electrode 11 with the resistance change layer 12 (the direction of the arrow C shown in FIG. 6). In FIG. 7, members other than the lower electrode 11, the resistance change layer 12, the upper electrode 13, and the plug 35 (corresponding to the member 51 in FIG. 4) are omitted, and the upper electrode 13 is indicated by a solid line and the lower electrode 11. The resistance change layer 12 and the plug 35 are indicated by broken lines. As shown in FIG. 7, in the element 21 of FIG. 6, the application of the positive bias voltage causes the connection between the upper electrode 13 and the plug 35 (that is, the application surface 16) to the resistance change layer 12 in the lower electrode 11. It is considered that the current 23 flows through the upper electrode 13 and the resistance change layer 12 toward the bonding portion (that is, the bonding surface 22).

実施例1では、接合面22に垂直な方向から見た当該接合面の形状を変化させたサンプルを11種類(サンプル1〜11)作製した。サンプル1を除く各サンプルでは、接合面22の形状を長方形とし、図7に示す電流23の方向、即ち、印加面16と接合面22とを結ぶ直線の方向、にほぼ垂直な方向が接合面22の長辺となるように各層を形成した。   In Example 1, 11 types (samples 1 to 11) of samples in which the shape of the joint surface viewed from the direction perpendicular to the joint surface 22 was changed were produced. In each sample except Sample 1, the shape of the bonding surface 22 is rectangular, and the direction substantially perpendicular to the direction of the current 23 shown in FIG. 7, that is, the direction of the straight line connecting the application surface 16 and the bonding surface 22 is the bonding surface. Each layer was formed to have 22 long sides.

各サンプルにおける接合面22の短辺および長辺の長さを表1に示す。表1には、接合面22における短辺の長さに対する長辺の長さの比(縦横比)を併せて示す。なお、サンプル1では、短辺の長さと長辺の長さとを同一、即ち、接合面22の形状を正方形とした。各サンプルにおける接合面22の面積(接合面積)は、全て0.36μm2とした。 Table 1 shows the lengths of the short side and the long side of the bonding surface 22 in each sample. Table 1 also shows a ratio (aspect ratio) of the length of the long side to the length of the short side in the joint surface 22. In sample 1, the length of the short side is the same as the length of the long side, that is, the shape of the bonding surface 22 is a square. The area (bonding area) of the bonding surface 22 in each sample was all 0.36 μm 2 .

上記各サンプル1〜11に対して、パルスジェネレータを用い、メタル配線38と基板10との間、即ち、上部電極13と下部電極11との間、に、駆動電圧としてパルス状の正バイアス電圧および負バイアス電圧(各々の大きさは3V)、読出電圧としてパルス状の正バイアス電圧(大きさ0.05V)を印加して、素子の上記状態を変化させながら各状態における電気抵抗値を検出し、素子の抵抗変化特性を評価した。素子の抵抗変化比は、素子の電気抵抗値の最大値をRMAX、最小値をRMINとして、(RMAX−RMIN)/RMINで示す式より求めた。素子の抵抗変化比の評価方法は、実施例2においても同様である。 For each of the above samples 1 to 11, a pulse generator is used as a drive voltage between the metal wiring 38 and the substrate 10, that is, between the upper electrode 13 and the lower electrode 11, and a pulsed positive bias voltage and Applying a negative bias voltage (each magnitude is 3V) and a pulsed positive bias voltage (size 0.05V) as a read voltage, the electrical resistance value in each state is detected while changing the above-mentioned state of the element. The resistance change characteristics of the element were evaluated. The resistance change ratio of the element was obtained from an equation represented by (R MAX −R MIN ) / R MIN where R MAX is the maximum value of the electric resistance value of the element and R MIN is the minimum value. The evaluation method of the resistance change ratio of the element is the same in the second embodiment.

駆動電圧として正バイアス電圧および負バイアス電圧を交互に数回印加した直後における各サンプルの抵抗変化比(初期抵抗変化比)は、全てのサンプルで約220であった。その後、駆動電圧として正バイアス電圧および負バイアス電圧の印加を交互に100回繰り返したところ、各サンプルの抵抗変化比は表1のようになった。   The resistance change ratio (initial resistance change ratio) of each sample immediately after applying the positive bias voltage and the negative bias voltage alternately several times as the drive voltage was about 220 for all the samples. Thereafter, application of a positive bias voltage and a negative bias voltage as the drive voltage was repeated 100 times alternately, and the resistance change ratio of each sample was as shown in Table 1.

Figure 2008028248
Figure 2008028248

表1に示すように、縦横比が1.5〜5の範囲であるサンプル4〜10では、素子21の抵抗変化比が20以上を保持できたが、接合面22の形状が正方形であるサンプル1をはじめ、縦横比が1.18のサンプル2、縦横比が10のサンプル11では、素子21の抵抗変化比がほぼ消失した。これらのサンプルでは、駆動電圧を繰り返し印加することにより、抵抗変化層12への部分的な電流の集中が生じ、抵抗変化層12の劣化が生じたと考えられる。   As shown in Table 1, in samples 4 to 10 in which the aspect ratio is in the range of 1.5 to 5, the resistance change ratio of the element 21 can be maintained at 20 or more, but the shape of the bonding surface 22 is a square. 1 and sample 2 with an aspect ratio of 1.18 and sample 11 with an aspect ratio of 10, the resistance change ratio of the element 21 almost disappeared. In these samples, it is considered that partial application of current to the variable resistance layer 12 caused by repeated application of the drive voltage resulted in deterioration of the variable resistance layer 12.

(実施例2)
実施例2では、図1、2に示すような抵抗変化素子1を、接合面15の形状を変化させて複数作製し、作製した各素子への駆動電圧の印加により上記状態を繰り返し変化させた場合における素子の抵抗変化特性の変動を評価した。
(Example 2)
In Example 2, a plurality of variable resistance elements 1 as shown in FIGS. 1 and 2 were manufactured by changing the shape of the bonding surface 15, and the above state was repeatedly changed by applying a drive voltage to each of the manufactured elements. The variation of the resistance change characteristic of the element in each case was evaluated.

評価した各素子サンプルの具体的な形状は、図6に示す素子21における抵抗変化層12の面積(矢印Cの方向から見た面積)を下部電極12の面積(矢印Cの方向から見た面積)よりも小さくした形状とした。   The specific shape of each element sample evaluated is the area of the resistance change layer 12 (area seen from the direction of arrow C) in the element 21 shown in FIG. 6 as the area of the lower electrode 12 (area seen from the direction of arrow C). ).

実施例2で評価した素子1を、上部電極13における抵抗変化層12との接合面15に垂直な方向から見た平面図を図8に示す。なお、図8では、下部電極11、抵抗変化層12、上部電極13およびプラグ35(図1における部材51に相当)以外の各部材の図示を省略し、上部電極13を実線で、下部電極11、抵抗変化層12およびプラグ35を破線で示す。図8に示すように、実施例2で評価した素子1では、正バイアス電圧の印加により、印加面16から接合面15に向かって上部電極13を電流17が流れると考えられる。   FIG. 8 shows a plan view of the element 1 evaluated in Example 2 as seen from the direction perpendicular to the bonding surface 15 of the upper electrode 13 with the resistance change layer 12. In FIG. 8, illustration of each member other than the lower electrode 11, the resistance change layer 12, the upper electrode 13, and the plug 35 (corresponding to the member 51 in FIG. 1) is omitted, and the upper electrode 13 is indicated by a solid line and the lower electrode 11. The resistance change layer 12 and the plug 35 are indicated by broken lines. As shown in FIG. 8, in the element 1 evaluated in Example 2, it is considered that a current 17 flows through the upper electrode 13 from the application surface 16 toward the bonding surface 15 by applying a positive bias voltage.

実施例2では、接合面15に垂直な方向から見た当該接合面の形状を変化させたサンプルを11種類(サンプル12〜22)作製した。サンプル12を除く各サンプルでは、接合面15の形状を長方形とし、図8に示す電流17の方向、即ち、印加面16と接合面15とを結ぶ直線の方向、にほぼ垂直な方向が接合面15の長辺となるように各層を形成した。   In Example 2, 11 types (samples 12 to 22) of samples in which the shape of the joint surface viewed from the direction perpendicular to the joint surface 15 was changed were produced. In each sample except the sample 12, the shape of the bonding surface 15 is rectangular, and the direction substantially perpendicular to the direction of the current 17 shown in FIG. 8, that is, the direction of the straight line connecting the application surface 16 and the bonding surface 15 is the bonding surface. Each layer was formed to have 15 long sides.

各サンプルにおける接合面15の短辺および長辺の長さを表2に示す。表2には、接合面15における短辺の長さに対する長辺の長さの比(縦横比)を併せて示す。なお、サンプル12では、短辺の長さと長辺の長さとを同一、即ち、接合面15の形状を正方形とした。各サンプルにおける接合面15の面積(接合面積)は、全て0.36μm2とした。 Table 2 shows the lengths of the short side and the long side of the bonding surface 15 in each sample. Table 2 also shows the ratio of the length of the long side to the length of the short side of the joint surface 15 (aspect ratio). In the sample 12, the length of the short side is the same as the length of the long side, that is, the shape of the bonding surface 15 is a square. The area (bonding area) of the bonding surface 15 in each sample was all 0.36 μm 2 .

駆動電圧として正バイアス電圧および負バイアス電圧を交互に数回印加した直後における各サンプルの抵抗変化比(初期抵抗変化比)は、全てのサンプルで約160であった。その後、駆動電圧として正バイアス電圧および負バイアス電圧の印加を交互に100回繰り返したところ、各サンプルの抵抗変化比は表2のようになった。   The resistance change ratio (initial resistance change ratio) of each sample immediately after applying a positive bias voltage and a negative bias voltage several times alternately as a drive voltage was about 160 for all the samples. Thereafter, application of a positive bias voltage and a negative bias voltage as the drive voltage was repeated 100 times alternately, and the resistance change ratio of each sample was as shown in Table 2.

Figure 2008028248
Figure 2008028248

表2に示すように、縦横比が1.5〜5の範囲であるサンプル15〜21では、素子1の抵抗変化比が6以上、場合によっては20以上を保持できたが、接合面15の形状が正方形であるサンプル1をはじめ、縦横比が1.18のサンプル13、縦横比が10のサンプル22では、素子1の抵抗変化比がほぼ消失した。これらのサンプルでは、駆動電圧を繰り返し印加することにより、抵抗変化層12への部分的な電流の集中が生じ、抵抗変化層12の劣化が生じたと考えられる。   As shown in Table 2, in Samples 15 to 21 in which the aspect ratio is in the range of 1.5 to 5, the resistance change ratio of the element 1 was 6 or more, and in some cases, 20 or more could be maintained. In the sample 1 having a square shape, the sample 13 having an aspect ratio of 1.18, and the sample 22 having an aspect ratio of 10, the resistance change ratio of the element 1 almost disappeared. In these samples, it is considered that partial application of current to the variable resistance layer 12 caused by repeated application of the drive voltage resulted in deterioration of the variable resistance layer 12.

以上説明したように、本発明の抵抗変化素子は、素子への駆動電圧または電流の印加時に、抵抗変化層への部分的な電流の集中を緩和でき、使用時における抵抗変化層の劣化を抑制できる。   As described above, the variable resistance element of the present invention can alleviate partial current concentration on the variable resistance layer when a driving voltage or current is applied to the element, and suppresses deterioration of the variable resistance layer during use. it can.

本発明の抵抗変化素子は、次世代の高密度不揮発性メモリを始めとする様々な電子デバイスへの応用が可能であり、例えば、情報通信端末等に使用される不揮発性メモリ、スイッチング素子、センサ、画像表示装置等への応用が考えられる。   The resistance change element of the present invention can be applied to various electronic devices including a next-generation high-density nonvolatile memory, for example, a nonvolatile memory, a switching element, and a sensor used for information communication terminals and the like. Application to an image display device or the like can be considered.

本発明の抵抗変化素子の一例を模式的に示す断面図である。It is sectional drawing which shows typically an example of the resistance change element of this invention. 図1に示す抵抗変化素子を、その上部電極における抵抗変化層との接合面に垂直な方向から見た平面図である。It is the top view which looked at the variable resistance element shown in FIG. 1 from the direction perpendicular | vertical to the joint surface with the variable resistance layer in the upper electrode. 本発明の抵抗変化素子の別の一例を模式的に示す平面図である。It is a top view which shows typically another example of the variable resistance element of this invention. 本発明の抵抗変化素子のまた別の一例を模式的に示す平面図である。It is a top view which shows typically another example of the resistance change element of this invention. 図4に示す抵抗変化素子を、その下部電極における抵抗変化層との接合面に垂直な方向から見た平面図である。It is the top view which looked at the resistance change element shown in FIG. 4 from the direction perpendicular | vertical to the joint surface with the resistance change layer in the lower electrode. 実施例1で評価した抵抗変化素子サンプルを模式的に示す断面図である。2 is a cross-sectional view schematically showing a resistance change element sample evaluated in Example 1. FIG. 図6に示す抵抗変化素子を、その下部電極における抵抗変化層との接合面に垂直な方向から見た平面図である。It is the top view which looked at the resistance change element shown in FIG. 6 from the direction perpendicular | vertical to the joint surface with the resistance change layer in the lower electrode. 実施例2で評価した抵抗変化素子サンプルを、その上部電極における抵抗変化層との接合面に垂直な方向から見た模式平面図である。It is the model top view which looked at the resistance change element sample evaluated in Example 2 from the direction perpendicular | vertical to the joint surface with the resistance change layer in the upper electrode.

符号の説明Explanation of symbols

1 抵抗変化素子
10 基板
11 下部電極
12 抵抗変化層
13 上部電極
14 多層構造体(積層体)
15 接合面
16 印加面
17 電流
18 分割線
19、20 部分
21 抵抗変化素子
22 接合面
23 電流
31 分離層
32 不純物多結晶シリコン層
33 不純物拡散層
34、35、36 コンタクトプラグ
37 コバルトシリサイド層
38 メタル配線
39 層間絶縁層
40 水素バリア膜
41 保護絶縁層
42 水素バリア膜
43 保護絶縁層
51 部材
DESCRIPTION OF SYMBOLS 1 Resistance change element 10 Board | substrate 11 Lower electrode 12 Resistance change layer 13 Upper electrode 14 Multilayer structure (laminated body)
DESCRIPTION OF SYMBOLS 15 Junction surface 16 Application surface 17 Current 18 Dividing line 19, 20 Portion 21 Resistance change element 22 Junction surface 23 Current 31 Separation layer 32 Impurity polycrystalline silicon layer 33 Impurity diffusion layer 34, 35, 36 Contact plug 37 Cobalt silicide layer 38 Metal Wiring 39 Interlayer insulating layer 40 Hydrogen barrier film 41 Protective insulating layer 42 Hydrogen barrier film 43 Protective insulating layer 51 Member

Claims (6)

第1の電極と、第2の電極と、前記第1および第2の電極に狭持された抵抗変化層とを含み、
前記第1および第2の電極間の電気抵抗値が異なる2以上の状態が存在し、
前記抵抗変化層に、前記第1および第2の電極を介して駆動電圧または駆動電流を印加することにより、前記2以上の状態から選ばれる1つの状態から他の状態へと変化する抵抗変化素子であって、
前記第1の電極における前記抵抗変化層との接合面の形状が長方形であり、
前記接合面に垂直な方向から見たときに、
前記第1の電極における前記接合面と重複しない部分に、前記第1の電極に前記駆動電圧または駆動電流を印加する印加面があり、かつ、前記接合面は、前記駆動電圧または駆動電流の印加時に前記印加面から前記接合面へと前記第1の電極を流れる電流の方向に実質的に垂直な方向に長辺を有する、抵抗変化素子。
A first electrode; a second electrode; and a resistance change layer sandwiched between the first and second electrodes;
There are two or more states with different electrical resistance values between the first and second electrodes,
A resistance change element that changes from one state selected from the two or more states to another state by applying a drive voltage or a drive current to the resistance change layer via the first and second electrodes. Because
The shape of the joint surface with the resistance change layer in the first electrode is a rectangle,
When viewed from a direction perpendicular to the joint surface,
There is an application surface for applying the drive voltage or drive current to the first electrode at a portion of the first electrode that does not overlap the junction surface, and the junction surface is applied with the drive voltage or drive current. A variable resistance element that sometimes has a long side in a direction substantially perpendicular to the direction of current flowing through the first electrode from the application surface to the bonding surface.
前記第1の電極の形状が長方形であり、
前記第1の電極を、その短辺に平行な分割線で2つに等分割したときに、等分割した一方の部分に前記接合面があり、他方の部分に前記印加面がある請求項1に記載の抵抗変化素子。
The first electrode has a rectangular shape;
2. When the first electrode is equally divided into two by a dividing line parallel to the short side thereof, the joint surface is in one of the equally divided portions, and the application surface is in the other portion. The resistance change element according to 1.
前記接合面の短辺と長辺との長さの比が、短辺:長辺=1:1.5〜1:5である請求項1に記載の抵抗変化素子。   2. The variable resistance element according to claim 1, wherein a ratio of a length of a short side to a long side of the joint surface is short side: long side = 1: 1.5 to 1: 5. 第1の電極と、第2の電極と、前記第1および第2の電極に狭持された抵抗変化層とを含み、
前記第1および第2の電極間の電気抵抗値が異なる2以上の状態が存在し、
前記抵抗変化層に、前記第1および第2の電極を介して駆動電圧または駆動電流を印加することにより、前記2以上の状態から選ばれる1つの状態から他の状態へと変化する抵抗変化素子であって、
前記第1の電極に、該電極に前記駆動電圧または駆動電流を印加する印加面があり、
前記第2の電極における前記抵抗変化層との接合面の形状が長方形であり、
前記接合面に垂直な方向から見たときに、
前記印加面と前記接合面とが重複せず、前記印加面と前記接合面との間に前記抵抗変化層があり、かつ、前記接合面は、前記駆動電圧または駆動電流の印加時に前記印加面から前記接合面へと前記第1の電極および前記抵抗変化層を流れる、前記方向から見た電流の方向に対して、実質的に垂直な方向に長辺を有する、抵抗変化素子。
A first electrode; a second electrode; and a resistance change layer sandwiched between the first and second electrodes;
There are two or more states with different electrical resistance values between the first and second electrodes,
A resistance change element that changes from one state selected from the two or more states to another state by applying a drive voltage or a drive current to the resistance change layer via the first and second electrodes. Because
The first electrode has an application surface for applying the driving voltage or driving current to the electrode,
The shape of the joint surface with the resistance change layer in the second electrode is a rectangle,
When viewed from a direction perpendicular to the joint surface,
The application surface and the bonding surface do not overlap, the resistance change layer is between the application surface and the bonding surface, and the bonding surface is the application surface when the driving voltage or driving current is applied. A variable resistance element having a long side in a direction substantially perpendicular to a direction of current viewed from the direction flowing through the first electrode and the variable resistance layer from the first to the junction surface.
前記接合面の短辺と長辺との長さの比が、短辺:長辺=1:1.5〜1:5である請求項4に記載の抵抗変化素子。   5. The variable resistance element according to claim 4, wherein a ratio of a length between a short side and a long side of the joint surface is short side: long side = 1: 1.5 to 1: 5. 請求項1〜5のいずれかに記載の抵抗変化素子をメモリ素子として備える抵抗変化型メモリ。   A resistance change type memory comprising the resistance change element according to claim 1 as a memory element.
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WO2010067585A1 (en) * 2008-12-10 2010-06-17 パナソニック株式会社 Resistance change element and nonvolatile semiconductor storage device using same

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WO2009150814A1 (en) * 2008-06-10 2009-12-17 パナソニック株式会社 Semiconductor device, semiconductor device manufacturing method, semiconductor chip and system
JP4575999B2 (en) * 2008-06-10 2010-11-04 パナソニック株式会社 Semiconductor device, semiconductor device manufacturing method, semiconductor chip and system
JPWO2009150814A1 (en) * 2008-06-10 2011-11-10 パナソニック株式会社 Semiconductor device, semiconductor device manufacturing method, semiconductor chip and system
US8624214B2 (en) 2008-06-10 2014-01-07 Panasonic Corporation Semiconductor device having a resistance variable element and a manufacturing method thereof
WO2010067585A1 (en) * 2008-12-10 2010-06-17 パナソニック株式会社 Resistance change element and nonvolatile semiconductor storage device using same
JP4937413B2 (en) * 2008-12-10 2012-05-23 パナソニック株式会社 Resistance change element and nonvolatile semiconductor memory device using the same
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