JP2008071786A - Resistance changing type memory and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a resistance changing type memory which has a different structure from the conventional ones and is superior in producibility and which can establish micro fabrication of elements, and to provide its manufacturing method. <P>SOLUTION: A multilayer structure 18 which is provided with a lower wiring electrode 11, an upper wiring electrode 12 and a resistance changing layer 15 pinched with the lower wiring electrode 11 and the upper wiring electrode 12 is arranged on a substrate 10. The resistance changing layer 15 is bonded with the lower wiring electrode 11 and the upper wiring electrode 12, and it is provided with a resistance changing section 13 which has two or more statuses with different resistances and changes from one status selected from the two or more statuses to another status by application of driving voltage or current through both wiring electrodes, and a separation section 14 which is higher in electric resistance than the resistance changing section and surrounds the resistance changing section. The resistance changing section 13 and the separation section 14 are made of metal oxide of the same kind that is different in oxidation state from the resistance changing section 13 and the separation section 14, and bits are assigned to the oxidation state in the resistance changing section. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a resistance change type memory having a resistance change layer whose electric resistance value is changed by application of a driving voltage or current through a wiring electrode, and a bit is assigned to the state of the electric resistance value of the resistance change layer. And its manufacturing method.

  Memory elements are used in a wide range of fields as important basic electronic components that support the information society. In recent years, with the widespread use of portable information terminals, there has been an increasing demand for miniaturization of memory elements, and nonvolatile memory elements are no exception. However, as the miniaturization of the device reaches the nanometer range, in a conventional charge storage type memory device (typically DRAM: Dynamic Random Access Memory), the charge capacity C per information unit (bit) decreases. Although various improvements have been made to avoid this problem, there are concerns about future technical limitations.

  As a memory element that is not easily affected by miniaturization, not a charge capacity C but a nonvolatile memory element (resistance change type memory element) that records information by a change in electric resistance value R has been attracting attention. As a type memory element, development of a resistance change element in which the electric resistance value R is changed by application of a driving voltage or current is underway. The resistance change element has two or more states having different electric resistance values, and a resistance change memory can be constructed by assigning a bit to each state.

A resistance change type memory is usually composed of a multilayer structure including a lower wiring electrode, an upper wiring electrode, and a resistance change layer sandwiched between both of the wiring electrodes, and is driven to the resistance change layer via the wiring electrode. It functions by application of voltage (current) and detection of the above state of the resistance change layer via the wiring electrode. Conventional resistance change type memories such as Patent Documents 1 and 2 have a structure in which a resistance change layer is arranged in a dot shape at an intersection between a lower wiring electrode and an upper wiring electrode, that is, between adjacent intersections, that is, In general, a protective insulating film made of SiO ₂ or the like is disposed between adjacent resistance change layers.
JP 2003-197877 A JP 2002-280542 A

  In the resistance change type memory having the above conventional structure, it is necessary to introduce a mask or a microfabrication process in order to form a resistance change layer arranged in a dot shape at the intersection of the lower wiring electrode and the upper wiring electrode. There is. In order to obtain a memory with excellent productivity, a memory having a structure in which a resistance change layer can be formed by a method in which the use of these masks or a fine processing process is omitted is desired.

  As a memory having such a structure, for example, it has a uniform resistance change layer common to a plurality of wiring electrodes, and each resistance change element (memory element) is connected to each wiring electrode in the resistance change layer. There exists a resistance change type memory treated as However, in such a memory, current diffusion occurs in the resistance change layer, so that problems such as crosstalk between adjacent elements are likely to occur, and it is difficult to miniaturize the elements and to increase the integration of the memory accordingly. .

  Accordingly, an object of the present invention is to provide a resistance change type memory having a structure different from that of the above conventional resistance change type memory, excellent in productivity, and capable of realizing miniaturization of an element, and a manufacturing method thereof.

  In the resistance change type memory according to the present invention, a multilayer structure having a lower wiring electrode, an upper wiring electrode, and a resistance change layer sandwiched between the lower wiring electrode and the upper wiring electrode is disposed on a substrate. Yes. The resistance change layer is bonded to the lower wiring electrode and the upper wiring electrode and has two or more states having different electric resistance values, and the two or more are applied by applying a driving voltage or current through both the wiring electrodes. A resistance changing portion that changes from one state selected from the states to another state, and a separation portion that has an electrical resistance value higher than that of the resistance changing portion and surrounds the resistance changing portion. The resistance change portion and the separation portion are made of the same kind of metal oxide having different oxidation states. Bits are assigned to the states in the resistance change section.

  Focusing on one variable resistance element in the variable resistance memory of the present invention, the variable resistance element (the variable resistance element of the present invention) has a lower electrode, an upper electrode, the lower electrode, and the upper electrode on a substrate. A multilayer structure having a resistance change layer sandwiched between the layers is disposed. The resistance change layer is bonded to the lower electrode and the upper electrode, has two or more states having different electric resistance values, and is applied from the two or more states by application of a driving voltage or current through both the electrodes. A resistance change portion that changes from one selected state to another state; and a separation portion that has an electrical resistance value higher than that of the resistance change portion and surrounds the resistance change portion. The resistance change portion and the separation portion are made of the same kind of metal oxide having different oxidation states.

  The method of manufacturing a resistance change type memory according to the present invention is the method of manufacturing the resistance change type memory according to the present invention, wherein a lower wiring electrode and a metal oxide layer are sequentially formed on a substrate, and then the metal oxide layer is formed. A stacking step of partially forming an upper wiring electrode on the surface of the metal, and placing the surface of the metal oxide layer partially covered with the upper wiring electrode in an oxidizing atmosphere to oxidize the metal oxide layer. And an oxidation step for forming a resistance change layer having a separation part and a resistance change part having different states. The metal oxide layer formed in the stacking step has two or more states having different electric resistance values, and changes from one state selected from the two or more states to another state by application of a driving voltage or current. It is a layer to do.

  According to the present invention, by using a resistance change layer having a resistance change portion and a separation portion made of the same kind of metal oxides having different oxidation states, the productivity is improved and the device is miniaturized and highly integrated. The resistance change type memory can be realized.

  In the manufacturing method of the present invention, instead of arranging a dot-shaped resistance change layer for each memory element, a metal oxide layer sandwiched between the lower wiring electrode and the upper wiring electrode is formed in the stacking process, and an oxidation process is performed. In order to form a resistance change layer having a resistance change portion and a separation portion by using a partial covering of the surface of the metal oxide layer by the upper wiring electrode, miniaturization of the element and accompanying high integration are required. The realized resistance change type memory can be manufactured with high productivity.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the same reference numerals may be given to the same members, and overlapping descriptions may be omitted.

  The resistance change memory 1 shown in FIG. 1 includes a substrate 10, a pair of wiring electrodes including a lower wiring electrode 11 and an upper wiring electrode 12, and a resistance change layer 15 sandwiched between the lower wiring electrode 11 and the upper wiring electrode 12. Including. The lower electrode wiring 11, the resistance change layer 15, and the upper electrode wiring 12 are arranged on the substrate 10 in the above order so as to be in contact with each other as the multilayer structure 18.

  The resistance change layer 15 includes a resistance change portion 13 and a separation portion 14 made of the same kind of metal oxide. “The same kind of metal oxide” means that the metal elements constituting the oxide are the same. From the judgment of whether or not they are the same, the metal contained in a trace amount due to diffusion from the wiring electrode, etc. Excludes elements. The resistance change unit 13 and the separation unit 14 have different oxidation states, and the separation unit 14 usually has a higher degree of oxidation than the resistance change unit 13. Since such a resistance change layer 15 can be formed by, for example, the manufacturing method of the present invention described later, specifically, by further oxidizing the metal oxide layer, the lower wiring electrode and the upper wiring electrode are formed. The memory 1 is more productive than the conventional resistance change memory in which the resistance change layers are arranged in the form of dots at the intersections. In the manufacturing method of the present invention, the portion where the metal oxide layer is further oxidized becomes the separation portion 14, and the portion where the oxidation is suppressed becomes the resistance change portion 13.

  The resistance change portion 13 is joined to the lower wiring electrode 11 and the upper wiring electrode 12. The resistance change section 13 has two or more states having different electric resistance values, and is selected from the two or more states by applying a driving voltage (current) through the lower wiring electrode 11 and the upper wiring electrode 12. Change from one state to another. Typically, the resistance change unit 13 has two states, a relatively high resistance state (state A) and a relatively low resistance state (state B), and applies a drive voltage (current). Thus, the state A changes from the state A to the state B or from the state B to the state A. In the memory 1, bits are assigned to such a state in the resistance change unit 13.

  The separation unit 14 has an electrical resistance value higher than that of the resistance change unit 13 and is disposed so as to surround the resistance change unit 13. Here, “surround” refers to being disposed on the entire side surface of the resistance change portion 13 when viewed from a direction perpendicular to the main surface of the substrate 10. Since the adjacent resistance change portions 13 can be electrically separated by the separation portion 14, the occurrence of crosstalk between the resistance change portions 13 can be suppressed, and the miniaturization of elements and the high integration of the memory 1 associated therewith can be achieved. Implementation is easier. As described above, since the separation portion 14 formed by the manufacturing method of the present invention is a portion in which the metal oxide layer is further oxidized to increase the resistance, the separation portion 14 is “high resistance portion” or “high resistance”. It can be said that it is a “resistance alteration part”.

  FIG. 2 shows a plan view of the memory 1 of FIG. 1 as viewed from above. A section AA in FIG. 2 corresponds to FIG.

  As shown in FIGS. 1 and 2, in the memory 1, the lower wiring electrode 11 and the upper wiring electrode 12 intersect with each other, and a resistance change portion 13 is disposed at the intersection of both wiring electrodes. The memory of the present invention does not necessarily have such a configuration. For example, the lower wiring electrode 11 and the upper wiring electrode 12 may extend in parallel in the same direction. By using the memory 1 as shown, a memory array having a so-called XY arrangement can be constructed.

  In the memory 1, two or more lower wiring electrodes 11 are arranged in a stripe shape. As described above, in the memory of the present invention, at least one selected from the lower wiring electrode and the upper wiring electrode may be arranged in a stripe shape, and in this case, the construction of the memory array becomes easier. When two or more wiring electrodes are arranged in a stripe shape, a memory array having a so-called XY arrangement can be constructed.

  The type of the metal oxide constituting the resistance change portion 13 is not particularly limited as long as it is a metal oxide generally used as a resistance change layer of the resistance change element. For example, it may be a transition metal oxide, and more specifically, may be at least one selected from iron oxide, nickel oxide, and copper oxide. As described above, the separation unit 14 is made of a compound obtained by further oxidizing these metal oxides.

For example, when the resistance change portion 13 and the separation portion 14 are made of iron oxide, the composition as the resistance change portion 13 is, for example, Fe ₃ O ₄ , and the composition as the separation portion 14 is, for example, Fe ₃ O _{4 + d1} ( 0 <d1 ≦ 0.5). When the resistance change portion 13 and the separation portion 14 are made of nickel oxide, the composition as the resistance change portion 13 is, for example, NiO _1-d2 (0 <d2 ≦ 0.5), and the composition as the separation portion 14 is, for example, NiO. However, in the vicinity of the boundary between the resistance change portion 13 and the separation portion 14, the oxidation state may be an intermediate value, so even in the resistance change portion 13, NiO _1-d3 (0 <d3 ≦ 0. 5, d3 <d2). When the resistance change portion 13 and the separation portion 14 are made of copper oxide, the composition as the resistance change portion 13 is, for example, CuO _1-d4 (0 <d4 ≦ 0.75), and the composition as the separation portion 14 is, for example, CuO It is. However, in the vicinity of the boundary between the resistance change portion 13 and the separation portion 14, the oxidation state may have an intermediate value, so even the resistance change portion 13 is CuO _1-d5 (0 <d5 ≦ 0. 75, d5 <d4). What is necessary is just to evaluate the composition of the resistance change part 13 and the isolation | separation part 14 by analytical methods, such as an Auger electron spectroscopy, the crystal structure analysis by X-ray diffraction, an infrared spectroscopy, a Raman spectroscopy, for example.

  The electrical resistance value of the separation part 14 only needs to be larger than that of the resistance change part 13. For example, the volume resistivity is preferably 10 Ω · cm or more.

  The electric resistance value of the resistance change portion 13 is preferably in the range of, for example, about 1 mΩ · cm to 10 Ω · cm in terms of volume resistivity.

  In the memory 1, as shown in FIG. 2, the upper wiring electrode 12 has a constricted portion 20 whose wiring width is narrowed, and a portion of the resistance change layer 15 located under the constricted portion 20 is a separation portion. 14 In other words, in this case, the constricted portion 20 is not positioned on the resistance change portion 13. Such a structure is formed by, for example, forming the upper wiring electrode 12 having the constricted portion 20 in the manufacturing method of the present invention, and using the constricted portion 20 to change the resistance having the resistance changing portion 13 and the separating portion 14. It is formed when the layer 15 is formed. In addition, the wiring width of the wiring electrode in this specification is the wiring width seen from the direction perpendicular to the main surface of the substrate.

  The degree of narrowing of the wiring width of the constricted portion 20 is not particularly limited. For example, the wiring width of the constricted portion 20 (X1 shown in FIG. 2) is the wiring width of the upper wiring electrode 12 at the joint portion with the resistance change portion 13. It may be in the range of about 20 to 80% of (X2 shown in FIG. 2). As will be described later in the description of the manufacturing method of the present invention, the degree of narrowing of the wiring width X1 with respect to the wiring width X2 may be adjusted according to the value of the wiring width X2.

  The shape of the upper wiring electrode 12 is not particularly limited to the example shown in FIGS. 1 and 2 and may not have the constricted portion 20. However, when a resistance change type memory is formed by the manufacturing method of the present invention, it will be described later. As described above, the upper wiring electrode 12 having the constricted portion 20 has the resistance change portion 13 and the separation portion 14, and the resistance change portion 13 intersects the lower wiring electrode 11 and the upper wiring electrode 12. It is easy to form the resistance change layer 15 positioned at the position.

  In the memory 1, an insulating layer 16 is disposed between adjacent lower wiring electrodes 11, and the wiring electrodes are electrically separated from each other.

  In FIG. 2, for convenience, the shape of the resistance change portion 13 is shown as a rectangular shape. However, when the memory 1 is formed by the manufacturing method of the present invention, the corner portion is actually rounded. Sometimes.

  In the resistance change type memory according to the present invention, the lower wiring electrode 11 may have a constricted portion with a reduced wiring width. A specific example of the resistance change type memory having such a structure will be described later.

  In the resistance change memory according to the present invention, the multilayer structure 18 including the lower wiring electrode 11, the resistance change layer 15, and the upper wiring electrode 12 may be arranged on the substrate 10 in multiple stages. In this case, multi-level memory becomes easier. The upper wiring electrode of the multilayer structure arranged at the nth stage (n is a natural number) counted from the substrate side and the lower wiring electrode of the multilayer structure arranged at the (n + 1) th stage, if necessary, Can be shared.

  1 can be said to be an example of the variable resistance element of the present invention. That is, the resistance change element 2 is sandwiched between the substrate 10, a pair of electrodes including a lower wiring electrode 11 corresponding to the lower electrode and an upper wiring electrode 12 corresponding to the upper electrode, and the lower wiring electrode 11 and the upper wiring electrode 12. The resistance change layer 15 is included. The lower wiring electrode 11, the resistance change layer 15, and the upper wiring electrode 12 are arranged on the substrate 10 in the above order so as to be in contact with each other as the multilayer structure 18.

  The lower wiring electrode 11 and the upper wiring electrode 12 may basically have conductivity. For example, platinum (Pt), ruthenium (Ru), iridium (Ir), titanium (Ti), aluminum (Al) , Copper (Cu), tantalum (Ta), iridium-tantalum alloy (Ir-Ta), or alloys or multilayer films thereof, oxides thereof, tin-doped indium oxide (ITO), or TiN (nitriding) Titanium), nitrides such as TiAlN (titanium aluminum nitride), and other materials that can be formed by fluoride, carbide, boride, silicide, or the like.

  The substrate 10 may be, for example, a Si (silicon) substrate. In this case, the combination of the resistance change type memory of the present invention and the semiconductor element is facilitated. The surface of the substrate 10 in contact with the lower wiring electrode 11 may be oxidized (an oxide film may be formed on the surface of the substrate 10). Note that in this specification, a processed substrate on which a transistor, a contact plug, and the like are formed is also referred to as a “substrate”.

The insulating layer 16 only needs to be able to electrically isolate adjacent lower wiring electrodes 11 from each other, and may be made of a material generally used for an insulating layer of a semiconductor element such as a memory such as SiO ₂ or Al ₂ O _3. . The insulating layer 16 may be an organic material such as a resist material. In this case, since the insulating layer 16 can be easily formed by spinner coating or the like, the insulating layer 16 is formed on an uneven surface. In this case, the insulating layer 16 having a flat surface can be easily formed. An example of such an organic material is polyimide.

  3A to 3D and FIGS. 4A to 4D show an example of the manufacturing method of the present invention. 3A to 3D correspond to the cross section AA of FIGS. 4A to 4D, respectively.

  First, a plurality of lower wiring electrodes 11 are formed in a stripe shape on the substrate 10 (FIGS. 3A and 4A). In the example shown in FIGS. 3A and 4A, the insulating layer 16 is disposed between the adjacent lower wiring electrodes 11, but such a structure is formed after the insulating layer 16 is formed on the substrate 10, for example. A groove portion for the lower wiring electrode 11 is provided in the insulating layer 16, and after the lower wiring electrode 11 is embedded in the groove portion, the surface thereof can be planarized by CMP (Chemical Mechanical Polishing). Alternatively, for example, after forming the plurality of lower wiring electrodes 11 in a stripe shape on the substrate 10, the insulating layer 16 is deposited on the entire surface including the substrate 10 and the lower wiring electrodes 11, and dry etching treatment, or It can be formed by a combination of CMP and dry etching.

  The lower wiring electrode 11 formed on the substrate 10 can be formed in an arbitrary form according to a configuration necessary as a memory. For example, one lower wiring electrode 11 may be formed, or FIG. Even when the plurality of lower wiring electrodes 11 are formed as shown in FIG.

  Next, a metal oxide layer 17 is formed on the layer including the lower wiring electrode 11 (FIGS. 3B and 4B). The metal oxide layer 17 has two or more states having different electric resistance values, and is a layer that changes from one state selected from the two or more states to another state by application of a driving voltage or current, For example, the same material as that of the resistance change portion 13 described above may be deposited and formed.

  Next, the upper wiring electrode 12 is partially formed on the surface of the metal oxide layer 17 so as to sandwich the metal oxide layer 17 together with the lower wiring electrode 11 (FIGS. 3C and 4C: above, laminating process). . Here, “partially forming the upper wiring electrode 12 on the surface of the metal oxide layer 17” means that the upper wiring electrode 12 is formed so as not to cover the entire surface of the metal oxide layer 17. By forming the upper wiring electrode 12 in this way, in the subsequent oxidation step, oxidation is suppressed by the separation portion 14 and the upper wiring electrode 12 covering the portion that is oxidized because it is not covered by the upper wiring electrode 12. The portion can be the resistance change portion 13. Therefore, the upper wiring electrode 12 may be formed on the surface of the metal oxide layer 17 in consideration of the shape of the resistance change portion 13 necessary for the memory.

  In the example shown in FIGS. 3C and 4C, the upper wiring electrode 12 is formed so as to intersect the lower wiring electrode 11, but the upper wiring electrode 12 is not necessarily formed in this way. However, when the upper wiring electrode 12 is formed so as to intersect with the lower wiring electrode 11, the resistance change portion 13 can be formed at the intersection, and the formation of the memory cell array having the so-called XY arrangement is facilitated.

  Next, the surface of the metal oxide layer 17 on which the upper wiring electrode 12 is partially formed is placed in an oxidizing atmosphere, so that the metal oxide layer 17 is separated into the separation portion 14 and the resistance change portion 13 having different oxidation states. (FIG. 3D, FIG. 4D: oxidation process) as a resistance change layer 15 having a multilayer structure 18 including a lower wiring electrode 11, a resistance change layer 15, and an upper wiring electrode 12 in this order on a substrate 10. A mold memory 1 is formed.

  In the manufacturing method of the present invention, the metal oxide layer 17 sandwiched between the lower wiring electrode 11 and the upper wiring electrode 12 is formed in the stacking process instead of arranging the dot-shaped resistance change layer for each memory element. In the oxidation process, the resistance change portion 13 and the separation portion 14 are formed by using the coating of the surface of the metal oxide layer 17 by the upper wiring electrode 12, so that miniaturization of the element and high integration associated therewith can be achieved. The produced resistance change type memory can be manufactured with high productivity.

  The oxidizing atmosphere in the oxidation step (oxidation treatment) is not particularly limited, and may be an atmosphere including at least one selected from oxygen, ozone, oxygen plasma, and oxygen radicals, for example. Oxygen plasma and oxygen radicals can be generated by techniques such as electron cyclotron resonance (ECR) discharge, glow discharge, RF discharge, helicon, inductively coupled plasma (ICP), and the like.

  The method of the oxidation treatment is not particularly limited as long as the surface of the metal oxide layer 17 can be in contact with the oxidizing atmosphere. For example, the entire substrate 10, the lower wiring electrode 11, the metal oxide layer 17, and the upper wiring electrode 12 are oxidized. What is necessary is just to accommodate in the chamber in atmosphere and to leave. The standing time may be appropriately adjusted according to the oxidation strength of the oxidizing atmosphere, how much oxidation is necessary for the metal oxide layer 17, and the like. The temperature of the oxidation treatment can be freely set in the range of about 0 to 500 ° C.

  When the multilayer structure is formed in multiple stages on the substrate 10, the oxidation treatment is preferably performed every time one metal oxide layer 17 is stacked. That is, it is preferable to repeat the steps shown in FIGS. 3A to 3D (FIGS. 4A to 4D) by the number of stages depending on the number of stages required. This is because in the method in which the oxidation treatment is performed after forming two or more metal oxide layers 17, unevenness is likely to occur in the degree of oxidation between the metal oxide layers 17. Furthermore, depending on the type of metal oxide layer 17 and the oxidation method, it takes time to oxidize. Therefore, it is preferable to perform the oxidation step so as to process a large number of wafers at a time because the manufacturing process time can be shortened. This technique is particularly effective when performing oxidation at a low temperature.

  In the example shown in FIG. 4C, the upper wiring electrode 12 having the constricted portion 20 whose wiring width is narrowed is formed. In this case, due to the diffusion of oxygen during the oxidation treatment, the portion located below the constricted portion 20 in the metal oxide layer 17 can be used as the separation portion 14, and the separation portion 14 (high resistance increase) surrounding the resistance change portion 13. Part or high resistance altered part) becomes easier.

  When the upper wiring electrode 12 having the constricted portion 20 is formed, the shape, size, position in the wiring electrode, etc. of the constricted portion are not particularly limited.

  For example, the wiring width X1 of the constricted portion 20 is not particularly limited, but is 20 with respect to the wiring width X2 of the upper wiring electrode 12 formed on the metal oxide layer 17 on the portion that becomes the resistance change portion 13 by the oxidation treatment. A range of ˜80% is preferred. The wiring width X1 of the constricted portion 20 may be adjusted by the wiring width X2. For example, when the wiring width X2 is about 1 μm, the wiring width X2 is 20 from the viewpoint of stable formation of the upper wiring electrode 12 and sheet resistance. % Or more is preferable.

  Further, for example, the constricted portion 20 in the upper wiring electrode 12 may be formed in the central portion of the wiring electrode by providing symmetrical cuts from both sides of the wiring electrode as shown in FIGS. 4C and 5A. In this case, since the resistance change portion 13 can be formed at the position shown in FIG. 5A and the like, the driving voltage (current) to the resistance change portion 13 via the wiring electrode is determined from the symmetry of the arrangement pattern of the resistance changing portion 13 with respect to the wiring electrode. ) Can be applied more uniformly. Further, as shown in FIG. 5B, the constricted portions 20 may be alternately formed at both end portions of the wiring electrode by providing cuts alternately from both side surfaces of the wiring electrode. It is possible to increase the pitch of fine processing for forming the constricted portion 20 and to easily form the constricted portion 20. Further, as shown in FIG. 5C, the constricted portion 20 may be formed in the central portion of the wiring electrode by alternately providing cuts from both side surfaces of the wiring electrode. In this case, the cut portion is made large. Therefore, the formation of the wiring electrode is facilitated. In the example shown in FIGS. 5A to 5C, the shape of the cut provided in the wiring electrode is rectangular, but the shape is not particularly limited.

  In the manufacturing method of the present invention, the lower wiring electrode 11 having a constricted portion with a reduced wiring width may be formed on the substrate 10 in the stacking step. By using together with the formation of the upper wiring electrode 12 having the constricted portion 20, the electrical separation between the adjacent resistance change portions 13 can be more reliably performed.

  An example of forming the lower wiring electrode 11 having the constricted portion in the manufacturing method of the present invention is shown in FIGS. 6A to 6D.

  First, a plurality of lower wiring electrodes 11 having a constricted portion 21 are formed in a stripe shape on the substrate 10 (FIG. 6A). In the example shown in FIG. 6A, the insulating layer 16 is formed between the adjacent lower wiring electrodes 11. Such a structure has, for example, the insulating layer 16 formed after the insulating layer 16 is formed on the substrate 10. A groove portion for the lower wiring electrode 11 is provided in the groove portion, and after the lower wiring electrode 11 is buried in the groove portion, the surface thereof can be planarized by CMP. Alternatively, for example, after forming the plurality of lower wiring electrodes 11 in a stripe shape on the substrate 10, the insulating layer 16 is deposited on the entire surface including the substrate 10 and the lower wiring electrodes 11, and dry etching treatment, or It can also be formed by a combination of CMP and dry etching.

  Next, a metal oxide layer 17 is formed on the layer including the lower wiring electrode 11 (FIG. 6B).

  Next, the upper wiring electrode 12 is partially formed on the surface of the metal oxide layer 17 so as to sandwich the metal oxide layer 17 together with the lower wiring electrode 11 (FIG. 6C: above, laminating process). In the example shown in FIG. 6C, the upper wiring electrode 12 is formed so that the constricted portion 20 of the lower wiring electrode 11 and the upper wiring electrode 12 and the constricted portion 21 of the upper wiring electrode 12 and the lower wiring electrode 11 do not overlap. is doing.

  Next, the surface of the metal oxide layer 17 on which the upper wiring electrode 12 is partially formed is placed in an oxidizing atmosphere, so that the metal oxide layer 17 is separated into the separation portion 14 and the resistance change portion 13 having different oxidation states. A resistance change memory 1 in which a multilayer structure including a lower wiring electrode 11, a resistance change layer 15, and an upper wiring electrode 12 in this order is arranged on a substrate 10 as a resistance change layer 15 having a resistance change layer 15 (FIG. 6D: oxidation step). Form.

  When the upper wiring electrode 12 is formed on the surface of the metal oxide layer 17, the upper wiring electrode 12 may be formed so that the constricted portion 20 of the upper wiring electrode 12 and the lower wiring electrode 11 overlap. As shown in FIG. 7, the size of the resistance change portion 13 formed by the oxidation process can be further miniaturized, and the memory can be further highly integrated. In addition, the resistance value as the memory element can be set on the higher resistance side by miniaturizing the resistance change portion 13.

  The driving voltage or current may be applied to the resistance change unit 13 via the lower wiring electrode 11 and the upper wiring electrode 12. By applying the drive voltage (current), the resistance change unit 13, that is, the resistance change element (memory element) 2 changes from a state A having a relatively high resistance to a state B having a relatively low resistance, for example. However, the state after the change is maintained until the drive voltage (current) is applied again to the resistance change unit 13, and is changed again by the application of the drive voltage (current).

  As described above, the resistance change unit 13, that is, the element 2 can hold the electric resistance value until a new drive voltage (current) is applied, and thus a mechanism for detecting the state in the resistance change unit 13 (element 2). (Ie, a mechanism for detecting an electrical resistance value) and assigning a bit to each of the above states (for example, state A is “0” and state B is “1”), so that a nonvolatile resistance change memory (A memory array in which two or more resistance change units 13 (elements 2) are arranged) can be constructed. Moreover, such a change in state can be repeated at least twice or more, and a reliable nonvolatile random access memory can be constructed.

  The drive voltage or current does not necessarily have to be the same when the resistance change unit 13 is in the state A and when the resistance change unit 13 is in the state B. It may be different depending on the state. That is, the “drive voltage or current” in this specification may be a “voltage or current” that can change to another state different from the state when the resistance change unit 13 is in the state.

  The drive voltage or current is preferably pulsed (pulse voltage or current pulse). In this case, it is possible to reduce power consumption and improve switching efficiency in the constructed resistance change memory. The shape of the pulse is not particularly limited, and may be at least one shape selected from, for example, a sine wave shape, a rectangular wave shape, and a triangular wave shape. The width of the pulse may usually be in the range of several nanoseconds to several milliseconds.

  In order to more easily drive the memory, the shape of the pulse is preferably a triangular wave. In order to make the response of the resistance change unit 13 faster, the shape of the pulse is preferably rectangular, and in this case, a response of several nanoseconds to several microseconds can be achieved. In order to achieve simple driving, reduction of power consumption, and parallelization of fast response speed, the pulse shape is a sine wave or a trapezoidal wave with a square wave rising / falling part having an appropriate slope shape It is preferable that A sine wave or trapezoidal pulse is suitable when the response speed of the resistance change unit 13 is about several tens of nanoseconds to several hundreds of microseconds, and a triangular wave pulse has a response speed of the resistance change unit 13. It is suitable for the case of several tens of microseconds to several milliseconds.

  It is preferable to apply a voltage to the resistance change unit 13, and in this case, further miniaturization of the resistance change unit 13 and higher integration as a memory are easier. In the case of the resistance change unit 13 in which the above two states A and B exist, a potential difference application mechanism that generates a potential difference between the lower wiring electrode 11 and the upper wiring electrode 12 is used. By applying a bias voltage (positive bias voltage) that makes the potential of the upper wiring electrode 12 positive with respect to the potential, the resistance changing portion 13 is changed from the state A to the state B, and the lower portion By applying a bias voltage (negative bias voltage) that makes the potential of the upper wiring electrode 12 negative with respect to the potential of the wiring electrode 11 (that is, when changing from the state A to the state B) May change the resistance changing portion 13 from the state B to the state A by applying a voltage with the polarity reversed). For example, a pulse generator may be used as the potential difference applying mechanism.

For example, as shown in FIG. 8, the resistance change type memory according to the present invention is combined with a pass transistor group 41 so that the lower wiring electrode is a bit line (or word line) and the upper wiring electrode is a word line (or bit line). The memory array 51 having a so-called XY arrangement can be obtained. In the memory array 51, one bit line (B _n ) selected from two or more bit lines 42 and one word line (W _n ) selected from two or more word lines 43 are formed by pass transistors 41a and 41b. By selecting, the resistance change portion 13a (memory element 2a) located at the coordinates (B _n , W _n ) is selected, and data can be written, erased, and read.

In the memory array 51 shown in FIG. 8, a reference resistor group 44 is separately arranged. When reading data from the resistance change section, that is, when detecting the electric resistance value of the resistance change section, it is preferable to detect a difference from the reference resistance group 44, and in some cases, signal amplification is performed by a differential amplifier. Is preferred. In the memory array 51 shown in FIG. 8, the difference (V−V _REF ) between the voltage V in the selected resistance change unit 13a and the voltage V _REF in the reference resistance group 44 is read, so that the load resistance such as the wiring resistance is reduced. The influence can be minimized and the read sensitivity can be improved. As the reference resistance, at least one resistance change unit 13 (element 2) in the memory cell may be used.

  As shown in FIG. 9, the resistance change type memory according to the present invention is combined with a rectifying element 45 typified by a diode, more specifically, a rectifying element 45 is provided between the wiring electrode and the resistance changing portion 13. By arranging the memory array 52, a so-called XY arrangement in which the lower wiring electrode is a bit line (or word line) and the upper wiring electrode is a word line (or bit line) can be obtained.

  In the memory array 52 shown in FIG. 9, the resistance change unit 13 and the rectifier element 45 are electrically connected in series between the bit line 42 and the word line 43, but in this case, the rectifier element 45 is interposed. The wraparound resistance component can be reduced.

  The rectifying element 45 may be disposed between the lower wiring electrode and the resistance change unit 13, or may be disposed between the upper wiring electrode and the resistance change unit 13.

  The rectifying element 45 may be any of a Schottky type, a double Schottky type, a P-N junction type, a P-I-N junction type, and a varistor characteristic type, but an element having strong nonlinear characteristics, specifically, An element having a characteristic that the drive current changes nonlinearly according to the applied voltage is preferable, and the selectivity of the resistance change unit 13 in the memory array can be improved by such a rectifying element.

  The lower wiring electrode 11, the metal oxide layer 17, and the upper wiring electrode 12 may be formed by a general thin film forming process and a fine processing process by applying a semiconductor manufacturing process. For example, pulsed laser deposition (PLD), ion beam deposition (IBD), cluster ion beam, and various sputtering such as RF, DC, electron cycloton resonance (ECR), helicon, inductively coupled plasma (ICP), and counter target For example, a vapor deposition method such as molecular beam epitaxy (MBE) or an ion plating method may be used. In addition to these PVD (Physical Vapor Deposition) methods, CVD (Chemical Vapor Deposition) methods, MOCVD (Metal Organic Chemical Vapor Deposition) methods, plating methods, MOD (Metal Organic Decomposition) methods, or sol-gel methods may also be used. Good.

  For microfabrication of each layer, for example, physical processes such as ion milling, RIE (Reactive Ion Etching), and FIB (Focused Ion Beam) used in semiconductor manufacturing processes and magnetic device (such as magnetoresistive elements such as GMR and TMR) manufacturing processes. A combination of a photolithography technique using a target or chemical etching method, a stepper for forming a fine pattern, an EB (Electron Beam) method, or the like may be used. For planarizing the surface of each layer, for example, CMP (Chemical Mechanical Polishing), cluster-ion beam etching, or the like may be used.

  In addition, the microfabrication method and the planarization method for the insulating layer 16 and the like can be formed by the same method.

  Hereinafter, the present invention will be described in more detail with reference to examples. The present invention is not limited to the examples shown below.

(Example 1)
In Example 1, the resistance change type memory 1 shown in FIGS. 1 and 2 is manufactured based on the method shown in FIGS. 3A to 3D (FIGS. 4A to 4D), and the resistance change characteristics in the resistance change portion 13 are evaluated. did.

First, a Si substrate having a thermal oxide film (SiO ₂ film) formed on the surface is prepared as the substrate 10, and a Ta layer (thickness 5 nm) is formed as an adhesion layer on the Si substrate. A Pt layer (thickness: 100 nm) to be the lower wiring electrode 11 was formed thereon.

  Next, the Pt layer thus formed is finely processed by dry etching so that the wiring width L1 shown in FIG. 10 is 0.8 μm and the wiring interval L2 is 0.7 μm, and the five Pt layers are arranged in stripes. A lower wiring electrode 11 was obtained.

Next, an insulating layer 16 made of ozone TEOS (SiO ₂ ) was deposited on the entire surface including the lower wiring electrode 11 formed, and planarized by CMP and dry etching. At this time, planarization by CMP is performed until the surface of the lower wiring electrode 11 is slightly covered with the insulating layer 16, and then the surface of the lower wiring electrode 11 is exposed by dry etching, so that FIG. The state shown in 4A) was obtained. Such a dry etching process is called an etch back process, and this process reduces the effects of scratch damage to the surface of the lower wiring electrode 11 and the occurrence of global steps due to CMP.

Next, an iron oxide layer (thickness: 50 nm) was formed as the metal oxide layer 17 on the entire lower wiring electrode 11 and the insulating layer 16. The iron oxide layer is formed by using Fe ₃ O ₄ as a target and by an RF magnetron sputtering method in an argon-oxygen mixed atmosphere (argon / oxygen partial pressure ratio = 25) at a pressure of 0.1 to 10 Pa (typically 2 Pa). Below, the temperature of the Si substrate was set to 20 to 400 ° C. (typically 300 ° C.), and the applied power was set to RF 100 W. When the composition of the formed metal oxide layer 17 was separately confirmed by infrared (IR) spectroscopy, it was found to be composed of a phase composed of Fe ₃ O ₄ .

  Next, a Pt layer (thickness: 100 nm) to be the upper wiring electrode 12 was formed on the formed metal oxide layer 17. The Pt layer was formed by DC magnetron sputtering in an argon atmosphere with a pressure of 0.7 Pa, the temperature of the Si substrate being 27 ° C., and an applied power of 100 W.

  Next, in the formed Pt layer, the narrowed portion 20 shown in FIG. 10 has a wiring width X1 of 0.3 μm, a wiring width X2 of 1 μm, a notch length B1 constituting the narrowed portion 20 of 0.5 μm, and a wiring width. 5 which are finely processed by dry etching so as to have a length B2 (which can be said to be a distance between the constricted portions 20) of a portion where the constricted portion is not narrowed is 1 μm, and each of the constricted portions 20 is arranged in a stripe shape. The upper wiring electrode 12 (only one is shown in FIG. 10). The shape of the portion other than the constricted portion 20 in the upper wiring electrode 12 is a square of 1 μm × 1 μm. The upper wiring electrode 12 was formed so that the major axis direction thereof was orthogonal to the major axis direction of the lower wiring electrode 11.

  Next, the entire laminate of the substrate 10, the lower wiring electrode 11, the metal oxide layer 17 and the upper wiring electrode 12 is left for 1 minute in an oxygen atmosphere at 400 ° C. to partially oxidize the metal oxide layer 17. Thus, the resistance change layer 15 having the resistance change portion 13 and the separation portion 14 was formed, and the resistance change memory 1 (sample 1-1) shown in FIGS. Sample 1-1 is a 5 × 5 memory array. The heating to 400 ° C. was performed using a lamp heater in a quartz tube.

  Separately from the production of Sample 1-1, as shown in FIG. 11, a resistance change type memory 3 having a structure in which a part of the constricted portion 20 in the upper wiring electrode 12 of Sample 1-1 was deleted was produced. The production of the memory 3 basically followed the production of the sample 1-1 except that the shape of the upper wiring electrode 12 was changed. The distance D1 between the upper wiring electrodes 12a and 12b is 0.5 μm, similar to the length B1 of the sample 1-1.

  When the electrical resistance value between the upper wiring electrodes 12a and 12b before and after the oxidation treatment was measured, the electrical resistance value, which was about 2 kΩ before the oxidation treatment, became several tens of times, 50 kΩ, due to the oxidation treatment. It was confirmed that the resistance change portions 13a and 13b formed by the oxidation treatment can be electrically separated. It is considered that a separation portion 14 having an electric resistance value higher than that of the resistance change portion is formed between the resistance change portions 13a and 13b by oxidation treatment.

  Next, a pulse-like drive voltage shown in FIG. 12 was applied to the resistance change portion 13 of Sample 1-1 manufactured as described above, and the resistance change ratio was evaluated. The evaluation method is shown below.

Using a pulse generator, a pulse voltage of 1.5 V (positive bias voltage) (pulse width 10 ms) and −1.5 V (negative bias) between one upper wiring electrode and one lower wiring electrode in Sample 1-1. Voltage) pulse voltage (pulse width 10 ms) is alternately applied several times, and then the RESET voltage V _RS shown in FIG. 12 is 2 V (positive bias voltage) and the SET voltage V _SE is −2 V (negative bias voltage, magnitude 2 V). ), 0.01 V (positive bias voltage) was applied as the READ voltage V _RE (the pulse width of each voltage was 100 ns). After applying the SET voltage and the RESET voltage, the electric resistance value of the resistance changing unit 13 is calculated from the current value read by applying the READ voltage, and the maximum value of the calculated electric resistance value is R _Max and the minimum value is R _Min. , (R _Max −R _Min ) / R _Min The resistance change ratio of the resistance change portion 13 in the sample 1-1 was obtained from the equation represented by R _Min .

  As a result of the evaluation, the resistance change ratio of the resistance change portion 13 in the sample 1-1 is about 50 times, and the multilayer structure 18 of the lower wiring electrode 11, the resistance change portion 13 and the upper wiring electrode 12 is of the resistance change type. It was confirmed that it functions as a memory element. In addition, when the same evaluation was performed by selecting the wiring electrode to which the drive voltage was applied and changing the resistance change portion 13 to which the voltage was applied, the resistance change ratio of about 50 times was obtained in all the resistance change portions 13. It was.

  Separately from the above evaluation, when the retention characteristic of the resistance change ratio of the resistance change portion 13 in the sample 1-1, that is, the retention performance of the sample 1-1 was evaluated, it was at least 100 hours under the condition of 85 ° C. in a nitrogen atmosphere. Even after the above, 90% or more of the initial resistance change ratio was maintained.

  Separately from the preparation of Sample 1-1, Comparative Example Sample A-1 was prepared by the method shown in FIGS. 13A to 13C and evaluated in the same manner as Sample 1-1. Sample A-1 was prepared in the same manner as Sample 1-1 except that the upper wiring electrode 12 without the constricted portion 20 was formed and the oxidation treatment was not performed. FIG. 13A is a diagram illustrating a state in which the lower wiring electrodes 11 arranged in a stripe shape are formed on the substrate 10, and FIG. 13B illustrates a state in which the metal oxide layer 17 is formed on the formed lower wiring electrodes 11. FIG. 13C shows a state in which the upper wiring electrode 12 having no constricted portion 20 is formed on the formed metal oxide layer 17 so that the lower wiring electrode 11 and the upper wiring electrode 12 are orthogonal to each other. FIG. Except for the shape of the upper wiring electrode 12, each layer was formed in the same manner as in the sample 1-1. The wiring width of the upper wiring electrode 12 was 1 μm.

  When the resistance change ratio between the lower wiring electrode 11 and the upper wiring electrode 12 in Sample A-1 was evaluated in the same manner as the resistance change ratio of the resistance changing portion 13 in Sample 1-1, it was about 2-3 times. It was. The retention performance of Sample A-1 was also evaluated in the same manner as Sample 1-1. As a result, 50% of the initial resistance change ratio was reached until a maximum of 0.5 hours had elapsed under a nitrogen atmosphere at 85 ° C. Degradation to the following occurred. This indicates that the resistance change is held by electrically separating the adjacent resistance change portions 13.

  Further, the sample A-1 was oxidized under the same conditions as the sample 1-1, but neither the resistance change ratio nor the retention performance was improved. This is because when the wiring width of the wiring electrode is about 1 μm, the separation part 14 surrounding the resistance change part 13 could not be formed by not having the constricted part 20, that is, between adjacent resistance change parts 13. It is presumed that the cause was that it could not be separated.

  In Example 1, the oxidation treatment was performed under the condition of 400 ° C. in an oxygen atmosphere. Similar results were obtained in the range of room temperature to about 500 ° C. with respect to the treatment temperature. Further, it was found that it is preferable to increase the exposure time to the oxygen atmosphere at a temperature lower than 400 ° C. For example, when the treatment temperature is 100 ° C., it was found that the same characteristics as those of Sample 1-1 can be obtained by exposing to an oxygen atmosphere for about 6 hours.

(Example 2)
In Example 2, except that the resistance change type memory 1 shown in FIGS. 1 and 2 was oxidized by leaving the oxidation atmosphere at the time of oxidation treatment at an ozone atmosphere of 200 ° C. and leaving it in the atmosphere for about 30 minutes. It was produced in the same manner as Sample 1-1 (Sample 2-1 which is a 5 × 5 memory array). Values such as the wiring width X1 in sample 2-1 were all the same as in sample 1-1. The heating to 200 ° C. was performed by placing the sample on a hot plate.

  In addition to the fabrication of Sample 2-1, a resistor having a structure in which a part of the constricted portion 20 in the upper wiring electrode 12 of Sample 2-1 is removed as shown in FIG. The changeable memory 3 was produced. The distance D1 between the upper wiring electrodes 12a and 12b is 0.5 μm, similar to the length B1 of the sample 2-1.

  When the electrical resistance value between the upper wiring electrodes 12a and 12b before and after the oxidation treatment was measured, the electrical resistance value, which was about 2 kΩ before the oxidation treatment, became several hundred times as high as about 100 kΩ by the oxidation treatment. It was confirmed that the resistance change portions 13a and 13b formed by the oxidation treatment can be electrically separated. Further, by using ozone for the oxidation treatment instead of the oxygen of Example 1, the separation layer 14 can be reliably formed even under a temperature condition lower than 400 ° C. which is the oxidation treatment temperature in Example 1, and the adjacent resistance It was found that separation between the changing parts (elements) was possible.

  Similar results were found to be obtained when plasma oxygen (300 ° C., left for 30 minutes) or radical oxygen (300 ° C., left for 30 minutes) was used instead of ozone. Plasma oxygen was generated using an ashing device, and radical oxygen was generated using an ECR beam device.

  When the pulse-like drive voltage shown in FIG. 12 was applied to the resistance change portion 13 of the sample 2-1 produced as described above and the resistance change ratio was evaluated in the same manner as in Example 1, the resistance change ratio was about 50. It was twice.

  Separately, the retention characteristic of the resistance change ratio of the resistance change portion 13 in the sample 2-1, that is, the retention performance of the sample 2-1, was evaluated. At least 100 hours or more in a nitrogen atmosphere at 85 ° C. Even after the lapse, 80% or more of the initial resistance change ratio was maintained.

(Example 3)
In Example 3, when the upper wiring electrode 12 having the constricted portion 20 is used, the influence of the ratio of the wiring width X1 of the constricted portion 20 to the wiring width X2 of the wiring electrode on the formation of the resistance change type memory. Evaluated whether to give.

  In Example 3, the contact chain 4 shown in FIG. 14B was produced, and resistance change characteristics in the resistance change portion 13 were evaluated. The configuration of the contact chain 4 is basically the same as that of the resistance change type memory 1 shown in FIGS. 1 and 2 except that the shape and arrangement of the wiring electrodes are different, and its production is basically Sample 1-1. This was performed by the same method as in the production of.

First, a Si substrate having a thermal oxide film (SiO ₂ film) formed on the surface is prepared as the substrate 10, and a Ta layer (thickness 5 nm) is formed as an adhesion layer on the Si substrate. A Pt layer (thickness: 100 nm) to be the lower wiring electrode 11 was formed thereon.

  Next, the formed Pt layer is finely processed by dry etching so that the wiring width L1 shown in FIG. 14A is 0.8 μm and the wiring interval L3 is 0.7 μm, and is arranged linearly in the major axis direction. A rectangular lower wiring electrode 11 was obtained.

  Next, an insulating layer 16 made of ozone TEOS was deposited on the entire surface including the formed lower wiring electrode 11 and planarized by an etch back process to expose the surface of the lower wiring electrode 11.

  Next, an iron oxide layer (thickness 50 nm) was formed as the metal oxide layer 17, and a Pt layer (thickness 100 nm) to be the upper wiring electrode 12 was formed on the iron oxide layer.

  Next, in the formed Pt layer, the wiring width X2 shown in FIG. 14A is 1 μm, the wiring width X1 of the constricted portion 20 is in the range of 0.1 to 1 μm, and the length B1 of the cut forming the constricted portion 20 is 0.00. A dumbbell-shaped upper portion that is finely processed by dry etching so that the length B2 of the portion where the wiring width is not narrowed is 1 μm and has a constricted portion 20 and is linearly arranged in the major axis direction. The wiring electrode 12 was obtained. As shown in FIG. 14A, the central axis of the upper wiring electrode 12 coincides with the central axis of the lower wiring electrode 11 and faces each of a pair of adjacent lower wiring electrodes 11 with the constricted portion 20 interposed therebetween. The wiring width to be formed is formed so as to overlap with each of the pair of portions that are not narrowed.

  Next, the entire laminate of the substrate 10, the lower wiring electrode 11, the metal oxide layer 17 and the upper wiring electrode 12 is left for 1 minute in an oxygen atmosphere at 400 ° C. to partially oxidize the metal oxide layer 17. By doing so, the contact chain 4 (sample 3-1) shown in FIG. 14B was produced. The number of resistance change portions 13 formed in the overlapping portion of the lower wiring electrode 11 and the upper wiring electrode 12 (the overlapping portion viewed from the direction perpendicular to the main surface of the substrate 10) is 25, and heating to 400 ° C. is performed by quartz. A lamp heater was used in the tube.

  Before the oxidation treatment, the electric resistance value of the metal oxide layer 17 was uniform as a whole, so it did not function as a contact chain, but it was confirmed that the contact chain resistance increased rapidly due to the oxidation treatment. did it. It is considered that a part of the metal oxide layer 17 became the separation portion 14 due to the oxidation treatment and functioned as a contact chain.

Here, (X2−X1) / X2 is used as the ratio of the wiring width X1 to the wiring width X2, and the ratio is changed from 0% (that is, without the constricted portion 20: X1 = 1 μm) to 90% (that is, X1 is X2). 10%: X1 = 0.1 μm) was prepared, and the oxidation resistance change rate R / R _init of the contact chain resistance before and after the oxidation treatment in each sample R / R _init (R _init is the contact chain resistance before oxidation treatment, R The contact chain resistance after oxidation treatment was obtained, and the results shown in FIG. 15 were obtained.

As shown in FIG. 15, from (X2-X1) / X2 being about 20%, the increase in oxidation resistance change rate R / R _init due to the oxidation treatment became remarkable, and increased monotonously to about 80%. When (X2-X1) / X2 was 90%, the oxidation resistance change rate R / _Rinit increased rapidly, exceeding the measurement limit (value of R was 100 MΩ or more). R _init was about 1.2 kΩ for all samples.

Sample 3-1 was subjected to the same evaluation on sample 3-2 produced by changing only the oxidation treatment conditions (leaving at 400 ° C. for 2 minutes in an oxygen atmosphere). As in sample 3-1, From X2−X1) / X2 of about 20%, the increase in the oxidation resistance change rate R / R _init due to the oxidation treatment becomes remarkable, and increases monotonically to about 80% (R / R _init is about 10 ^{3 at} 80%). ). When (X2-X1) / X2 was 90%, the rate of change in oxidation resistance R / _Rinit increased rapidly, exceeding the measurement limit.

  Separately from the above evaluation, the oxygen content by the Auger spectrum (AES) is evaluated for the BB cross section shown in FIG. 14B of the sample 3-1, and the coating with the upper wiring electrode 12 is used to oxidize the metal oxide layer 17. It was evaluated whether it would have an impact. The evaluation results are shown in FIG. AES can increase the spatial resolution by narrowing the electron beam irradiated to the sample, and has a spatial resolution of micron size or submicron size.

  In FIG. 16, the end of the upper wiring electrode 12 is defined as a reference (0), and the overlap length is positive from the reference in the direction of the central axis of the upper wiring electrode 12 (if the overlap length is positive, the upper wiring electrode And plots the relative change in the amount of oxygen with respect to the overlap length of 0.5 μm (corresponding to the position of the central axis of the upper wiring electrode 12 where the wiring width X2 is 1 μm). ing. The relative change in the oxygen amount is shown as the change amount of the oxygen amount after the oxidation treatment with respect to the reference value with the oxygen amount before the oxidation treatment as a reference value. In addition, about the part coat | covered with the upper wiring electrode 12, evaluation by AES was performed using sputter etching to a depth direction together.

  As a result of the evaluation, as shown in FIG. 16, the degree of oxidation varies depending on the overlap length, that is, the coating of the upper wiring electrode 12, and the degree of oxidation from the metal oxide layer 17 by the manufacturing method of the present invention. It was confirmed that the resistance change portion 13 and the separation portion 14 having different values can be formed.

Example 4
In Example 4, the resistance change type memory 1 (shown in FIGS. 1 and 2) is the same as Sample 1-1 except that copper oxide or nickel oxide is used as the metal oxide layer 17 instead of iron oxide. Sample 4-1 using copper oxide and sample 4-2) using nickel oxide were prepared. Both Samples 4-1 and 4-2 were made into 5 × 5 memory arrays as in Sample 1-1.

Formation of the copper oxide layer (thickness: 50 nm) in Sample 4-1 is an argon-oxygen mixed atmosphere at a pressure of 0.1 to 10 Pa (typically 2 Pa) by RF magnetron sputtering using Cu ₂ O as a target. Under (Argon / oxygen partial pressure ratio = 8), the temperature of the Si substrate was set to 20 to 400 ° C. (typically 300 ° C.), and the applied power was set to RF 100 W. When the composition of the formed metal oxide layer 17 was separately confirmed by Auger spectroscopy, it was CuO _0.7 .

  In addition to the fabrication of Sample 4-1, a resistor having a structure in which a part of the constricted portion 20 in the upper wiring electrode 12 of Sample 4-1 is removed as shown in FIG. The changeable memory 3 was produced. A distance D1 between the upper wiring electrodes 12a and 12b is 0.5 μm.

  When the electrical resistance value between the upper wiring electrodes 12a and 12b before and after the oxidation treatment was measured, the electrical resistance value that was about 20 kΩ before the oxidation treatment was increased to about 800 kΩ and several tens of times by the oxidation treatment. It was confirmed that the resistance change portions 13a and 13b formed by the oxidation treatment can be electrically separated.

As in Example 1, the pulse-like drive voltage shown in FIG. 12 (however, the pulse width is 10 μs) is applied to the resistance change portion 13 of the sample 4-1 produced as described above, and the resistance change ratio thereof. Was evaluated to be about 10 ³ times.

  Separately from this, the retention characteristic of the resistance change ratio of the resistance change portion 13 in the sample 4-1, that is, the retention performance of the sample 4-1, was evaluated. At least 10 hours or more in a nitrogen atmosphere at 85 ° C. Even after the lapse, 90% or more of the initial resistance change ratio was maintained.

  Separately from the production of Sample 4-1, Comparative Sample B-1 was produced in the same manner as Sample A-1, which is a Comparative Sample of Example 1, and the same evaluation as Sample 4-1 was performed. Sample B-1 was prepared in the same manner as Sample 4-1, except that the upper wiring electrode 12 without the constricted portion 20 was formed and the oxidation treatment was not performed.

  When the resistance change ratio between the lower wiring electrode 11 and the upper wiring electrode 12 in Sample B-1 was evaluated in the same manner as the resistance change ratio of the resistance changing portion 13 in Sample 4-1, it was about 10 times. The retention performance of Sample B-1 was also evaluated in the same manner as Sample 4-1. As a result, 50% of the initial resistance change ratio was reached by 0.5 hours at the maximum under the condition of 85 ° C. in a nitrogen atmosphere. Degradation to the following occurred.

Formation of the nickel oxide layer (thickness: 50 nm) in Sample 4-2 was performed using an RF magnetron sputtering method using Ni as a target and an argon-oxygen mixed atmosphere (argon) at a pressure of 0.1 to 10 Pa (typically 2 Pa). / Oxygen partial pressure ratio = 10), the temperature of the Si substrate was set to 20 to 400 ° C. (typically 300 ° C.), and the applied power was RF 100 W. When the composition of the formed metal oxide layer 17 was separately confirmed by Auger spectroscopy, it was NiO _0.8 .

  In addition to the fabrication of Sample 4-2, a resistor having a structure in which a part of the constricted portion 20 in the upper wiring electrode 12 of Sample 4-2 is deleted as shown in FIG. The changeable memory 3 was produced. A distance D1 between the upper wiring electrodes 12a and 12b is 0.5 μm.

  When the electrical resistance value between the upper wiring electrodes 12a and 12b before and after the oxidation treatment was measured, the electrical resistance value, which was about 10 kΩ before the oxidation treatment, became several tens of times as high as about 500 kΩ by the oxidation treatment. It was confirmed that the resistance change portions 13a and 13b formed by the oxidation treatment can be electrically separated.

As in Example 1, the pulse-like drive voltage shown in FIG. 12 (however, the pulse width is 10 μs) is applied to the resistance change portion 13 of the sample 4-2 manufactured as described above, and the resistance change ratio. Was evaluated to be about 10 ³ times.

  Separately from this, the retention characteristic of the resistance change ratio of the resistance change portion 13 in the sample 4-2, that is, the retention performance of the sample 4-2 was evaluated, and at least 10 hours or more in a nitrogen atmosphere at 85 ° C. Even after the lapse, 90% or more of the initial resistance change ratio was maintained.

  Separately from the preparation of Sample 4-2, Comparative Sample B-2 was prepared in the same manner as Sample A-1, which is a comparative sample of Example 1, and the same evaluation as Sample 4-2 was performed. Sample B-2 was prepared in the same manner as Sample 4-2, except that the upper wiring electrode 12 without the constricted portion 20 was formed and the oxidation treatment was not performed.

  When the resistance change ratio between the lower wiring electrode 11 and the upper wiring electrode 12 in Sample B-2 was evaluated in the same manner as the resistance change ratio of the resistance changing portion 13 in Sample 4-2, it was about 10 times. The retention performance of Sample B-2 was also evaluated in the same manner as Sample 4-2. As a result, 50% of the initial resistance change ratio was reached by 0.5 hours at the maximum in a nitrogen atmosphere and at 85 ° C. Degradation to the following occurred.

(Example 5)
In Example 5, the variable resistance type in which the multilayer structure 18 including the lower wiring electrode 11, the resistance change layer 15, and the upper wiring electrode 12 in the sample 1-1 manufactured in Example 1 is arranged on the substrate 10 in three stages. A memory (Sample 5-1) was produced.

  Sample 5-1 was manufactured as described below after a resistance change type memory similar to that of Sample 1-1 was formed as the first-stage multilayer structure 18a (FIG. 17A).

  An insulating layer 16 made of ozone TEOS was deposited on the entire surface including the upper wiring electrode 12 formed, and planarized by an etch back process to expose the surface of the upper wiring electrode 12.

  Next, an iron oxide layer (thickness: 50 nm) is formed as a metal oxide layer 17 on the first upper wiring electrode 12 as the second lower wiring electrode 11, and the iron oxide layer is formed on the iron oxide layer. A Pt layer (thickness: 100 nm) to be the second upper wiring electrode 12 was formed.

  Next, the Pt layer was finely processed in the same manner as the upper wiring electrode 12 in the first stage to form the upper wiring electrode 12 in the second stage. The second upper wiring electrode 12 was formed to be orthogonal to the first upper wiring electrode 12.

  Next, the whole was allowed to stand in an oxygen atmosphere at 400 ° C. for 1 minute, and the metal oxide layer 17 was partially oxidized to form a resistance change layer 15 to form a second-stage multilayer structure 18b (FIG. 17B). ).

  Next, the second-stage upper wiring electrode 12 was used as the third-stage lower wiring electrode 11, and the same process as described above was repeated to form the third-stage multilayer structure 18c as Sample 5-1 (FIG. 17C). ).

  When the pulse-like drive voltage shown in FIG. 12 was applied to the resistance change portion 13 of the sample 5-1 produced as described above and the resistance change ratio was evaluated in the same manner as in Example 1, the resistance change ratio was about 50. It was twice.

  Separately from this, when the retention characteristic of the resistance change ratio of the resistance change unit 13 in the sample 5-1, that is, the retention characteristic of the sample 5-1, was evaluated, it was at least 100 hours or more in a nitrogen atmosphere at 85 ° C. Even after the lapse, 60% or more of the initial resistance change ratio was maintained. This is superior to the retention characteristic of Comparative Sample A-1 in Example 1, and it was confirmed that a multistage resistance change memory can be constructed by the manufacturing method of the present invention.

(Example 6)
In Example 6, the resistance change type memory 1 shown in FIGS. 1 and 2 is replaced with an Ir layer (thickness 100 nm), a TiAlN layer (thickness 100 nm) or a TiN layer (thickness 100 nm) instead of the Pt layer as the upper wiring electrode 12. (Sample 6-1 using Ir, Sample 6-2 using TiAlN, Sample 6-3 using TiN). The values of the wiring widths X1, X2, etc. of the upper wiring electrode 12 in each sample were all the same as those of the sample 1-1.

  The Ir layer, TiAlN layer, or TiN layer was formed by DC magnetron sputtering in an argon atmosphere at a pressure of 0.7 Pa, the temperature of the Si substrate being 27 ° C., and an applied power of 100 W.

  In addition to the manufacture of Samples 6-1 to 6-3, the constricted portion 20 in each upper wiring electrode 12 of Samples 6-1 to 6-3 as shown in FIG. Three types of resistance change type memory 3 having a structure in which a part of the resistance change type memory 3 is deleted are manufactured.

  When the electrical resistance value between the upper wiring electrodes 12a and 12b before and after the oxidation process was measured for the memory 3, the electrical resistance value which was about 2 to 5 kΩ before the oxidation process was It has been confirmed that the resistance change portions 13a and 13b formed by the oxidation process can be electrically separated by passing through the process, which is several tens of times as high as about 500 kΩ.

  Next, similarly to Example 1, the pulse-like drive voltage shown in FIG. 12 is applied to the resistance change portions 13 of Samples 6-1 to 6-3 manufactured as described above, and the resistance change ratios are applied. Was about 50 times (Sample 6-1), about 75 times (Sample 6-2), and about 30 times (Sample 6-3). The evaluation results are summarized in Table 1 below.

  Separately from this, when the retention characteristic of the resistance change ratio of the resistance change portion 13 in Samples 6-1 to 6-3, that is, the retention performance of Samples 6-1 to 6-3 was evaluated, 85 ° C. in a nitrogen atmosphere. Under these conditions, 90% or more of the initial resistance change ratio was maintained even after at least 100 hours had elapsed.

  From these results, it was confirmed that the resistance change type memory of the present invention could be manufactured regardless of the material of the upper wiring electrode 12.

  As described above, the resistance change type memory according to the present invention has a structure capable of realizing element miniaturization while being excellent in productivity. Further, according to the manufacturing method of the present invention, such a resistance change type memory can be manufactured with high productivity.

  The resistance change type memory of the present invention can be applied to various electronic devices. Examples of the device include non-volatile memories used in information communication terminals, switching elements, sensors, image display devices, and the like. Can be considered.

It is sectional drawing which shows typically an example of the resistance change memory of this invention. It is the top view which looked at the resistance change type memory shown in FIG. 1 from the upper surface. It is process drawing which shows typically an example of the manufacturing method of the resistance change memory of this invention. It is process drawing which shows typically an example of the manufacturing method of the resistance change memory of this invention. It is process drawing which shows typically an example of the manufacturing method of the resistance change memory of this invention. It is process drawing which shows typically an example of the manufacturing method of the resistance change memory of this invention. It is process drawing which shows typically an example of the manufacturing method of the resistance change memory of this invention. It is process drawing which shows typically an example of the manufacturing method of the resistance change memory of this invention. It is process drawing which shows typically an example of the manufacturing method of the resistance change memory of this invention. It is process drawing which shows typically an example of the manufacturing method of the resistance change memory of this invention. It is a top view which shows typically an example of the upper wiring electrode in the resistance change memory of this invention. It is a top view which shows typically an example of the upper wiring electrode in the resistance change memory of this invention. It is a top view which shows typically an example of the upper wiring electrode in the resistance change memory of this invention. It is process drawing which shows typically an example of the manufacturing method of the resistance change memory of this invention. It is process drawing which shows typically an example of the manufacturing method of the resistance change memory of this invention. It is process drawing which shows typically an example of the manufacturing method of the resistance change memory of this invention. It is process drawing which shows typically an example of the manufacturing method of the resistance change memory of this invention. It is a top view which shows typically an example of the resistance change memory of this invention. It is a schematic diagram which shows an example of the structure as a memory array of the resistance change memory of this invention. It is a schematic diagram which shows an example of the structure as a memory array of the resistance change memory of this invention. It is a top view which shows typically the structure of the resistance change type memory sample of this invention produced in the Example. It is a top view which shows typically the structure of the resistance change type memory sample of this invention produced in the Example. In an Example, it is a schematic diagram which shows the drive voltage pattern applied to the resistance change type memory sample of this invention. It is process drawing which shows typically the manufacturing method of the conventional resistance change type memory sample produced in the Example. It is process drawing which shows typically the manufacturing method of the conventional resistance change type memory sample produced in the Example. It is process drawing which shows typically the manufacturing method of the conventional resistance change type memory sample produced in the Example. It is a top view which shows typically the structure of the contact chain produced in the Example. It is a top view which shows typically the structure of the contact chain produced in the Example. It is a figure which shows the relationship between ratio (X2-X1) / X2 and oxidation resistance change rate R / _Rinit evaluated in Example 3. FIG. It is a figure which shows the relationship between the overlap length evaluated in Example 3, and the relative change of the oxygen amount before and behind an oxidation process. It is process drawing which shows typically the manufacturing method of the resistance change type memory sample of this invention produced in the Example. It is process drawing which shows typically the manufacturing method of the resistance change type memory sample of this invention produced in the Example. It is process drawing which shows typically the manufacturing method of the resistance change type memory sample of this invention produced in the Example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Resistance change type memory 2, 2a Resistance change element (memory element)
3 Resistance change memory 4 Contact chain 10 Substrate 11 Lower wiring electrode 12, 12a, 12b Upper wiring electrode 13, 13a, 13b Resistance changing part 14 Separating part 15 Resistance changing layer 16 Insulating layer 17 Metal oxide layer 18, 18a, 18b 18c Multi-layer structure 20 Constricted portion (of upper wiring electrode) 21 Constricted portion of (lower wiring electrode) 41 Pass transistor group 41a, 41b Pass transistor 42 Bit line 43 Word line 44 Reference resistance group 45 Rectifier element 51 Memory array 52 Memory array

Claims (17)

A multilayer structure having a lower wiring electrode, an upper wiring electrode, and a resistance change layer sandwiched between the lower wiring electrode and the upper wiring electrode is disposed on the substrate,
The resistance change layer includes:
Joined to the lower wiring electrode and the upper wiring electrode, has two or more states having different electric resistance values, and is selected from the two or more states by applying a driving voltage or current through both the wiring electrodes A resistance change section that changes from one state to another,
An electrical resistance value higher than that of the resistance change portion, and a separation portion surrounding the resistance change portion, and
The resistance change portion and the separation portion are made of the same kind of metal oxides having different oxidation states,
A resistance change type memory in which a bit is assigned to the state in the resistance change unit. The lower wiring electrode and the upper wiring electrode intersect,
The resistance change memory according to claim 1, wherein the resistance change portion is arranged at an intersection of both the wiring electrodes.   The resistance change type memory according to claim 1, wherein at least one selected from the lower wiring electrode and the upper wiring electrode is arranged in a stripe shape.   The resistance change type memory according to claim 1, wherein the metal oxide is a transition metal oxide.   The resistance change type memory according to claim 1, wherein the metal oxide is at least one selected from iron oxide, nickel oxide, and copper oxide. The upper wiring electrode has a constricted portion with a reduced wiring width;
The resistance change type memory according to claim 1, wherein a portion of the resistance change layer located below the constricted portion is formed of the separation portion.   The resistance change type memory according to claim 6, wherein a wiring width of the constricted portion is in a range of 20 to 80% of a wiring width of the upper wiring electrode at a joint portion with the resistance changing portion.   The resistance change type memory according to claim 6, wherein the lower wiring electrode has a constricted portion whose wiring width is narrowed.   The resistance change type memory according to claim 1, wherein the multilayer structure is arranged in multiple stages on a substrate. A multilayer structure having a lower electrode, an upper electrode, and a resistance change layer sandwiched between the lower electrode and the upper electrode is disposed on the substrate,
The resistance change layer includes:
From one state that is joined to the lower electrode and the upper electrode, has two or more states having different electric resistance values, and is selected from the two or more states by applying a driving voltage or current through both the electrodes. A resistance change section that changes to another state;
An electrical resistance value higher than that of the resistance change portion, and a separation portion surrounding the resistance change portion, and
The resistance change element and the separation part are resistance change elements made of the same kind of metal oxides having different oxidation states. It is a manufacturing method of the resistance change type memory according to claim 1,
A stacking step of partially forming an upper wiring electrode on the surface of the metal oxide layer after sequentially forming a lower wiring electrode and a metal oxide layer on the substrate;
By placing the surface of the metal oxide layer partially covered with the upper wiring electrode in an oxidizing atmosphere, the resistance change layer having a separation portion and a resistance change portion having different oxidation states from each other. And an oxidation step
The metal oxide layer has two or more states having different electric resistance values, and is a layer that changes from one state selected from the two or more states to another state by application of a driving voltage or current. Manufacturing method of resistance change type memory.   The method of manufacturing a resistance change type memory according to claim 11, wherein in the stacking step, the upper wiring electrode is formed so as to intersect the lower wiring electrode.   12. The method of manufacturing a resistance change type memory according to claim 11, wherein in the stacking step, at least one selected from the lower wiring electrode and the upper wiring electrode is formed in a stripe shape.   12. The method of manufacturing a resistance change type memory according to claim 11, wherein in the stacking step, the upper wiring electrode having a constricted portion with a reduced wiring width is formed.   12. The method of manufacturing a resistance change type memory according to claim 11, wherein the oxidizing atmosphere in the oxidizing step is an atmosphere containing at least one selected from oxygen, ozone, oxygen plasma, and oxygen radicals.   The method of manufacturing a resistance change memory according to claim 11, wherein the metal oxide layer includes a transition metal oxide.   The method of manufacturing a resistance change memory according to claim 11, wherein the metal oxide layer has at least one selected from iron oxide, nickel oxide, and copper oxide.

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