JP2010177655A - Method for manufacturing back junction type solar cell - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an inexpensive method for manufacturing a back junction type solar cell having high pn electrode resolution, thin substrate correspondence, and low temperature manufacturing processes. <P>SOLUTION: One conductivity silicon region and its electrode are formed by combination of a low temperature sputter epitaxial deposition method and a shielding mask, and then, the another conductivity silicon region and its electrode are formed by self-aligning technique. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

The present invention relates to a back-junction solar cell in which a PN junction is formed on a surface opposite to a light incident surface, and a shielding mask is used when a region having a conductivity type or impurity concentration different from that of a substrate is formed on a silicon substrate. The present invention relates to a method for manufacturing a back junction solar cell that can reduce the manufacturing cost and improve the efficiency by substituting a conventional photolithography process or printing process by a sputter epitaxial deposition method.

First, the words used in this specification will be described. In this specification, in principle, a “shielding mask” is a sheet in which an opening is formed. In vacuum deposition such as sputtering or vapor deposition, a film patterned according to the shape of the opening is deposited. . “Vacuum deposition” refers to depositing a film by vapor deposition or sputtering at a vacuum pressure of 40 mTorr or less, preferably 10 mTorr or less.

In recent years, development of clean energy has been desired due to global environmental problems such as an increase in CO _{2 in} the atmosphere, and in particular, renewable energy using solar cells has been developed and put into practical use as a new energy source, and the path of development Is walking.

Currently, most of the solar cells that are industrially produced in large quantities use single crystal or polycrystalline silicon substrates. This is due to the relatively cheap silicon material, non-toxicity and high conversion efficiency. However, the power generation cost of solar cells is still higher than that of thermal power generation, which is a bottleneck in the spread of solar cells. In order to reduce the power generation cost, it is necessary to increase the power generation efficiency of the solar cell and at the same time reduce the manufacturing cost.

From the viewpoint of increasing power generation efficiency, a so-called back junction solar cell has been developed in which an electrode is not formed on the light receiving surface of a silicon substrate, but a pn junction is formed on the back surface of the silicon substrate. Since a back junction solar cell generally does not have an electrode on the light receiving surface, there is no loss due to the electrode, and a higher output can be obtained compared to a solar cell having an electrode on the light receiving surface of a conventional silicon substrate.

There exists patent document 1 which showed the manufacturing method of the back junction type solar cell by the printing method as a typical example of the manufacturing method of a back junction type solar cell. However, there are problems with the printing method, such as the precision of patterns and the alignment accuracy between multiple patterns.
JP 2007-088254 A

Generally, the minimum pattern that can be formed by printing is approximately 0.1 mm, and the alignment accuracy is 0.1 mm. Due to the limit of precision and accuracy, the distance between the p ⁺ type region and the n ⁺ type region formed on the back surface is about 0.5 mm when this alignment accuracy is assumed. However, if the interval between the pn electrodes is so long, the probability that carriers are recombined in the middle increases, and the conversion efficiency decreases. In order to increase the conversion efficiency, an FZ substrate having a long carrier diffusion distance (a substrate manufactured by a floating zone melting method) can be used, but this substrate is a conventional Cz substrate (Czochralski ( Compared with the substrate manufactured by the Czochralski method). Therefore, efficiency is improved, but the problem of high cost remains. In order to increase the efficiency of the conventional Cz substrate, it is necessary to devise a method for narrowing the interval between the pn comb electrodes.

Subsequently, from the viewpoint of lowering the manufacturing cost, the material used can be reduced by making the substrate thinner. However, if the substrate is made 150 μm or less, in the current electrode forming process by the screen printing method, the substrate is likely to be cracked, resulting in a decrease in yield and an increase in cost. In order to handle a substrate of 150 μm or less, a method of manufacturing a solar cell by vacuum deposition is desired for all processes.

In the conventional solar cell manufacturing process, the p ⁺ type silicon region and the n ⁺ type silicon region are formed using a thermal diffusion method close to 900 ° C. In this high-temperature process, there is a problem that stress due to heat is applied to the silicon substrate and the carrier lifetime is lowered, resulting in a reduction in efficiency.

Problems to be solved by the invention

Until now, there has been no method for manufacturing a back-junction solar cell that can realize high resolution of the pn comb-shaped electrode of the back-junction solar cell, support for substrate thinning, and low-temperature fabrication process at a low manufacturing cost.

An object of the present invention is to provide a low-cost and high-efficiency manufacturing method of a back-junction solar cell that does not use a photolithography process or a printing process by combining a low-temperature sputter epitaxial deposition method and a shielding mask.

Means for solving the problem

The present invention provides a method for manufacturing a back junction solar cell in which a first conductivity type silicon region, a second conductivity type silicon region, a first electrode, and a second electrode are formed on the back surface of the silicon substrate that is not the light receiving surface. At least one of the first conductivity type silicon region and the second conductivity type silicon region is formed using a sputter epitaxial deposition method.

Since the deposition temperature is 300 ° C. or lower in the sputter epitaxial deposition method (see Non-Patent Document 1), the junction formation temperature by the conventional diffusion method is lower by 600 ° C., and a long carrier lifetime can be maintained.

Electrochem. Solid-State Lett. , 12, p. H67 (2009).

As another feature of the present invention, the first conductivity type silicon region formed using the sputter epitaxial deposition method is a step of sputter epitaxial depositing the first conductivity type silicon region through a shielding mask fixed on a silicon substrate; And vacuum depositing the first electrode through a shielding mask fixed on the silicon substrate.

A method of manufacturing a solar cell in which at least one of the first conductivity type silicon region and the second conductivity type silicon region is formed by a sputter epitaxial deposition method is the first conductivity type silicon region through a shielding mask fixed on a silicon substrate. Sputter epitaxial depositing, vacuum depositing the first electrode through a shielding mask fixed on the silicon substrate, vacuum depositing an insulating film through the shielding mask fixed on the silicon substrate, shielding A step of removing the mask, a step of sputter epitaxially depositing a second conductivity type silicon region on the exposed silicon substrate, and a step of forming a second electrode on the second conductivity type silicon region. This is a method for manufacturing a solar cell.

A method of manufacturing a solar cell in which at least one of the first conductivity type silicon region and the second conductivity type silicon region is formed by a sputter epitaxial deposition method includes: an aluminum as a first electrode through a shielding mask fixed on a silicon substrate; A step of vacuum-depositing a film, a step of vacuum-depositing an insulating film through a shielding mask fixed on the silicon substrate, a step of removing the shielding mask, and a second conductivity type silicon region on the exposed silicon substrate. And a step of forming a second electrode on the second conductivity type silicon region, and p ⁺ as a first conductivity type silicon region at the interface between the aluminum film and the silicon substrate by heat treatment. And a step of forming a mold-type silicon region.

Also, instead of depositing the first electrode after sputter epitaxial growth of the first conductivity type silicon region, the aluminum film as the first electrode is vacuum deposited through a shielding mask fixed on the silicon substrate and then heat-treated. A method of forming a p ⁺ type region as a first conductivity type silicon region at the interface between the film and the silicon substrate may be employed.

The first electrode and the first electrode external connection electrode need to be in electrical contact. For this purpose, it is necessary to expose a part of the first electrode in the step of forming an insulating film on the first electrode. This is a step of vacuum-depositing an insulating film through a shielding mask fixed on the silicon substrate. The first shielding plate is formed by vacuum-depositing an insulating film through a first shielding plate that shields a part of the first electrode. The first electrode is exposed at the shielded portion.

In the step of sputter epitaxial depositing the second conductivity type silicon region on a part of the exposed silicon substrate, in order to avoid short circuit between the second conductivity type silicon region to be deposited and the exposed portion of the first electrode, This is done through a second shielding plate that can completely shield the exposed portion of the first electrode.

In the step of forming the second electrode on the second conductivity type silicon region, the electrode material is vacuum deposited through the third shield plate that completely shields the boundary of the second conductivity type silicon film formed by the second shield plate. As a result, the second electrode is formed on the second conductivity type silicon region, and at the same time, the external connection electrode of the first electrode is formed.

Further, a method for manufacturing a solar cell in which at least one of the first conductivity type silicon region and the second conductivity type silicon region is formed by a sputter epitaxial deposition method includes: a first conductivity type silicon through a shielding mask fixed on a silicon substrate; Sputter epitaxial depositing the region; vacuum depositing the first electrode through a shielding mask fixed on the silicon substrate; vacuum depositing an insulating film through the shielding mask fixed on the silicon substrate; Removing the shielding mask; vacuum depositing an aluminum film as a second electrode on the exposed silicon substrate; forming an external connection electrode of the first electrode; and heat-treating the aluminum film and the silicon substrate. This is a method for manufacturing a solar cell comprising a step of forming a p ⁺ type region as second conductivity type silicon at the interface.

Here again, the first electrode and the first electrode external connection electrode need to be in electrical contact. For this purpose, it is necessary to expose a part of the first electrode in the step of forming an insulating film on the first electrode. . This is a process of vacuum-depositing an insulating film through a shielding mask fixed on the silicon substrate. The insulating film is vacuum-deposited through a first shielding plate that shields a part of the first electrode.

In the step of vacuum depositing an aluminum film as a second electrode on a part of the exposed silicon substrate, the exposed portion of the first electrode is completely shielded in order to avoid a short circuit between the first electrode and the second electrode. Aluminum is vacuum deposited through the second shielding plate.

In the step of forming the external connection electrode of the first electrode, the electrode material is vacuum-deposited through the third shield plate that completely shields the boundary of the aluminum electrode formed by the second shield plate, thereby the first electrode external connection Simultaneously with the formation of the electrode, the second electrode external connection electrode is formed on the second electrode.

The shielding mask includes openings that extend linearly and are parallel to each other.

Since the shielding mask is provided with openings that extend linearly and are parallel to each other, fine wires having a diameter of 0.01 mm to 0.1 mm are arranged at intervals of 0.01 mm to 0.1 mm. A simple and cost-effective shielding mask is realized.

The electrode material is silver.

When depositing the insulating film on the first electrode, the insulating film needs to cover the front and side surfaces of the first electrode, so that the deposition pressure of the insulating film is higher than the deposition pressure of the first electrode. The insulating film is deposited slightly around the side of the opening of the shielding mask.

On the light receiving surface on the silicon substrate, it is necessary to process the unevenness and form an antireflection film. In order to make all the steps vacuum, in the present invention, the step of forming irregularities is performed by reactive ion etching, and the antireflection film is formed by sputter deposition or chemical vapor deposition.

Examples 1 to 3 are shown below as modes of the present invention. The difference between the first to third embodiments lies in the formation of one conductivity type silicon region. In the first embodiment, the first conductivity type silicon region and the second conductivity type silicon region are both formed by the sputter epitaxial deposition method. There is. In Example 2, the first conductivity type silicon region is formed by forming an aluminum electrode as the first electrode and then heat-treating to form a p ⁺ type region as the first conductivity type silicon region at the interface between the aluminum electrode and the silicon substrate. The n ⁺ type region as the second conductivity type silicon region is characterized by being formed by a sputter epitaxial deposition method. In Example 3, the n ⁺ -type region as the first conductivity type silicon region was formed by the sputter epitaxial deposition method, but the second conductivity type silicon region was heat-treated after forming the aluminum electrode as the second electrode. The p ⁺ type region as the second conductivity type silicon region is formed at the interface between the aluminum electrode and the silicon substrate.

First, as shown in FIG. 2A , a p-type (100) plane single crystal silicon substrate 1 is prepared. In this embodiment, a silicon substrate having a size of 2 cm × 2 cm was used. The silicon substrate 1 may be n-type. When the silicon substrate 1 is n-type, a pn junction is formed on the back surface by the p ⁺ layer on the back surface of the silicon substrate 1 and the n-type silicon substrate 1. The A substrate having a thickness of 220 μm was used.

Next, the surface of the silicon substrate 1 is mirror-etched with a hydrofluoric acid solution of HF: HNO ₃ : CH ₃ COOH = 3: 5: 3. Next, the silicon substrate is taken out, and the oxide film on the surface is removed with a hydrogen fluoride aqueous solution or the like. Here, in addition to the aqueous hydrogen fluoride solution, it can be removed in vacuum by active hydrogen generated by, for example, catalytic CVD.

Next, the shielding mask was put on the back surface opposite to the light receiving surface of the silicon substrate, and both were fixed so that the relative position between the shielding mask and the silicon substrate did not change. In the present embodiment, the distance between the shielding mask and the silicon substrate is in close contact, but in reality, a gap of 10 μm or less is generated due to the surface roughness of the shielding mask. FIG. 1A shows a shielding mask 210 used in this embodiment. The shielding mask has an opening 210a. In vacuum deposition, the shielding mask 210 is placed on one substrate, and a film having the same pattern as the opening 210a is deposited on the silicon substrate 100 on the one substrate. Therefore, the pattern of the opening of the shielding mask 210 has a pattern that becomes a finger portion of a general comb-shaped back electrode. In this embodiment, the openings 210a are linear and parallel to each other for ease of processing of the shielding mask 210. For example, a curved finger shape like the shielding mask 210 of FIG. It can also be used. Further, as shown in FIG. 1C, a thin line 250 can be provided to form the shielding mask 210. In this method, the high-definition shielding mask 210 can be easily made by densely stretching the thin wires 250 having a small cross-sectional diameter with a space therebetween.

The shielding mask used in this example has a shape as shown in FIG. 1A. The actual opening width of the opening 210a is 0.1 mm, the interval between the openings is 0.1 mm, and the length is 25 mm. Met.

FIGS. 2A to 2F and FIGS. 3A to 3E are schematic cross-sectional views of the silicon substrate 100 after each subsequent process and plan views viewed from the back surface opposite to the light receiving surface, respectively. It was shown to. 2A to 2E are cross-sectional views taken along line I-I shown in FIGS. 3A to 3E, respectively. However, the plan view corresponding to FIG. 2F is the same as FIG. Further, in the cross-sectional view of FIG. 2, the front surface as the light receiving surface is displayed downward and the back surface is displayed upward.

Subsequently, the silicon substrate 100 was introduced into a silicon deposition sputtering apparatus. This sputtering apparatus targeted p ⁺ type silicon having a resistivity of 0.001 Ωcm or less, and the target diameter was 75 mm. A DC power source was used as the power source, and the sputtering gas was Ar. The deposition conditions are a substrate temperature of 175 ° C., an Ar pressure of 2.5 mTorr, and a power supply power of 300 W. Under these conditions, 300 nm of p ⁺ type silicon was deposited on the back surface of the silicon substrate 100 through the shielding mask 210 as shown in FIGS. As a result, ap ⁺ region 110 was formed as the first conductivity type silicon region. Here, as shown in Non-Patent Document 1, since the sputtered film is epitaxially grown on the silicon substrate, the silicon substrate 100 and the p ⁺ region 110 are crystallographically continuous.

Next, the silicon substrate 100 is transferred to the thermal evaporation chamber, and under the condition of 1 mTorr or less, as shown in FIGS. 2B and 3B, the p-type electrode is the first electrode on the p ⁺ -type region 110. An aluminum film having a thickness of 120 was deposited to 200 nm.

Next, the first shielding plate 220 was overlapped on the shielding mask 210, and a part of each finger of the p-type electrode 120 was shielded by the first shielding plate 220. A region surrounded by a dotted line in FIG. Next, as the insulating film 130, a SiO ₂ film was deposited to 400 nm through the shielding mask 210 under the condition of 150 W by a pulsed DC reactive sputter deposition method (Non-patent Document 2). Since the deposition pressure is higher than the pressure which is deposited a ^{p +} -type region 110 and p electrode 120 in 2.5～10MTorr, deposited insulating film 130 side of the shielding mask openings 210a as shown in FIG. 2 (c) And deposited so as to completely enclose the p ⁺ -type region 110 and the p-electrode 120. Here, the portion of the p-type electrode 120 shielded by the first shielding plate 220 was exposed from the insulating film 130 as shown in FIG.
Norihan Sung, Master's thesis of Taiwan University of Science and Technology, Teaching Hafumasa, June 2008.

Subsequently, the shielding mask 210 and the first shielding plate 220 are removed from the silicon substrate 100, and the second shielding plate 230 that completely shields the area shielded by the first shielding plate 220 as shown in FIG. the n ⁺ -type region serving as a second conductivity type silicon region sputter deposition. The deposition conditions are the same as those for depositing the p ⁺ type silicon except that the target is changed to n ⁺ type silicon of 0.001 Ωcm or less. As shown in FIGS. 2D and 3D, the silicon deposited on the portion where the silicon substrate 100 is exposed is epitaxially grown to form an n ⁺ -type region 140a, which is deposited on the insulating film. The portion thus formed becomes an n ⁺ -type region 140b that is turned into amorphous silicon. However, the amorphous siliconized n ⁺ -type region 140b hardly affects the characteristics of the solar cell.

Subsequently, the second shielding plate 230 is removed from the silicon substrate 100, and the third shielding plate that completely shields the boundary of the n ⁺ type silicon film 140 formed by the second shielding plate 230 as shown in FIG. 240 was installed, and a silver film as an electrode material was sputter deposited. By this step, the n-type electrode 150 and the p-type electrode external connection electrode 160 as the second electrode are formed. Thus, the process on the back surface of the silicon substrate 100 is completed.

Next, regarding the formation of the concavo-convex structure 170 for preventing the reflection of the light receiving surface in FIG. 2F, it was formed by magnetron parallel plate type reactive ion etching using CF ₄ gas and O ₂ gas as raw materials. The power source power was 10 W, the CF ₄ : O ₂ flow ratio was 1: 1, and the etching pressure was 15 mTorr. As a result, a visible light reflectance of 2% or less was obtained.
Next, SiO ₂ was deposited by reactive sputtering to form an antireflection film 180. Although the deposited film thickness is not particularly limited, for example, the thickness can be 60 nm or more and 140 nm or less.

Finally, the sample was heat-treated in a tube furnace maintained at a temperature of 300 ° C. to 450 ° C. and flowing nitrogen containing about 5% of hydrogen.

And the characteristic of the back junction solar cell of Example 1 was evaluated with the solar simulator.

As a result, Jsc (short circuit current density) of the back junction solar cell of Example 1 is 38.2 mA / cm ² , Voc (open voltage) is 0.612 V, and F.I. F (fill factor) was 0.680 and Eff (conversion efficiency) was 15.7%.

Since the type, size, and pretreatment of the silicon substrate used are all the same as those in the first embodiment, description thereof is omitted. The shielding mask to be used is exactly the same as that of the first embodiment, and the process until the shielding mask is fixed to the silicon substrate is not changed at all, so that the description thereof is omitted.

FIGS. 4A to 5E and FIGS. 5A to 5D are a schematic cross-sectional view of the silicon substrate 100 after each subsequent process and a plan view viewed from the back surface opposite to the light receiving surface, respectively. It was shown to. 4A to 4D are cross-sectional views taken along the line I-I shown in FIGS. 5A to 5D. However, the plan view corresponding to FIG. 4E is the same as FIG. Further, in the cross-sectional view of FIG. 4, the front surface as the light receiving surface is displayed downward and the back surface is displayed upward.

After the shielding mask 210 is fixed to the silicon substrate 100, the silicon substrate 100 is transferred to the thermal evaporation chamber, and passes through the shielding mask 210 as shown in FIGS. 4A and 5A under the condition of 1 mTorr or less. The aluminum electrode which becomes the p-type electrode 120 as the first electrode was deposited to 500 nm.

Next, the first shielding plate 220 shown in the region surrounded by the dotted line in FIG. 5B is overlaid from above the shielding mask 210 so that a part of each finger of the p-type electrode 120 is shielded by the first shielding plate 220. did. Next, as the insulating film 130, a SiO ₂ film was deposited to 400 nm through the shielding mask 210 under the condition of 150 W by a pulsed DC reactive sputter deposition method (Non-patent Document 2). Since the deposition pressure is higher than the pressure at which the p-electrode 120 is deposited at 2.5 to 10 mTorr, the deposited insulating film 130 is on the side surface of the shielding mask opening 210a as shown in FIG. The p-type electrode 120 is deposited so as to completely surround the p-type electrode 120. Here, the portion of the p-type electrode 120 shielded by the first shielding plate 220 was exposed from the insulating film 130 as shown in FIG.

Subsequently, the shielding mask 210 and the first shielding plate 220 are removed from the silicon substrate 100, and through the second shielding plate 230 that completely shields the area shielded by the first shielding plate 220 as shown in FIG. An n ⁺ type region as a second conductivity type silicon region was sputter deposited. The sputtering apparatus used for sputter deposition in the n ⁺ region targeted n ⁺ type silicon having a resistivity of 0.001 Ωcm or less, and had a diameter of 75 mm. A DC power source was used as the power source, and the sputtering gas was Ar. The deposition conditions are a substrate temperature of 175 ° C., an Ar pressure of 2.5 mTorr, and a power supply power of 300 W. Here, as shown in FIGS. 4C and 5C, the silicon deposited on the portion where the silicon substrate 100 is exposed is epitaxially grown to form an n ⁺ -type region 140a. The portion deposited in the region becomes an n ⁺ -type region 140b that is turned into amorphous silicon. However, the amorphous siliconized n ⁺ -type region 140b hardly affects the characteristics of the solar cell.

Subsequently, the second shielding plate 230 is removed from the silicon substrate 100, and the third shielding plate that completely shields the boundary of the n ⁺ -type silicon film 140 formed by the second shielding plate 230 as shown in FIG. 240 was installed, and a silver film as an electrode material was sputter deposited. By this step, the n-type electrode 150 and the p-type electrode external connection electrode 160 as the second electrode are formed.

Next, the concavo-convex structure 170 for preventing reflection on the light receiving surface in FIG. The method used was a magnetron parallel plate type reactive ion etching using CF ₄ gas and O ₂ gas as raw materials. The power source power was 10 W, the CF ₄ : O ₂ flow ratio was 1: 1, and the etching pressure was 15 mTorr. As a result, a visible light reflectance of 2% or less was obtained.

Next, SiO ₂ was deposited by reactive sputtering to form an antireflection film 180. Although the deposited film thickness is not particularly limited, for example, the thickness can be 60 nm or more and 140 nm or less.

Next, the sample was put in an oven at 550 ° C. to 650 ° C. and heat-treated to form a p ⁺ type region as the first conductivity type silicon at the interface between the aluminum electrode 120 as the p type electrode and the silicon substrate 100. This heat treatment step may be performed after the steps of FIGS. 4C to 4D. Further, it may be performed after the steps of FIGS. 4A to 4B, but the thin silicon oxide film formed on the surface hinders the sputter epitaxial deposition of FIG. It is necessary to remove the oxide film with a hydrofluoric acid solution or hydrogen plasma.

Finally, the sample was heat-treated in a tubular furnace maintained at a temperature of 300 ° C. to 450 ° C. and flowing nitrogen containing about 5% of hydrogen.

And the characteristic of the back junction solar cell of Example 2 was evaluated with the solar simulator.

As a result, Jsc (short circuit current density) of the back junction solar cell of Example 2 is 38.0 mA / cm ² , Voc (open voltage) is 0.62 V, and F.I. F (fill factor) was 0.71, and Eff (conversion efficiency) was 16.5%.

Since the type, size, and pretreatment of the silicon substrate used are all the same as those in the first embodiment, description thereof is omitted. The shielding mask to be used is exactly the same as that of the first embodiment, and the process until the shielding mask is fixed to the silicon substrate is not changed at all, so that the description thereof is omitted.

FIGS. 6A to 6F and FIGS. 7A to 7E are schematic cross-sectional views of the silicon substrate 100 after each subsequent process and plan views viewed from the back surface opposite to the light receiving surface, respectively. It was shown to. 6A to 6E are cross-sectional views taken along line I-1 shown in FIGS. 7A to 7E, respectively. However, the plan view corresponding to FIG. 6F is the same as FIG. In the cross-sectional view of FIG. 6, the front surface as the light receiving surface is displayed downward and the back surface is displayed upward.

Subsequently, the silicon substrate 100 was introduced into a silicon deposition sputtering apparatus. This sputtering apparatus targeted n ⁺ type silicon having a resistivity of 0.001 Ωcm or less, and the diameter of the target was 75 mm. A DC power source was used as the power source, and the sputtering gas was Ar. The deposition conditions are a substrate temperature of 175 ° C., an Ar pressure of 2.5 mTorr, and a power supply power of 300 W. Under these conditions, as shown in FIGS. 6A and 7A, 300 nm of n ⁺ -type silicon was deposited on the back surface of the silicon substrate 100 through the shielding mask 210. As a result, an n ⁺ type region 140a was formed as the first conductivity type silicon region. Here, as shown in Non-Patent Document 1, since the sputtered film is epitaxially grown on the silicon substrate, the silicon substrate 100 and the n ⁺ region 140a are crystallographically continuous.

Next, the silicon substrate 100 is transported to the sputtering apparatus, and under the condition of 2 mTorr or less, as shown in FIGS. 6B and 7B, the n-type electrode 150 is the first electrode on the n ⁺ -type region 140a. A silver electrode was deposited to 200 nm through the shielding mask 210.

Next, a first shielding plate 220 surrounded by a dotted line in FIG. 7C is overlapped on the shielding mask 210 so that a part of each finger of the n-type electrode 150 is shielded by the first shielding plate 220. Then pulsed DC reactive sputtering deposition of the SiO ₂ film as the insulating film 130 under the condition of 150W by (non-patent document 2), and 400nm deposited through a shielding mask 210. Since the deposition pressure is higher than the pressure at which the n ⁺ -type region 140a and the n-electrode 150 are deposited at 2.5 to 10 mTorr, the deposited insulating film 130 has a side surface of the shielding mask opening 210a as shown in FIG. The n ⁺ -type region 140a and the n-electrode 150 are deposited so as to completely surround the n ⁺ -type region 140a. Here, the portion of the n-type electrode 150 shielded by the first shielding plate 220 was exposed from the insulating film 130 as shown in FIG.

Subsequently, the shielding mask 210 and the first shielding plate 220 are removed from the silicon substrate 100, and the region shielded by the first shielding plate 220 is completely shielded as shown in FIGS. 6 (d) and 7 (d). Through the two shielding plates 230, an aluminum film serving as the p-type electrode 120 was deposited to a thickness of 200 nm as the second electrode. The aluminum film was formed by thermal evaporation.

Subsequently, the second shielding plate 230 is removed from the silicon substrate 100, and a third shielding plate 240 that completely shields the boundary of the p-type electrode 120 formed by the second shielding plate 230 as shown in FIG. Then, a silver film as an electrode material was deposited by sputtering. By this step, the n-type electrode external connection electrode 160 of the n-type electrode 150 and the p-type electrode external connection electrode 190 of the p-type electrode 120 are formed simultaneously.

Next, regarding the formation of the concavo-convex structure 170 for preventing the reflection of the light receiving surface in FIG. 6 (f), it was formed by magnetron parallel plate type reactive ion etching using CF ₄ gas and O ₂ gas as raw materials. The power source power was 10 W, the CF ₄ : O ₂ flow ratio was 1: 1, and the etching pressure was 15 mTorr. As a result, a visible light reflectance of 2% or less was obtained.
Next, SiO ₂ was deposited by reactive sputtering to form an antireflection film 180. Although the deposited film thickness is not particularly limited, for example, the thickness can be 60 nm or more and 140 nm or less.

Then cured, or placed in the sample to 550 ° C. to 650 ° C. oven, as shown in FIG. 6 (f), p ⁺ -type region serving as a second conductivity type silicon at the interface of the aluminum p-type electrode 120 and the silicon substrate 100 Formed. This heat treatment step may be performed after the step shown in FIG. 6D or after the step shown in FIG.

Finally, the sample was heat-treated in a tube furnace maintained at a temperature of 300 ° C. to 450 ° C. and flowing nitrogen containing about 5% of hydrogen.

And the characteristic of the back junction type solar cell of Example 3 was evaluated with the solar simulator.

As a result, Jsc (short circuit current density) of the back junction solar cell of Example 3 is 38.0 mA / cm ² , Voc (open voltage) is 0.63 V, and F.I. F (fill factor) was 0.72, and Eff (conversion efficiency) was 16.8%.

The technical scope of the present invention is not limited to the above-described embodiment, and various changes can be made without departing from the spirit of the present invention.

The invention's effect

The present invention provides a high-resolution pn electrode for a back-junction solar cell, which has been a problem, and a low-temperature manufacturing process by forming a low-temperature junction by a sputter epitaxial deposition method and forming a one-conductivity type region by a shielding mask. By simultaneously solving the thinning of the substrate by the all vacuum thin film process, a solar cell manufacturing method with high power generation efficiency and low cost was realized.

(A)-(c) is a typical top view explaining the example of the pattern of the shielding mask in this invention. In particular, (a) is a schematic plan view of the shielding mask used in the examples. (A)-(f) is typical sectional drawing which shows an example of the manufacturing process of the manufacturing method of the back junction type solar cell of this invention. (A)-(e) is typical top view which shows an example of the manufacturing process of the manufacturing method of the back junction type solar cell of this invention, and respond | corresponds to the cross-sectional structure shown to Fig.2 (a)-(e), respectively. To do. (A)-(e) is typical sectional drawing which shows an example of the manufacturing process of the manufacturing method of the back junction type solar cell of this invention. (A)-(d) is typical top view which shows an example of the manufacturing process of the manufacturing method of the back junction type solar cell of this invention, and respond | corresponds to the cross-sectional structure shown to Fig.2 (a)-(d), respectively. To do. (A)-(f) is typical sectional drawing which shows an example of the manufacturing process of the manufacturing method of the back junction type solar cell of this invention. (A)-(e) is typical top view which shows an example of the manufacturing process of the manufacturing method of the back junction type solar cell of this invention, and respond | corresponds to the cross-sectional structure shown to Fig.2 (a)-(e), respectively. To do.

100 silicon substrate,
110 p ⁺ type region 120 p type electrode 130 Insulating film 140 n ⁺ silicon film 140a Epitaxially grown n ⁺ type region 140b Amorphized n ⁺ type region 150 n type electrode 160 p type electrode external connection electrode 170 Surface uneven structure 180 Antireflection Film 210 Shielding Mask 210a Shielding Mask Opening 220 First Shielding Plate 230 Second Shielding Plate 240 Third Shielding Plate 250 Fine Wire

Claims (16)

In the method of manufacturing a back junction solar cell in which a first conductivity type silicon region, a second conductivity type silicon region, a first electrode, and a second electrode are formed on the back surface of the silicon substrate that is not the light receiving surface, the first conductivity type A method for manufacturing a solar cell, comprising forming at least one of a type silicon region and the second conductivity type silicon region by a sputter epitaxial deposition method. The first conductivity type silicon region formed using the sputter epitaxial deposition method includes a step of performing sputter epitaxial deposition of the first conductivity type silicon region through a shielding mask fixed on the silicon substrate, and the first conductivity type silicon region fixed on the silicon substrate. And vacuum depositing the first electrode through the shielding mask. The method for manufacturing a solar cell according to claim 1. A method of manufacturing a solar cell in which at least one of the first conductivity type silicon region and the second conductivity type silicon region is formed by a sputter epitaxial deposition method is the first conductivity type silicon region through a shielding mask fixed on a silicon substrate. Sputter epitaxial depositing, vacuum depositing a first electrode through a shielding mask fixed on the silicon substrate, vacuum depositing an insulating film through a shielding mask fixed on the silicon substrate, Removing the shielding mask, sputter epitaxially depositing a second conductivity type silicon region on the exposed silicon substrate, and forming a second electrode on the second conductivity type silicon region. The manufacturing method of the solar cell of Claim 1 characterized by these. A method of manufacturing a solar cell in which at least one of the first conductivity type silicon region and the second conductivity type silicon region is formed by a sputter epitaxial deposition method includes: an aluminum as a first electrode through a shielding mask fixed on a silicon substrate; A step of vacuum-depositing a film, a step of vacuum-depositing an insulating film through a shielding mask fixed on the silicon substrate, a step of removing the shielding mask, and a second conductivity type silicon region on the exposed silicon substrate. And a step of forming a second electrode on the second conductivity type silicon region, and p ⁺ as a first conductivity type silicon region at the interface between the aluminum film and the silicon substrate by heat treatment. Forming the mold region, and the method for manufacturing a solar cell according to claim 1. 4. The step of vacuum-depositing an insulating film through a shielding mask fixed on the silicon substrate is characterized in that the insulating film is vacuum-deposited through a first shielding plate that shields a part of the first electrode. Or the manufacturing method of the solar cell of Claim 4. The step of sputter epitaxially depositing a second conductivity type silicon region on a part of the exposed silicon substrate is performed through a second shielding plate that completely shields the exposed portion of the first electrode. The manufacturing method of the solar cell of Claim 3 to 5. The step of forming the second electrode on the second conductivity type silicon region includes the step of forming an electrode material through a third shield plate that completely shields the boundary of the second conductivity type silicon film formed by the second shield plate. The solar cell manufacturing method according to claim 3, wherein the second electrode is formed on the second conductivity type silicon region and the external connection electrode of the first electrode is simultaneously formed by vacuum deposition. Method. A method of manufacturing a solar cell in which at least one of the first conductivity type silicon region and the second conductivity type silicon region is formed by a sputter epitaxial deposition method includes: a first conductivity type silicon region through a shielding mask fixed on a silicon substrate; Sputter epitaxial depositing, vacuum depositing a first electrode through a shielding mask fixed on the silicon substrate, vacuum depositing an insulating film through a shielding mask fixed on the silicon substrate, Removing the shielding mask; vacuum depositing an aluminum film as a second electrode on the exposed silicon substrate; forming an external connection electrode on the second electrode; and heat treating the aluminum film. And a step of forming a p ⁺ type region as the second conductivity type silicon at the interface of the silicon substrate. The manufacturing method of the solar cell of Claim 1. 9. The step of vacuum-depositing an insulating film through a shielding mask fixed on the silicon substrate comprises vacuum-depositing the insulating film through a first shielding plate that shields a part of the first electrode. The manufacturing method of the solar cell of description. The step of vacuum depositing an aluminum film as a second electrode on the exposed silicon substrate is characterized in that aluminum is vacuum deposited through a second shielding plate that completely shields the exposed portion of the first electrode. The method for manufacturing a solar cell according to claim 8. The step of forming an external connection electrode on the second electrode includes vacuum deposition of an electrode material through a third shielding plate that completely shields the boundary of the aluminum film formed by the second shielding plate, The method for manufacturing a solar cell according to claim 8, wherein the external connection electrode is formed on the first electrode simultaneously with the formation of the external connection electrode on the two electrodes. The said shielding mask is provided with the opening part extended linearly and mutually parallel, The manufacturing method of the solar cell of Claim 2 to 4 or Claim 8 characterized by the above-mentioned. The solar cell according to claim 12, wherein the shielding mask is a shielding mask in which thin wires having a diameter of 0.01 mm to 0.1 mm are arranged at intervals of 0.01 mm to 0.1 mm. Production method. The method for manufacturing a solar cell according to claim 7 or 11, wherein the electrode material is silver. The solar cell according to claim 3, wherein the first electrode and the insulating film have a deposition pressure of the insulating film higher than a deposition pressure of the first electrode. Production method. 5. The light-receiving surface on the silicon substrate is formed with a step of forming irregularities by a reactive ion etching method, and an antireflection film is formed by a sputter deposition method or a chemical vapor deposition method. The manufacturing method of the solar cell of Claim 8.

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