JP2010177285A - Solid-state imaging device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging device suppressing increase of gate length of a storage gate even when the arrangement pitch of pixels for photoelectric conversion is reduced. <P>SOLUTION: Two pixels arranged adjacent to each other are used as one pixel pair 1, and all pixels arranged in one line are divided into (n) sets of pixel pairs 1. When it is assumed that the pixels included in one set of the pixel pair 1 are called a pixel 11 and a pixel 12, a shift gate 2 transfers charge stored in the pixel 12 to the pixel 11; a storage gate 3 stores the charge transferred from the pixel 11; a storage gate 4 stores charge transferred from the storage gate 3; a shift gate 5 transfers the charge stored in the storage gate 4 to a CCD register 6; and the CCD register 6 transfers charge transferred by the shift gate 5 in the same direction as that of the arrangement direction of the pixels. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device.

  In a CCD line sensor in which pixel portions that accumulate charges corresponding to the intensity of incident light are arranged in a row, an accumulation gate and a shift gate are arranged corresponding to each pixel portion.

  The charges accumulated in the pixel portion are sequentially transferred to the accumulation gate and the shift gate, and then transferred from the shift gate to the CCD register (see, for example, Patent Document 1).

  In order to increase the resolution of such a CCD line sensor, it is necessary to narrow the arrangement pitch of the pixel portions.

  Conventionally, the pixel arrangement pitch has been reduced in response to the narrowing of the pixel portion arrangement. At this time, the storage gate length is lengthened so that the gate area of the gate becomes an area capable of holding a necessary charge amount. In this case, in order to move the charge in the storage gate quickly, it is necessary to form a potential gradient in the storage gate in which the potential increases from the pixel portion toward the shift gate.

  When the storage gate length is increased, the device area is correspondingly increased, the number of devices that can be manufactured from one wafer is reduced, and the manufacturing cost is increased. Further, in terms of the sensor characteristics, the electron transfer path becomes longer, and the operation speed of the sensor becomes slower.

Regarding the operation speed, conventionally, the operation speed is increased by increasing the potential gradient in the storage gate. However, if the gate length of the storage gate is increased, it is necessary to make the impurity concentration a multi-step, and accordingly, the number of impurity implantations is increased and the manufacturing cost is increased. It also becomes difficult to secure a manufacturing margin. For the above reasons, in the CCD line sensor, extending the storage gate length causes problems such as an increase in manufacturing cost and deterioration of transfer characteristics. In order to solve these problems, a shift gate is formed in each pixel, and a single accumulation gate is shared by a plurality of pixels, thereby extending the accumulation gate width and suppressing the extension of the gate length. However, in a CCD line sensor in which pixels are arranged with high resolution, in order to arrange a shift gate in each pixel, a very fine processing technique is required, which makes it difficult to form the shift gate.

Japanese Patent Laid-Open No. 11-261897 (page 4, FIG. 1)

  Solid that can improve the difficulty in forming shift gates, extending the length of storage gates, increasing manufacturing costs, and degrading manufacturing margins and device characteristics caused by narrowing the pixel arrangement for photoelectric conversion for higher resolution An imaging device is provided.

  According to one aspect of the present invention, there is provided a solid-state imaging device in which a plurality of pixels that accumulate charges generated according to the intensity of incident light are arranged in a row in one direction, and are arranged adjacent to each other. A plurality of pixel sets, each having one pixel as one pixel set and the two pixels as a first pixel and a second pixel, are stored in the second pixel arranged for each pixel set. A first shift gate for transferring the transferred charge to the first pixel, a first storage gate for storing the charge transferred from the first pixel, and a charge transferred from the first storage gate. A second storage gate for storing, a second shift gate for transferring the charge stored in the second storage gate, and a charge transferred by the second shift gate in the same direction as the arrangement direction of the pixels With a CCD register to transfer to The solid-state imaging device is provided to symptoms.

  According to the present invention, even if the arrangement pitch of the pixels for photoelectric conversion is narrowed, it is possible to easily form a shift gate for the purpose of reading out charges from the pixel portion, and to suppress the extension of the gate length of the storage gate. The manufacturing cost, manufacturing margin, and transfer characteristics can be improved.

FIG. 2 is a schematic configuration diagram illustrating the layout of a solid-state imaging device according to an embodiment of the present invention. 1 is a schematic cross-sectional view of a solid-state imaging device according to an embodiment of the present invention. The figure which shows the example of the difference in the electric potential gradient of the pixel 11 and the pixel 12 which are contained in the pixel group 1 of the Example of this invention. The figure which shows the example of the impurity distribution of the shift gate 2 of the Example of this invention. The timing chart which shows the example of the drive timing of the Example of this invention. The figure which shows the example of a structure of the output data of the Example of this invention. The figure for demonstrating the structural feature of the storage part 3 of the Example of this invention.

  Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof will not be repeated.

  As an embodiment of the present invention, an example of a solid-state imaging device called a line sensor or a linear sensor in which a plurality of pixels that accumulate charges generated according to the intensity of incident light are arranged in a row in one direction is shown.

  FIG. 1 is a schematic configuration diagram illustrating a layout of a solid-state imaging device according to an embodiment of the present invention.

  In the solid-state imaging device according to the present embodiment, two pixels arranged adjacent to each other are set as one pixel set 1, and all the pixels arranged in one column are divided into n pixel sets 1. Here, the pixels included in the pixel set 1 are referred to as a pixel 11 and a pixel 12.

  With respect to this one set of pixels 1, the solid-state imaging device according to the present embodiment includes a shift gate 2 that transfers charges accumulated in the pixels 12 to the pixels 11, and an accumulation gate that accumulates charges transferred from the pixels 11. 3, an accumulation gate 4 that accumulates charges transferred from the accumulation gate 3, a shift gate 5 that transfers charges accumulated in the accumulation gate 4, and the charges transferred by the shift gate 5 are the same as the pixel arrangement direction. A CCD register 6 for transferring in the direction is provided.

  Conventionally, all the charges stored in each pixel are transferred in the same direction, whereas in this embodiment, the charges stored in the two pixels (pixel 11 and pixel 12) are transferred in different directions. Is done.

  Since the pixel 11 and the pixel 12 share the storage gate, a time difference is provided between the transfer of the charge accumulated in the pixel 11 and the transfer of the charge accumulated in the pixel 12, and the respective charges are time-divisionally divided. Transfer to storage gate 3. Further, the charge accumulated in the pixel 12 is transferred to the accumulation gate 3 via the pixel 11.

  For this purpose, in this embodiment, a shift gate 2 for transferring the charge accumulated in the pixel 12 to the pixel 11 is provided.

  The shift gate 2 is disposed at a position where the pixel faces the storage gate 3 with the pixel 11 and the pixel 12 interposed therebetween. That is, as shown in FIG. 1, when the accumulation gate 3 is arranged in the lower end direction of the pixel 11 and the pixel 12, the shift gate 2 is arranged in the upper end direction of the pixel 11 and the pixel 12.

  Therefore, in order to send the charge from the pixel 12 to the shift gate 2, it is necessary to move the charge accumulated in the pixel 12 upward in FIG.

  On the other hand, in order to transfer the charge accumulated in the pixel 11 to the accumulation gate 3, it is necessary to move the charge accumulated in the pixel 11 downward in FIG.

  That is, in the pixel 11 and the pixel 12, it is necessary to form the charge movement directions in opposite directions.

  The movement direction of this electric charge is controlled by changing the impurity concentration near the light receiving surface of the pixel 11 and the pixel 12 in a stepwise manner to provide a potential gradient.

  FIG. 2 is a schematic structural cross-sectional view showing an example of the structure when the solid-state imaging device of the present embodiment is formed on a p-type substrate. FIG. 2 also shows the potential gradient when the light source is turned on and off along the cross-sectional structure.

  2A shows a case where the formation regions of the shift gate 2, the pixel 11, the accumulation gate 3, the accumulation gate 4, the shift gate 5, and the CCD register 6 arranged in the vertical direction in FIG. 1 are cut in the arrangement direction. FIG.

  Similarly, FIG. 2B shows the formation region of the shift gate 2, the pixel 12, the storage gate 3, the storage gate 4, the shift gate 5, and the CCD register 6 arranged in the vertical direction in FIG. It is sectional drawing when cut | disconnecting.

  As shown in FIG. 2A and FIG. 2B, gate electrodes are respectively provided on the substrate surfaces of the shift gate 2, the storage gate 3, the storage gate 4, the shift gate 5, and the CCD register 6, respectively. Signal wirings for supplying the driving pulses PDSH, ST1, ST2, SH and CK are connected.

  Here, as can be seen from a comparison between FIG. 2A and FIG. 2B, there is a difference in the shape of the p-type impurity region formed in the n-type region between the pixel 11 and the pixel 12. Accordingly, the gradient direction of the potential gradient is also different.

  FIG. 3 shows the difference in impurity concentration gradient and potential gradient between the pixel 11 and the pixel 12 in more detail.

  FIG. 3A shows the cross section of the pixel 11, and FIG. 3B shows the cross section of the pixel 12. This cross-sectional structure shows a state in which the impurity concentration is gradually changed to p1, p2, and p3 by performing pitting of p-type impurities while changing the implant region.

  When implanting the impurities, the change in the implant region is reversed in the pixels 11 and 12, so that a potential gradient in the opposite direction is formed in the pixels 11 and 12. Thereby, in the pixel 11 and the pixel 12, the charge movement direction is reversed. In addition, since the potential of the p1 region of the pixel 12 is higher than the potential of the p3 region of the pixel 11 and it is necessary to prevent the charge from returning from the shift gate 2, p4 is implanted in the entire region of the pixel 12. When p4 is not used, the area of the shift gate 2 may be increased so that charges can be accumulated.

  In the pixel 11, the charge moves in the direction of the accumulation gate 3, whereas in the pixel 12, the charge moves in the direction of the shift gate 2.

The shift gate 2 needs to transfer the charges transferred from the pixel 12 to the pixel 11. Therefore, this shift gate 2 is provided with a potential gradient so that charges move from the pixel 12 toward the pixel 11.
FIG. 4 shows an example of the impurity concentration distribution of the shift gate 2.

FIG. 4A shows an example in which the shift gate 2 is formed in a p-type region and a p ⁺ impurity region is provided on the pixel 12 side.

  Further, as shown in FIG. 4B, the shift gate 2 may be formed in the n-type region, and the p-type region may be provided on the pixel 12 side.

  In either case, a potential gradient is formed such that charges move from the pixel 12 toward the pixel 11.

  The shift gate 2 transfers the charge accumulated in the pixel 12 to the pixel 11 when the drive pulse PDSH is input. When the charge can be stored in the shift gate 2, the charge is once held in the shift gate 2 when the drive pulse PDSH is input, and the charge is stored in the pixel 11 when the PDSH is switched from the high level to the low level. Transferred.

  The charge transferred to the pixel 11 is transferred to the storage gate 3 when the drive pulse ST1 is input, and is stored in the storage gate 3.

  The charges accumulated in the accumulation gate 3 are transferred to the accumulation gate 4 when the drive pulse ST2 is inputted, and accumulated in the accumulation gate 4.

  The charge accumulated in the accumulation gate 4 is transferred to the CCD register 6 via the shift gate 5 when the drive pulse SH is inputted.

  Next, the state of charge transfer in this embodiment will be described with reference to the drive timing chart shown in FIG.

  When the light source that has been lit up at time t1 is turned off and the drive pulse ST1 is input, the charge C1 accumulated in the pixel 11 during lighting is transferred to the accumulation gate 3 and accumulated in the accumulation gate 3. The

  Thereafter, when the drive pulse ST2 is input at time t2, the charge C1 accumulated in the accumulation gate 3 is transferred to the accumulation gate 4 and accumulated in the accumulation gate 4.

  Next, when the drive pulse SH is input at time t3, the charge C1 stored in the storage gate 4 is transferred to the CCD register 6 via the shift gate 5.

  On the other hand, at time t3, the drive pulse PDSH and the drive pulse ST1 are also input, and the charge C2 accumulated in the pixel 12 is transferred to the pixel 11 via the shift gate 2 and further transferred to the accumulation gate 3.

  Next, when the driving pulse ST <b> 2 is input at time t <b> 4, the charge C <b> 2 accumulated in the accumulation gate 3 is transferred to the accumulation gate 4 and accumulated in the accumulation gate 4.

  Thereafter, when the drive pulse SH is input at time t5, the charge C2 accumulated in the accumulation gate 4 is transferred to the CCD register 6 via the shift gate 5.

  Thus, in this embodiment, the charge C1 accumulated in the pixel 11 is transferred to the CCD register 6 when the first drive pulse SH is input, and the pixel 12 is input when the next drive pulse SH is input. The charge C <b> 2 stored in is transferred to the CCD register 6. Thereafter, for each input of the driving pulse SH, the charge C1 accumulated in the pixel 11 and the charge C2 accumulated in the pixel 12 are transferred to the CCD register 6 alternately.

  The n CCD registers 6 provided in each pixel group form a horizontal transfer CCD register by sequentially connecting adjacent CCD registers 6 in the horizontal direction. The charges transferred to each CCD register 6 are sequentially transferred to adjacent CCD registers 6 and output as serial data. This shift operation is controlled by the drive pulse CK.

  FIG. 6 shows the serial data output.

  When the first driving pulse SH is input at time t11, the charges C11 to C1n accumulated in the respective pixels 11 of the first to nth column pixel sets 1 are connected to the respective pixel groups 1. Transferred to register 6. Thereafter, when the driving pulse CK is input n times, the charges C11 to C1n transferred to the CCD register 6 are output as serial data.

  Next, when the next drive pulse SH is input at time t <b> 12, the charges C <b> 21 to C <b> 2 n accumulated in the respective pixels 12 of the first to n-th column pixel groups 1 are connected to the respective pixel groups 1. Transferred to the CCD register 6. Thereafter, when the driving pulse CK is input n times, the charges C21 to C2n transferred to the CCD register 6 are output as serial data.

  The charge accumulated in the pixel 11 of the pixel set 1 and the charge accumulated in the pixel 12 are alternately output as serial data each time the drive pulse SH is input.

  As described above, in this embodiment, one shift gate 2, storage gate 3, and storage gate 4 are provided for two pixels. Therefore, the widths of the shift gate 2, the accumulation gate 3, and the accumulation gate 4 can be doubled as the pixel arrangement pitch. In other words, the width of the shift gate 2, the accumulation gate 3, and the accumulation gate 4 can be widened even when the pixel arrangement pitch is narrowed as the resolution is increased.

  Since the width of the shift gate 2 can be widened, the shift gate can be formed without requiring high processing accuracy.

  Further, the effect of extending the storage gate width will be described with reference to FIG.

  FIG. 7A shows the positional relationship between the pixels 11 and 12 and the storage gate 3 in this embodiment, and FIG. 7B shows a storage gate provided for each pixel as a reference example. The example of arrangement | positioning is shown.

  As shown in FIG. 7A, in this embodiment, since one storage gate 3 is provided for the pixel 11 and the pixel 12, the width of the storage gate 3 can be set to the width of two pixels. it can. On the other hand, in the reference example shown in FIG. 7B, the width of the storage gate must be set to one pixel. That is, in this embodiment, the width of the storage gate 3 can be made longer than in the reference example. Therefore, when the area of the storage gate is constant, the gate length of the storage gate 3 of this embodiment can be made shorter than the gate length of the storage gate of the reference example.

  Therefore, as can be seen from the comparison of the cross-sectional views shown in FIGS. 7A and 7B, the number of steps of the potential gradient provided in the storage gate 3 can be reduced as compared with the reference example.

  For example, in the reference example shown in FIG. 7B, the impurity concentration is set to 2 in the present embodiment shown in FIG. Since only the steps are required, the number of impurity implantations is two.

  According to this embodiment, since one storage gate is provided for two pixels, the width of the storage gate can be made equal to the width of two pixels. Thereby, the gate length of the storage gate can be shortened as compared with the case where the storage gate is provided for each pixel. Therefore, an increase in the gate length of the storage gate can be suppressed even when the pixel arrangement pitch is narrowed.

  Further, since the gate length of the storage gate is short, the number of impurity concentration steps in the storage gate can be reduced. Thereby, in addition to reducing the number of implants for impurities, the storage gate length is shortened and the device area is reduced, so that the manufacturing cost can be reduced.

  Further, when the gate length of the storage gate is short, charges are transferred quickly, so that a good image signal can be obtained and a sufficient manufacturing margin can be secured.

1 pixel group 11, 12 pixel 2, 5 shift gate 3, 4 accumulation gate 6 CCD register

Claims (5)

A solid-state imaging device in which a plurality of pixels for accumulating charges generated according to the intensity of incident light are arranged in a row in one direction,
A plurality of pixel sets in which two pixels arranged adjacent to each other are set as one pixel set, and the two pixels are a first pixel and a second pixel;
Arranged for each pixel set,
A first shift gate for transferring the charge accumulated in the second pixel to the first pixel;
A first accumulation gate for accumulating charges transferred from the first pixel;
A second accumulation gate for accumulating charges transferred from the first accumulation gate;
A second shift gate for transferring charges accumulated in the second accumulation gate;
A solid-state imaging device comprising: a CCD register that transfers the charge transferred by the second shift gate in the same direction as the arrangement direction of the pixels. The first shift gate comprises:
2. The solid-state imaging device according to claim 1, wherein the solid-state imaging device is disposed at a position facing the first accumulation gate across the first pixel and the second pixel. The charge transfer direction of the second pixel is
The solid-state imaging device according to claim 2, wherein the charge transfer direction of the first pixel is opposite to that of the first pixel. After the charge accumulated in the first pixel is transferred to the second accumulation gate,
The charge accumulated in the second pixel is
The solid-state imaging device according to claim 3, wherein the solid-state imaging device is transferred to the first accumulation gate via the first shift gate and the first pixel. The second shift gate comprises:
The solid-state imaging device according to claim 4, wherein the charge accumulated in the first pixel and the charge accumulated in the second pixel are alternately transferred to the CCD register.

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