JP2008065085A - Electronic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a malfunction caused by incorrect transmission of a signal between circuits in an electronic device having a scanning circuit to scan a pixel array in which a plurality of pixels are arranged. <P>SOLUTION: The scanning circuit of the electronic device includes a first power supply line pair (PL1, PL2), a second power supply line pair (PL3, PL4), a first interconnection line PI1, and a 2nd interconnection line PI2. The first power supply line pair consists of the first power supply line PL1 for supplying a first voltage to a first circuit group and the second power supply line PL2 for supplying a second voltage to the first circuit group. The second power supply line pair consists of the first power supply line PL3 for supplying the first voltage to a second circuit group and the second power supply line PL2 for supplying a second voltage to the first circuit group. The first interconnection line PI1 connects the first power suply line PL1 with the third power supply line PL4. The second interconnection line PI2 connects the second power supply line PL2 with the fourth power supply line PL4. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an electronic device, and more particularly to an electronic device including a pixel array in which a plurality of pixels are arranged and a scanning circuit that scans the pixel array.

As an electronic device that inputs or outputs an image, such as a solid-state imaging device and a liquid crystal display device, there is a device that includes a pixel array in which a plurality of pixels are arranged and a scanning circuit that scans the pixel array. The scanning circuit includes a vertical scanning circuit that selects a row of the pixel array and a horizontal scanning circuit that selects a column of the pixel array. Such a scanning circuit can be configured to include a shift register as a basic configuration.
JP 2002-247456 A JP 2006-140549 A JP 2006-148525 A

  In an electronic device such as a solid-state imaging device and a liquid crystal display device, the screen size and the number of pixels are increasing. This means that the pixel array and the scanning circuit that scans the pixel array are enlarged and the number of pixels is increased. Due to the increase in the size of the scanning circuit and the increase in the number of pixels, the length of the power supply line pair of the scanning circuit becomes longer, resulting in a voltage drop due to an increase in resistance. Here, the power supply line pair is a term including a positive power supply line and a negative power supply line. The negative power supply line is a term including a ground line, for example. Due to the voltage drop due to the resistance, the voltage of the positive power line can drop below the normal voltage, and the negative power line can rise above the normal voltage. Due to such voltage fluctuation, the threshold value of the logic circuit is deviated from the design threshold value, and a signal is not correctly transmitted from the logic circuit to the logic circuit of the next stage, and malfunction may occur.

  An object of the present invention is, for example, to prevent malfunction caused by a signal not being correctly transmitted between circuits in an electronic device having a pixel array in which a plurality of pixels are arranged and a scanning circuit that scans the pixel array.

  The present invention relates to an electronic apparatus including a pixel array in which a plurality of pixels are arranged and a scanning circuit that scans the pixel array, and the power supply line pairs in which the scanning circuit is arranged along one direction. And a plurality of interconnect lines and a plurality of circuit groups including a first circuit group and a second circuit group. The plurality of power supply line pairs include a first power supply line pair and a second power supply line pair. The first power supply line pair includes a first voltage line that supplies a first voltage to the first circuit group and a second voltage line that supplies a second voltage to the first circuit group. The second power supply line pair includes a first voltage line that supplies a first voltage to the second circuit group and a second voltage line that supplies a second voltage to the second circuit group. The first circuit group and the second circuit group are connected to each other. The plurality of interconnect lines include a first interconnect line that connects a first voltage line of the first power supply line pair and a first voltage line of the second power supply line pair, and a first interconnect line of the first power supply line pair. And a second interconnect line connecting the second voltage line and the second voltage line of the second power supply line pair.

  The electronic device can be configured as a device including a solid-state imaging device, for example. Alternatively, the electronic device can be configured as a display device such as a liquid crystal display device.

  According to the present invention, for example, in an electronic device having a pixel array in which a plurality of pixels are arrayed and a scanning circuit that scans the pixel array, it is possible to prevent malfunction due to a signal not being correctly transmitted between the circuits.

  FIG. 10 is a layout diagram of a MOS transistor. FIG. 11 is a circuit diagram of the CMOS inverter. FIG. 12 is a circuit diagram showing an example of a circuit configured with a CMOS inverter. FIG. 13 shows a layout of the circuit shown in the circuit diagram of FIG. FIG. 14 is a diagram schematically showing the circuit shown in FIG. 12 and its layout. In FIG. 14, the positions of signal lines, power supply lines, and circuit elements are schematically shown. In the present application, the position of the signal line, the power supply line, and the circuit element may be schematically shown by such a drawing method.

  FIG. 15 is a diagram schematically showing a circuit and layout of a dynamic scanning circuit (dynamic shift register). In FIG. 15, the dynamic scanning circuit is arranged so that power is supplied by one power supply line pair extending in one direction. The power supply line pair includes a first power supply line (VDD line) PL1 that supplies a positive voltage that is a first voltage, and a second power supply line (GND line) PL2 that supplies a negative voltage that is a second voltage. Consists of. Here, the power supply line that supplies the first voltage may be referred to as a first voltage line, and the power supply line that supplies the second voltage may be referred to as a second voltage line.

  The signal is input to the input terminal of the leftmost CMOS inverter IV, and sequentially transmitted to the next-stage inverter IV via the switch SW. Φ1 and Φ2 are clock signals for opening and closing the switch SW. Φ1 and Φ2 are activated alternately so that the activation periods do not overlap.

  FIG. 16 is a schematic block diagram illustrating a configuration of an amplification type solid-state imaging device in which a pixel includes an amplification transistor. As the horizontal scanning circuits 1003a and 1003b and the vertical scanning circuit 1004 of the solid-state imaging device shown in FIG. 16, a circuit to which a scanning circuit schematically shown in FIG. 15 is applied can be used. Of course, depending on the function to be given to each circuit, the circuit configuration becomes more complicated.

  In recent years, the pixel size of amplification type solid-state imaging devices has been reduced. As illustrated in FIG. 20, each pixel can include a light receiving unit (photodiode) PD and a readout circuit, for example, an amplification transistor Q1. Reduction of the pixel size requires reduction of a unit block constituting the scanning circuit. FIG. 17 is a diagram schematically showing the circuit and layout of the scanning circuit when the pixel size is reduced. When the pixel size is large, the unit blocks constituting the scanning circuit can be arranged within a large pitch (pixel width viewed from the scanning circuit side). Therefore, all circuit elements (inverters I1 to I5, switches S1 to S5) can be arranged in a region through which one power supply line pair passes. On the other hand, when the pixel size is reduced, the unit blocks constituting the scanning circuit must be arranged within a small pitch, so that the length of the unit block extends in the direction orthogonal to the pitch. As the length of the unit block increases, the number of power supply line pairs passing through the unit block increases. For this reason, the scanning circuit is arranged in a region through which a plurality of power supply line pairs pass. In the example shown in FIG. 17, the scanning circuit is arranged in a region where two power supply line pairs pass.

  In the amplification type solid-state imaging device, a large imaging area is regarded as important as the number of pixels increases. As a result, the number of circuit elements connected to the power supply line increases and the resistance of the power supply line increases. Here, consider a case where high data is written in all rows of a vertical scanning circuit having a configuration partially shown in FIG. In this case, the outputs of the inverters I1, I3, I5 are high and the outputs of the inverters I2, I3, I4 are low during a certain period, and the outputs of the inverters I1, I3, I5 are low and the inverters I2, I3, The output of I4 is controlled to be high. Therefore, a large current flows through the first and fourth power supply lines during a certain period, and a large current flows through the second and third power supply lines during the next period. A voltage drop occurs due to the current and the resistance of the power supply line, and the power supply voltage fluctuates greatly. Therefore, there arises a problem that the power supply voltage differs between inverters that exchange signals. When the power supply voltage is different, the threshold voltage is different between the inverters. In general, the design is made on the assumption that the threshold voltage is the same (usually about ½ of the power supply voltage), and therefore malfunction may occur if the threshold voltage is different for each inverter. That is, there is a problem that signals are not correctly transferred.

  The current flowing through the power supply line can include a through current of the inverter and a charge / discharge current for charging / discharging the capacitive load of the gate and the signal line. Depending on the number of connected circuit elements, the current value may be several mA to several tens of mA. The resistance value is as large as about 50 to 500Ω, although it depends on the line width. For example, when a current of 4 mA flows, a voltage fluctuation of 2 volts can occur. As a result, the threshold value of a certain inverter is 3.5 volts, and the threshold value of other inverters is 1.5 volts, which may prevent correct signal transmission.

  Furthermore, since the unit blocks constituting the scanning circuit are arranged within a small pitch as the pixels are miniaturized, the line width of the power supply line can be reduced. Therefore, the resistance value of the power supply line becomes a larger value, and the possibility that correct transmission of the signal cannot be increased.

  FIG. 18 is a diagram schematically showing the circuit and layout of another scanning circuit (dynamic shift register). The example shown in FIG. 18 is an example in which clock buffers buf1 and buf2 are provided every certain period, for example, every several to hundreds of pixels, in order to improve waveform rounding due to resistance of the lines of clocks Φ1 and Φ2. In FIG. 18, buf1 is connected to CMOS switches S1, S5, and buf2 only to CMOS switch S3, but in actuality, any of them can be connected to, for example, several to several hundred CMOS switches. Although omitted for simplification in FIG. 18, buf1 and buf2 output a non-inverted signal and an inverted signal to drive the nMOS gate and the pMOS gate of the CMOS switch. Here, it is considered that the clock Φ2 transitions to high while the clock Φ1 is low. Since buf2 is connected to many CMOS switches, it is necessary to charge and discharge the gate capacitance of these CMOS switches. Therefore, a large charge / discharge current flows through the power line via buf2. Therefore, a power supply voltage fluctuation of several volts occurs due to the resistance of the power supply line. For example, the potential of the second voltage line (ground line) can increase by about 1.5 volts. At this time, buf1 refers to the potential of the second voltage line and applies a low level to the nMOS in the CMOS switch. However, since the potential of the second voltage line rises to 1.5 volt, the nMOS is turned on, and the held signal (signal to be shifted) is lost.

  As described above, a scanning circuit such as a vertical scanning circuit or a horizontal scanning circuit that selects a row and a column in a pixel array in which a plurality of pixels are arranged in a matrix is elongated as the pixel size is reduced. Accordingly, the scanning circuit can be configured to be driven by a plurality of power supply line pairs. At this time, if there is a potential difference between power supply lines that should be at the same potential (for example, between the first voltage line of one power supply line pair and the first voltage line of another power supply line pair), a signal is transmitted between circuit elements. May not be transmitted correctly and malfunctions may occur.

  The present invention has been made on the basis of such problem recognition. Hereinafter, preferred embodiments of the present invention will be exemplarily described.

  FIG. 1 shows a notation method of unit blocks constituting a scanning circuit (shift register for shifting data). Here, the unit block is a circuit block that is arranged within the width (pitch) of one pixel in the column direction or the row direction and selects a pixel group for one row or one column. One unit block shown on the left side of FIG. 1 is expressed as shown on the right side of FIG. A symbol A is attached to such a unit block.

  FIG. 2 is a diagram representing the connection of power supply lines (voltage lines) in accordance with the notation defined in FIG. According to the example shown in FIG. 2, the first power line (first voltage line of the first power line pair) and the third power line (second power line pair) for supplying the first voltage (VDD). Are connected to each other. In addition, the second power supply line (second voltage line of the first power supply line pair) and the fourth power supply line (second voltage line of the second power supply line pair) for supplying the second voltage (GND) are mutually connected. It is connected.

  For example, when a current flows through an element directly connected to the first power supply line and no current flows through an element directly connected to the third power supply line, the current flowing through the element directly connected to the first power supply line is The power can be distributed between the first power line and the third power line. Thereby, the voltage drop of a 1st voltage line can be suppressed. In addition, for example, when a current flows through an element directly connected to the fourth power supply line and a current does not flow through an element directly connected to the second power supply line, a current flowing through the element directly connected to the fourth power supply line Can be distributed between the fourth power line and the fourth power line. Thereby, the voltage rise of a 2nd voltage line can be suppressed.

  According to the above configuration, the potential difference between the first power supply line and the third power supply line and the potential difference between the second power supply line and the fourth power supply line are eliminated, and the above-described malfunction related to signal transmission is solved. .

  In the example shown in FIG. 2, power supply lines (voltage lines) to which the same voltage is to be supplied are connected to each unit block. In the example shown in FIG. 2, a first circuit group is configured by a plurality of first circuits configured by inverters and switches to which power is supplied by the first power supply line pair (PL1, PL2). Further, a second circuit group is configured by a plurality of second circuits configured by inverters and switches to which power is supplied by the first power supply line pair (PL3, PL4). Here, a signal output from a part of the plurality of first circuits is input to a part of the plurality of second circuits, and a signal output from the other part of the plurality of second circuits is the plurality of first circuits. Has been entered into the other part. In this way, a plurality of first circuits and a plurality of second circuits are alternately connected to constitute a path for shifting data.

  FIG. 4 is a diagram illustrating a configuration example of a scanning circuit configured to be driven by three power supply line pairs. In FIG. 4, illustration of some signal lines is omitted. The first power supply line pair includes a first power supply line (first voltage line) PL1 that supplies a first voltage (VDD), and a second power supply line (second voltage line) PL2 that supplies a second voltage (GND). Consists of. The second power supply line pair includes a third power supply line (first voltage line) PL3 that supplies a first voltage (VDD), and a fourth power supply line (second voltage line) PL4 that supplies a second voltage (GND). Consists of. The third power supply line pair includes a fifth power supply line (first voltage line) PL5 that supplies a first voltage (VDD), and a sixth power supply line (second voltage line) PL6 that supplies a second voltage (GND). Consists of.

  The first power supply line PL1, the third power supply line PL3, and the fifth power supply line PL5 are all the first voltage lines, and are connected to each other by the first interconnection line PI1. The second power supply line PL2, the fourth power supply line PL4, and the sixth power supply line PL6 are all the second voltage lines and are connected to each other by the second interconnect line PI3.

  The first to sixth power supply lines PL1 to PL6 may be configured with, for example, a first metal layer, and the first and second interconnect lines PI1 and PI2 may be configured with, for example, a second metal layer. The first power supply line PL1, the third power supply line PL3, the fifth power supply line PL5, and the first interconnection line PI1 can be connected by a via 401. The second power supply line PL2, the fourth power supply line PL4, the sixth power supply line PL6, and the second interconnection line PI3 can be connected by a via 402.

  FIG. 19 is a diagram showing another configuration example of the scanning circuit configured to be driven by three power supply line pairs. In this configuration example, the arrangement of the power supply line and the interconnection line is the same as the example shown in FIG. Clock buffers buf1, buf2 (first circuit group) can be arranged in the area A1 where the first power supply line pair (PL1, PL2) is arranged. A transfer circuit (I1, S1, I3, S3, I5, S5...; Second circuit group) for transferring shift data is arranged in the area A2 where the second power supply line pair (PL3, PL4) is arranged. sell. A shift register is configured by the clock buffer and the transfer circuit. In the region A3 where the third power supply line pair (PL5, PL6) is arranged, output buffers (ob1, ob2; third circuit group) for buffering the output from the shift register and outputting them to the pixel array can be arranged. .

  FIG. 3 is a diagram illustrating another connection method of the power supply lines. The example shown in FIG. 3 has a configuration in which interconnection lines are thinned out from the example shown in FIG. For example, as is apparent from FIG. 4, in order to arrange the interconnection lines, a region for the interconnection lines is necessary, which may increase the layout area. Therefore, as in the example shown in FIG. 3, it should be considered to suppress an increase in layout area by thinning out the interconnect lines.

  FIG. 5 is a diagram of the voltage of the second voltage line (ground line) of the scanning circuit obtained by removing the interconnection line from the configuration illustrated in FIG. 2 or FIG. 3 as viewed in the scanning direction. Here, a case where a current flows through the second power supply line (second voltage line) PL2 and a current does not flow through the fourth power supply line (second voltage line) PL4 is shown. In this example, since the voltage is supplied from both sides of the scanning circuit, the voltage distribution of the second power supply line PL2 has a mountain shape. In FIG. 5, the arrows indicate the threshold values of the voltage difference between the two power supply lines PL2 and PL4 that cause malfunction. If a potential difference equal to or greater than the potential difference indicated by the arrow occurs between the two power supply lines PL2 and PL4, a malfunction occurs.

  FIG. 6 is a view of the voltage of the second voltage line (ground line) of the scanning circuit in which the interconnection lines are arranged at short intervals as shown in FIG. 2 along the scanning direction. As shown in FIG. 6, the potential difference between the two power supply lines PL2 and PL4 is zero at all points. Moreover, since the resistance value of the power supply line is also halved, the voltage rise in the power supply line is also halved. Naturally, no malfunction occurs.

  7, when the interconnect lines are thinned and disposed as illustrated in FIG. 3, more specifically, the voltage of the second voltage line (ground line) of the scanning circuit in which the interconnect lines are disposed at two positions is scanned. It is the figure seen along the direction. Although the potential difference between the second power supply line PL2 and the fourth power supply line PL4 is not zero, the potential difference can be reduced below the level causing malfunction, and the wiring space can be greatly reduced.

  Specifically, assuming a scanning circuit of a solid-state imaging device having 3000 rows in the vertical direction, assuming that the width of the interconnect line is 0.6 μm and the interconnect lines are arranged in units of two rows, The total width reaches 0.6 × 1500 = 900 μm. On the other hand, if there are two interconnection lines, the distance is only about 1.2 μm. This is important in reducing the pixel size of a solid-state imaging device or the like.

  The arrangement of the power supply line and the interconnection line as described above is particularly effective in the vertical scanning circuit in the solid-state imaging device. The vertical scanning circuit has many logic circuits and output buffers because it is necessary to drive a transfer switch, a selection switch, a reset transistor, and the like. Therefore, the unit block of the vertical scanning circuit extends in the row direction and is driven by a plurality of pairs of power supply lines.

  Hereinafter, as examples of the electronic device according to the present invention, a configuration example of a solid-state imaging device, a display device, and an imaging device including the solid-state imaging device will be given.

[First embodiment]
In a solid-state imaging device having a pixel array of 3000 rows in the vertical direction and 4000 columns in the horizontal direction, a dynamic scanning circuit illustrated in FIG. 2 is arranged as a vertical scanning circuit. For each unit block, the first power supply line PL1 and the third power supply line PL3 are connected by a first interconnect line PI1 having a width of 0.4 μm, and the second power supply line and the fourth power supply line PL4 are connected by a 0.4 μm width. Two interconnect lines PI2 were connected. As a result, the voltage distribution shown in FIG. 6 was obtained, and a good solid-state imaging device free from malfunction could be obtained.

[Second Embodiment]
In a solid-state imaging device having a pixel array of 3000 rows in the vertical direction and 4000 columns in the horizontal direction, a circuit in which interconnection lines are added to the static scanning circuit illustrated in FIG. 8 is used as the vertical scanning circuit. The static type scanning circuit has twice the number of switches and the number of inverters per unit row as compared with the dynamic type scanning circuit, and is a circuit that is likely to malfunction because it extends over many power supply lines. Interconnect lines were arranged at 30 locations in units of 100 rows. Since the static scanning circuit has a large number of elements, the space for the interconnect line having a width of 0.4 μm is also a large loss in reducing the pixel size. In this embodiment, it was possible to obtain a good solid-state imaging device free from malfunctions while omitting the space for the interconnection lines.

[Third embodiment]
In a solid-state imaging device having a pixel arrangement of 3000 rows in the vertical direction and 4000 columns in the horizontal direction, the power supply voltage VDD is used to increase the transfer efficiency of the transfer switch Q3 for transferring charges from the light receiving unit PD to the gate of the amplification transistor Q1. Was increased from 5 volt to 6 volt. As the power supply voltage VDD rises, the through current increases to the square of the power supply voltage VDD, and the charge / discharge current increases in proportion to the power supply voltage VDD, so the possibility of malfunction increases.

  Therefore, interconnection lines were arranged at about 30 locations. At this time, interconnected lines were arranged at positions indicated by a substantially geometric series so that the central portion of the scanning circuit was dense and became rough toward both ends. Thereby, the voltage difference in the center part of the scanning circuit was reduced.

  In the solid-state imaging device, a control signal is provided from the vertical scanning circuit to the control terminal of each switch in the pixel shown in FIG. Of these switches, the reset switch Q2 and the selection switch Q4 are simple circuit switches. On the other hand, the transfer switch Q3 needs to transfer all the charges accumulated in the embedded photodiode constituting the photoelectric conversion unit PD to the gate of the amplification transistor Q1. In order to achieve good transfer, it is necessary to apply a high voltage to the gate of the transfer switch Q3. Further, since the transfer switch Q3 is the only switch in contact with the photodiode, it is necessary to sufficiently turn off the transfer switch Q3 in order to suppress the dark current generated in the photodiode, and it is preferable to use a negative power supply. Therefore, in the vertical scanning circuit of the solid-state imaging device, a high potential difference is required between the positive power supply voltage and the negative power supply voltage. Therefore, in the vertical scanning circuit of the solid-state imaging device, the above-described problem is likely to be manifested, and the circuit is desired to be applied to the present invention.

[Fourth embodiment]
The present invention is also suitable for a scanning circuit of a display device such as a liquid crystal display device. FIG. 9 is a diagram showing a schematic configuration of the liquid crystal display device. Image signals are input to the image signal input terminals 17a and 17b, and the image signals are output to the common signal lines 16a and 16b through the amplifiers 15a and 15b. The image signal is written to the pixels in the pixel array unit 11. More specifically, each pixel has a writing switch and a pixel electrode, and an image signal is written to the pixel electrode via the writing switch selected by the horizontal scanning circuits 13a and 13b and the vertical scanning circuit 14.

  In a liquid crystal display device, it is necessary to write a high voltage to the pixel electrode in order to invert the liquid crystal. The image signal is an alternating signal in order to prevent the liquid crystal from burning. Therefore, the scanning circuit for driving the pixel array unit 11 is also driven with a high voltage. In this example, a 15 volt power source was used. The liquid crystal display device has 10 million pixels regardless of the display standard. In this embodiment, since a high-breakdown-voltage MOS transistor is used, the size of each transistor increases, so that a scanning circuit is arranged across a plurality of pairs of power supply lines. Interconnect lines were arranged in units of two rows. As a result, it was possible to obtain a good liquid crystal display device with no malfunction.

[Fifth Embodiment]
A function of scanning in the reverse direction, a function of switching the scanning order, a function of skipping reading, and the like are added to the scanning circuit of the solid-state imaging device according to the first embodiment. As a result, the number of elements is increased as compared with the first embodiment 1, so that the number of power supply line pairs becomes 10. In addition, the through current and charge / discharge current increased. In this embodiment, the skip position is arranged in units of 200 lines. Therefore, a large block unit of the scanning circuit becomes 200 row units. Interconnect lines were placed for each large block unit. Arranging interconnect lines for each large block unit can suppress malfunctions and malfunctions that tend to occur in units of blocks in addition to suppressing malfunctions. I was able to.

[Example of application of fixed imaging device]
FIG. 21 is a diagram illustrating a schematic configuration of an imaging apparatus according to a preferred embodiment of the present invention. The imaging device 400 includes a solid-state imaging device 1004 typified by the photoelectric conversion devices 100 and 101 of the first and second embodiments.

  An optical image of the subject is formed on the imaging surface of the solid-state imaging device 1004 by the lens 1002. On the outside of the lens 1002, a barrier 1001 serving both as a protection function of the lens 002 and a main switch can be provided. The lens 1002 can be provided with a diaphragm 1003 for adjusting the amount of light emitted therefrom. The imaging signal output from the solid-state imaging device 1004 through a plurality of channels is subjected to various corrections, clamping, and the like by the imaging signal processing circuit 1005. Imaging signals output from the imaging signal processing circuit 1005 through a plurality of channels are subjected to analog-digital conversion by an A / D converter 1006. The image data output from the A / D converter 1006 is subjected to various corrections, data compression, and the like by the signal processing unit 1007. The solid-state imaging device 1004, the imaging signal processing circuit 1005, the A / D converter 1006, and the signal processing unit 1007 operate according to the timing signal generated by the timing generation unit 1008.

  The blocks 1005 to 1008 may be formed on the same chip as the solid-state imaging device 1004. Each block of the imaging apparatus 400 is controlled by the overall control / arithmetic unit 1009. In addition, the imaging apparatus 400 includes a memory unit 1010 for temporarily storing image data and a recording medium control interface unit 1011 for recording or reading an image on a recording medium. The recording medium 1012 includes a semiconductor memory or the like and can be attached and detached. The imaging apparatus 400 may include an external interface (I / F) unit 1013 for communicating with an external computer or the like.

  Next, the operation of the imaging apparatus 400 illustrated in FIG. 21 will be described. When the barrier 1001 is opened, the main power source, the control system power source, and the power source of the imaging system circuit such as the A / D converter 1006 are sequentially turned on. Thereafter, the overall control / calculation unit 1009 opens the aperture 1003 in order to control the exposure amount. A signal output from the solid-state imaging device 1004 passes through the imaging signal processing circuit 1005 and is provided to the A / D converter 1006. The A / D converter 1006 A / D converts the signal and outputs it to the signal processing unit 1007. The signal processing unit 1007 processes the data and provides it to the overall control / arithmetic unit 1009, and the overall control / arithmetic unit 1009 performs an operation for determining the exposure amount. The overall control / calculation unit 1009 controls the aperture based on the determined exposure amount.

  Next, the overall control / calculation unit 1009 extracts a high frequency component from the signal output from the solid-state imaging device 1004 and processed by the signal processing unit 1007, and calculates the distance to the subject based on the high frequency component. Thereafter, the lens 1002 is driven to determine whether or not it is in focus. When it is determined that the subject is not in focus, the lens 1002 is driven again to calculate the distance.

  Then, after the in-focus state is confirmed, the main exposure starts. When the exposure is completed, the imaging signal output from the solid-state imaging device 1004 is corrected and the like in the imaging signal processing circuit 1005, A / D converted by the A / D converter 1006, and processed by the signal processing unit 1007. The image data processed by the signal processing unit 1007 is accumulated in the memory unit 1010 by the overall control / calculation 1009.

  Thereafter, the image data stored in the memory unit 1010 is recorded on the recording medium 1012 via the recording medium control I / F unit under the control of the overall control / calculation unit 9. The image data can be provided to a computer or the like through the external I / F unit 1013 and processed.

It is a figure which shows the notation method of the unit block which comprises a scanning circuit. FIG. 2 is a diagram illustrating connection of power supply lines (voltage lines) according to the notation method defined in FIG. 1. It is a figure which shows the other connection method of a power supply line. It is a figure which shows the structural example of the scanning circuit comprised so that it might drive with three power supply line pairs. It is the figure which looked at the voltage of the 2nd voltage line (ground line) of the scanning circuit which removed the interconnection line from the structure shown in FIG. 2 or FIG. 3 along the scanning direction. It is the figure which looked at the voltage of the 2nd voltage line (ground line) of the scanning circuit which has arrange | positioned the interconnection line at short intervals along the scanning direction. It is the figure which looked at the voltage of the 2nd voltage line (ground line) of the scanning circuit which has arranged the interconnection line in two places along the scanning direction. It is a circuit diagram of a static type scanning circuit. It is a block layout figure of a liquid crystal display device. It is a layout diagram of a MOS transistor. It is a circuit diagram of a CMOS inverter. It is a circuit diagram which shows an example of the circuit comprised by a CMOS inverter. It is a figure which shows the layout of the circuit shown by the circuit diagram of FIG. FIG. 13 is a diagram schematically showing the circuit shown in FIG. 12 and its layout. It is the figure which represented typically the circuit and layout of a dynamic type scanning circuit. It is a block layout figure of a solid imaging device. It is the figure which represented typically the circuit and layout of the scanning circuit at the time of reducing pixel size. It is the figure which represented typically the circuit and layout of another dynamic type scanning circuit (dynamic shift register). It is a figure which shows the other structural example of the scanning circuit comprised so that it might drive with three power supply line pairs. Pixel equivalent circuit diagram used in solid-state imaging device 1 is a diagram illustrating a schematic configuration of an imaging apparatus according to a preferred embodiment of the present invention.

Claims (7)

An electronic device including a pixel array in which a plurality of pixels are arranged, and a scanning circuit that scans the pixel array,
The scanning circuit includes a plurality of power supply line pairs arranged along one direction, a plurality of interconnection lines, and a plurality of circuit groups including a first circuit group and a second circuit group,
The plurality of power supply line pairs include a first power supply line pair and a second power supply line pair, and the first power supply line pair supplies a first voltage line for supplying a first voltage to the first circuit group, and the first power supply line pair. A second voltage line for supplying a second voltage to the circuit group, and the second power line pair includes a first voltage line for supplying the first voltage to the second circuit group and a second voltage line for the second circuit group. A second voltage line for supplying two voltages,
The first circuit group and the second circuit group are connected to each other;
A plurality of interconnection lines connecting a first voltage line of the first power supply line pair and a first voltage line of the second power supply line pair; and a first interconnect line of the first power supply line pair. A second interconnect line connecting two voltage lines and a second voltage line of the second power line pair;
An electronic device characterized by that.   The signal output from at least a part of the plurality of first circuits constituting the first circuit group is inputted to at least a part of the plurality of second circuits constituting the second circuit group. Item 2. The electronic device according to Item 1.   A signal output from a part of the plurality of first circuits constituting the first circuit group is inputted to a part of the plurality of second circuits constituting the second circuit group, and other than the plurality of second circuits. The electronic device according to claim 1, wherein a signal output from a part of the electronic circuit is input to another part of the plurality of first circuits.   The scanning circuit includes a shift register for shifting data, and a path for shifting the data includes a plurality of first circuits constituting the first circuit group and a plurality of second circuits constituting the second circuit group. The electronic device according to claim 1, wherein the electronic device is configured by being alternately connected.   The electronic device according to claim 1, wherein the electronic device is configured as a device including a solid-state imaging device.   6. The electronic apparatus according to claim 5, wherein the scanning circuit is a vertical scanning circuit that selects a row of the pixel array.   The electronic device according to claim 1, wherein the electronic device is configured as a device including a display device.

Images