JP5197440B2 - Photoelectric conversion device - Google Patents

Description

  The present invention relates to a photoelectric conversion device having a sensor cell unit that performs photoelectric conversion and a memory cell unit that stores signals.

  Patent Document 1 discloses a technique for removing noise added to a signal in order to accurately extract a signal obtained by photoelectric conversion in a photoelectric conversion device, particularly a CMOS type sensor. Further, Patent Document 2 discloses that the technology is applied to an autofocus (hereinafter also referred to as AF) sensor. In recent years, there has been an increasing demand for multipoint AF ranging points for the AF function, and it has been proposed as an area-type phase difference detection AF sensor that is advantageous for high-density pixel arrangement.

Japanese Patent Laid-Open No. 9-200614 JP-A-9-200269

  In response to the above-described demand for higher density of AF distance measuring points, further reduction of peripheral circuits including further simplification of circuit configuration and reduction of the number of elements has become problems.

  The removal of noise added to a signal in the photoelectric conversion device can be realized by the circuit configuration including the sensor cell unit, the memory cell unit, and the transfer system circuit unit described in the first embodiment of Patent Document 1. It is. However, in order to perform real-time AGC (automatic gain control) for performing gain control according to an optical signal during an optical signal accumulation operation for accumulating photoelectrically converted charges, Embodiment 2 of Patent Document 1 described above is used. A circuit configuration as shown was necessary. That is, it is necessary to provide a switch MOS transistor to enable feedback from the transfer system circuit unit to the sensor cell unit. In other words, real-time AGC cannot be performed with a circuit configuration in which the number of elements is reduced as shown in Embodiment 1 of Patent Document 1.

  Moreover, in the thing of the said patent document 1, the sensor cell part and the memory cell part are connected via the transfer system circuit part. For this reason, the sensor cell unit and the memory cell unit are arranged apart from each other, and the sensor cell unit and the memory cell unit individually include inverting amplifiers (inverting amplifiers) for reading signals.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a photoelectric conversion apparatus capable of performing real-time AGC with a smaller number of circuit elements than in the past.

The photoelectric conversion device according to the present invention includes a sensor cell unit that inverts and amplifies and outputs a signal obtained by photoelectric conversion, a memory cell unit that accumulates and inverts and outputs the signal, the sensor cell unit, and the memory A common output line connected to the cell portion is connected to the first node, and has a transfer capacitor connected to the first node via a first switch; from the sensor cell portion and the memory cell portion; A transfer circuit unit for transferring the output signal, an interconnection point between the first switch and the transfer capacitor, and a second switch connected to a power source are provided.
According to the above configuration, feedback from the transfer circuit unit to each of the sensor cell unit and the memory cell unit can be performed without individually providing a switch corresponding to each of the sensor cell unit and the memory cell unit.

  According to the present invention, it is not necessary for the sensor cell unit and the memory cell unit to have separate switches for enabling feedback from the transfer circuit unit. Therefore, the number of switches is reduced as compared with the prior art, and optical storage, real-time AGC, and signal readout operations can be performed with a smaller number of elements.

It is a figure which shows the structural example of the photoelectric conversion apparatus in the 1st Embodiment of this invention. It is a timing chart which shows operation | movement of the photoelectric conversion apparatus in 1st Embodiment. It is the schematic diagram which showed a part of area type AF sensor layout. It is a schematic diagram which shows the example of the area type AF sensor layout to which the photoelectric conversion apparatus in 1st Embodiment is applied. It is a schematic diagram which shows the example of the area type AF sensor layout in 2nd Embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
A first embodiment of the present invention will be described.
FIG. 1 is a circuit diagram illustrating a configuration example of the photoelectric conversion apparatus according to the first embodiment. FIG. 2 is a timing chart showing the operation of the photoelectric conversion apparatus according to the first embodiment.

  As shown in FIG. 1, the photoelectric conversion device according to the first embodiment includes a sensor cell unit SC, a memory cell unit MC, and a transfer circuit unit TC. The sensor cell unit SC and the memory cell unit MC are commonly connected to a common output line CL, and the common output line CL is connected to a node (first node) NA of the transfer circuit unit TC. The sensor cell unit SC inverts and amplifies a signal obtained by photoelectric conversion and outputs the signal. The memory cell unit MC accumulates, inverts and amplifies the signal and outputs it. The transfer circuit unit TC transfers signals output from the sensor cell unit SC and the memory cell unit MC.

  FIG. 1 shows an example in which one sensor cell unit SC, one transfer circuit unit TC, and one memory cell unit MC are provided on the common output line CL, but the present invention is not limited to this. For example, in the photoelectric conversion device according to the first embodiment, a plurality of sensor cell units SC and memory cell units MC can be arranged to function as area sensors.

  Next, each block of the sensor cell unit SC, the memory cell unit MC, and the transfer circuit unit TC will be described.

  The sensor cell unit SC includes a photodiode PD, a P-channel MOS transistor (hereinafter referred to as “PMOS transistor”) M11 and M12, and a write switch PPS1. The write switch PPS1 is a MOS transistor. The MOS transistor constituting the write switch PPS1 may be any of a PMOS transistor, an N-channel MOS transistor (hereinafter referred to as “NMOS transistor”), and a CMOS (Complementary MOS) transistor. The PMOS transistor M12 is on / off controlled by the signal φSL1 and functions as a select switch. The write switch PPS1 is on / off controlled by a signal φPS1. The output format is an inverting amplifier with a gain of (-1). The inverting amplifier (inverting amplifier) includes a PMOS transistor M11 and a load MOS transistor M13 as a load element. The MOS transistor M13 is on / off controlled by a signal φL.

  The memory cell unit MC has the same configuration as the sensor cell unit SC except that the photodiode PD is replaced with a frame memory capacity CM. The memory cell unit MC includes a frame memory capacitor CM, PMOS transistors M31 and M32, and a write switch PPS2. The write switch PPS2 is a MOS transistor. The MOS transistor constituting the write switch PPS2 may be any of a PMOS transistor, an NMOS transistor, and a CMOS transistor. The PMOS transistor M32 is ON / OFF controlled by the signal φSL2 and functions as a select switch. The write switch PPS2 is on / off controlled by a signal φPS2. The output format is an inverting amplifier with a gain of (-1). The inverting amplifier (inverting amplifier) includes a PMOS transistor M31 and a load MOS transistor M13 as a load element. The inverting amplifiers (inverting amplifiers) in each of the sensor cell unit SC and the memory cell unit MC share the load MOS transistor M13 as a load element, but each load element (load MOS transistor) may be provided individually. Of course it is good.

  The transfer circuit unit TC includes a transfer switch (first switch) PFT, a feedback switch (third switch) PFB, a transfer capacitor CT, and an NMOS source follower circuit (transfer amplifier). The transfer switch (first switch) PFT is a switch for turning on / off the connection between the common output line CL connected to the node NA and the transfer circuit unit TC. The transfer capacitor CT is connected to the node NA via the transfer switch PFT. The NMOS source follower circuit (transfer amplifier) is a circuit for reading the potential of the transfer capacitor CT, and includes an input NMOS transistor M21 and a constant current source. The input part of the NMOS source follower circuit (transfer amplifier) is connected to the transfer capacitor CT. The output part of the NMOS source follower circuit (transfer amplifier) is connected to the output terminal OUT2 and to the node NA through the feedback switch PFB.

  The transfer switch PFT and the feedback switch PFB are MOS transistors. The MOS transistors constituting the transfer switch PFT and the feedback switch PFB may be any of a PMOS transistor, an NMOS transistor, and a CMOS transistor. The transfer switch PFT and the feedback switch PFB are on / off controlled by a signal φFT and a signal φFB, respectively. The transfer capacitor CT and the gate of the MOS transistor M21 are reset by a constant voltage VGR, and a switch NMOS transistor M23 for performing the reset is on / off controlled by a signal φGR. In addition, a switch NMOS transistor M22 for resetting the photodiode PD (sensor cell unit SC) and the frame memory capacitor CM (memory cell unit MC) with the constant voltage VRS is provided at an interconnection point between the transfer switch PFT and the transfer capacitor CT. Connected. The switch NMOS transistor M22 as the second switch is on / off controlled by a signal φRS.

  The optical signal readout from the memory cell portion MC is an inverting amplifier output, and the MOS transistor M24 is controlled to be turned on / off by the shift pulse φH of the shift register and sequentially read out to the output line. The read optical signal is finally output to the output terminal OUT via the buffer amplifier.

Next, the operation of the photoelectric conversion device in the first embodiment will be described with reference to FIG.
In FIG. 2, the signal input to the PMOS transistor represents that the PMOS transistor is turned on at a high level as a / (bar) signal notation.

  In the period (1), first, the signals φRS, φFT, φPS1, and φPS2 are set to the high level, and the sensor cell unit SC and the memory cell unit MC are reset. At the same time, the signal / φGR, which is a reverse phase signal of the signal φGR, is also set to the high level, and the transfer capacitor CT in the transfer circuit unit TC is also reset.

  Next, the signals φRS, / φGR, φPS1, and φPS2 are set to the low level. Subsequently, the signal / φSL1 which is the reverse phase signal of the signal φSL1 and the signal / φL which is the reverse phase signal of the signal φL are set to the high level, and the sensor noise Ns after the reset of the sensor cell unit SC is read to the common output line CL. And written in the transfer capacity CT. At the end of writing, the signal φFT is set to a low level.

  In the period (2), the potential input to the gate of the MOS transistor M21 is VGR + Ns, and the signal φFB is set to the high level, so that it is output to the common output line CL by the source follower circuit. Immediately thereafter, the signal φPS1 is set to the high level, and noise (Ns + Nt) obtained by adding the noise Nt of the transfer circuit unit TC to the sensor noise Ns is input to the sensor cell unit SC. Thereafter, the signals φPS1 and φFB are set to the low level.

  Next, in period (3), the signal φFT is set to the high level, and the signals / φSL1 and / φL1 are set to the high level in order to operate the inverting amplifier of the sensor cell unit SC. Accordingly, a signal obtained by adding the sensor noise Ns to the inverting amplifier output (− (Ns + Nt)), that is, (−Nt) is output from the sensor cell unit SC. At this time, when the signal / φGR becomes high level, a signal of VGR + Nt is held between the transfer capacitors CT in the transfer circuit unit TC. Subsequently, the signal / φGR is set to the low level, and the electrode on one side of the transfer capacitor CT is brought into a floating state. Further, the signal φFT is set to a low level.

  Next, in period (4), the signal φFB is set to the high level, and the signal φPS2 is set to the high level in order to write noise into the signal φRS and the frame memory capacity CM in the memory cell unit MC. As a result, the electrode on the common output line CL side of the transfer capacitor CT becomes the potential VRS and fluctuates by the noise Nt, so the potential of the other electrode of the transfer capacitor CT also fluctuates by Nt. Therefore, the noise output from the source follower circuit and input to the memory cell unit MC is 2Nt. Thereafter, the signals φPS2 and φFB are set to the low level.

Next, in the period (5), the sensor cell unit SC enters an optical signal accumulation operation period, and performs a real-time AGC operation for controlling the output setting gain by monitoring the optical signal in real time. Here, the optical signal accumulated in the sensor-cell unit SC and S _1. The operation during the real-time AGC period will be described below.

  The signal / φGR for fixing the input of the source follower circuit to the constant voltage VGR is set to the high level, and the signal φFT is set to the high level to fix the potential of the common output line CL to the constant voltage VRS. The signal φRS is maintained at a high level. As a result, the potentials of both electrodes of the transfer capacitor CT are set to the constant voltages VGR and VRS, respectively. Further, the signal / φGR is set to the low level, and the other electrode (source follower circuit side) of the transfer capacitor CT is made floating.

Thereafter, in the period (6), the signals / φSL1 and / φL are set to the high level, and the sensor noise Ns is added to the inverted output (− (S ₁ + Ns + Nt)) from the sensor cell unit SC, and as a result, (− (S ₁ + Nt)) is output to the transfer circuit unit TC. As a result, the potential on the common output line CL side of the transfer capacitor CT varies by (− (S ₁ + Nt)), so that the potential of the other electrode of the transfer capacitor CT becomes VGR− (S ₁ + Nt). When outputting from the transfer circuit unit TC, the noise Nt of the transfer circuit unit TC is added, so that an optical signal (−S ₁ ) is output from the output terminal OUT2. As described above, the optical signal (−S ₁ ) is monitored and real-time AGC is performed.

In the period (7), the signals / φSL1, / φL, / φGR are set to the high level. As a result, the other electrode (source follower circuit side) of the transfer capacitor CT is fixed to the constant voltage VGR, and the electrode on the common output line CL side of the transfer capacitor CT varies by (− (S ₂ + Nt)) from the potential VRS. . Here, the optical signal after the end of the optical signal accumulation operation period is (−S ₂ ).

Next, in the period (8), the signal / φSL2 and the signal / φL which are opposite phase signals of the signal φSL2 are set to the high level, and the noise 2Nt stored in the memory cell unit MC is read out through the inverting amplifier. . At this time, the noise Nm of the memory cell unit MC is added, and as a result, (−2Nt + Nm) is read out to the electrode on the common output line CL side of the transfer capacitor CT. Here, a potential fluctuation amount of (−2Nt + Nm) − (− (S ₂ + Nt)) = S ₂ −Nt + Nm is written in the transfer capacitor CT.

In the period (9), when the signal φFT is set to the low level and the signals φFB and φPS2 are set to the high level, the noise Nt of the transfer circuit unit TC is added and (S ₂ + Nm) is transferred from the transfer circuit unit TC to the memory cell. Written in the part MC.

Next, the signals φPS2 and φFB are set to the low level, the signals / φSL2 and / φL for operating the inverting amplifier of the memory cell unit MC, and the signal φFT for conducting between the common output line CL and the MOS transistor M24. Is set to high level. As a result, the noise Nm of the memory cell unit MC is added to the inverted signal (− (S ₂ + Nm)), and finally (−S ₂ ) from which the noise component has been removed is output from the memory cell unit MC. This is read out sequentially for each column with the signal φH at the high level.

As described above, feedback from the transfer circuit unit TC to the sensor cell unit SC can be performed without providing a switch for individually enabling feedback for each of the sensor cell unit SC and the memory cell unit MC. As a result, a real-time AGC operation using an optical signal (−S ₁ ) from which random noise of the sensor is removed is possible even with a circuit configuration in which the number of elements is reduced, and the final signal (−S ₂ ) is also detected by the random noise of the sensor. A signal with a high S / N ratio not included is obtained.

  FIG. 3 is a schematic diagram showing a part of the configuration of the area type AF sensor layout. FIG. 3A shows a part of a conventional area AF sensor layout for comparison, and FIG. 3B shows an area AF sensor layout to which the photoelectric conversion device according to this embodiment is applied. Some of the examples are shown.

  In FIG. 3, a two-dimensional sensor array is arranged in 3 rows × 9 columns. The sensor cell unit 10 includes a sensor unit 11 and a pixel amplifier 12. The sensor unit 11 represents the photodiode PD in FIG. 1, and the pixel amplifier 12 represents a readout circuit composed of MOS transistors M11 to M13. Therefore, the sensor cell unit 10 in FIG. 3 and the sensor cell unit SC in FIG. 1 are the same. The pixel amplifier 12 is an inverting amplifier having a gain of (−1). Further, the transfer circuit unit 13 matches the transfer circuit unit TC in FIG. 1, and the memory cell unit 14 matches the memory cell unit MC in FIG. The shift register 15 is a scanning circuit for outputting a signal φH to drive the MOS transistor M24 in FIG. The optical signal is read sequentially for each column by this shift register.

  A black circle described at the center of each pixel indicates the center of gravity of each pixel. The position of the center of gravity of each pixel is optically determined in the AF sensor. Therefore, when the configuration shown in FIG. 3A is replaced with the configuration shown in FIG. 3B, the positions of the centers of gravity shown by the black circles are arranged so as not to change.

  FIG. 4 is a schematic diagram illustrating an example of the entire area-type AF sensor layout formed on a semiconductor substrate to which the photoelectric conversion device according to the first embodiment is applied. A configuration in which 9 column pixels × 3 rows are extracted from 250 pixels × 18 rows of the horizontal eye A image in FIG. 4 corresponds to the configuration shown in FIG.

  Since the area type AF sensor shown in FIG. 4 is a phase difference detection type AF sensor, the standard part (A image) and the reference part (B image) form a pair, and the vertical eye and the horizontal eye allow cross-range measurement. Each is arranged. The vertical eye is composed of a pixel array of 150 pixels × 42 columns, and the horizontal eye is composed of a pixel array of 250 pixels × 18 rows. Peripheral circuit portions indicated by hatched portions are arranged in the vertical and horizontal eyes, respectively.

  As shown in FIG. 4, it can be seen that there is no layout margin between the vertical peripheral circuit portion and the horizontal eye A image and horizontal eye B image, and the area of the peripheral circuit portion is an obstacle to high-density pixel arrangement. In addition, when a sufficient area for arranging the peripheral circuit portion is secured, it is clear that the lateral A image and the lateral B image are moved outward, leading to an increase in the chip area.

  In FIG. 3A, since the sensor cell unit 10 and the memory cell unit 14 are connected with the transfer circuit unit 13 interposed therebetween, the sensor cell unit 10 and the memory cell unit 14 are arranged apart from each other. The peripheral circuit section includes a transfer circuit section 13, a memory cell section 14, and a shift register 15. Since the transfer circuit unit 13 is connected to a common output line (not shown), a total of two feedback lines exist in the sensor cell unit 10 (upward) and the memory cell unit 14 (downward). For this reason, there are two lines of wiring, and there is one set of a MOS transistor constituting a feedback switch and a MOS transistor constituting a transfer switch. Therefore, there are two MOS transistors that constitute the feedback switch and two MOS transistors that constitute the transfer switch.

  In FIG. 3B, the sensor cell units 10 and the memory cell units 14 are alternately arranged, and the sensor unit 11 of the sensor cell unit 10 and the corresponding memory cell unit 14 are arranged adjacent to each other. Therefore, the peripheral circuit unit is configured by the transfer circuit unit 13 and the shift register 15 by taking the memory cell unit 14 occupied as the peripheral circuit into the sensor cell unit 10 while maintaining the optical system specifications. .

  In FIG. 3B, the sensor cell unit 10 and the memory cell unit 14 are not arranged with the transfer circuit unit 13 interposed therebetween. Therefore, the number of feedback lines connected to a common output line (not shown) is reduced to one system, and the number of elements is also reduced by one for each MOS transistor constituting the feedback switch and one MOS transistor constituting the transfer switch. Therefore, the area of the peripheral circuit portion is further reduced.

  By replacing the one shown in FIG. 3A with the one shown in FIG. 3B, the opening of the sensor cell portion is slightly reduced. However, the center of gravity of each pixel of the AF sensor does not change. Further, by raising the lower end of the peripheral circuit, it becomes possible to place an eye that overlaps in the empty space in FIG. The effect of being able to place another eye is much greater than the disadvantage of sacrificing some sensitivity. In the above description, the configuration of the arrangement of three rows has been described as an example. However, the effect of reducing the circuit area is improved as the number of rows increases, and the peripheral circuit area is reduced when the arrangement is several tens of rows. Obviously, the effect is even greater.

  As described above, when the photoelectric conversion device according to the present embodiment is applied to an AF sensor, the peripheral circuit area is reduced by reducing the number of elements, so that more pixels can be arranged with high density while maintaining the optical system specifications. It becomes possible. Therefore, it is easy to increase the number of AF distance measurement points, and it is possible to provide an AF sensor in which the number of AF distance measurement points is increased at a low cost by preventing an increase in the chip area.

(Second Embodiment)
Next, a second embodiment of the present invention will be described.
FIG. 5 is a schematic diagram showing a part of the configuration of an area type AF sensor layout to which the photoelectric conversion device according to the second embodiment is applied, and shows an example in which the layout is arranged in a different arrangement order from FIG. Yes.

  As is clear from FIG. 1, the photoelectric conversion device according to the embodiment of the present invention has the sensor cell unit and the memory cell unit connected in parallel when viewed from the transfer circuit unit. Therefore, the freedom degree of arrangement | positioning of the sensor cell part and memory cell part seen from the transfer circuit part is high.

  In the second embodiment, the memory cell unit array in which the memory cell units 14 are arranged in an array is arranged on the side opposite to the transfer circuit unit 13 across the sensor cell unit array in which the sensor cell units 10 are arranged in an array. . That is, the memory cell unit array, the sensor cell unit array, and the transfer circuit unit 13 are arranged in this order.

  Although not shown, it is also possible to arrange a memory cell unit array between the sensor cell unit array and the transfer circuit unit 13. That is, the sensor cell unit array, the memory cell unit array, and the transfer circuit unit 13 can be arranged in this order.

  In this way, the circuit configuration as shown in FIG. 1 increases the degree of freedom in the layout of the peripheral circuit portion. That is, since it is possible to disperse and arrange the area occupied by the peripheral circuit portion, it is possible to realize a high-density arrangement of the sensor cell portion array. In FIG. 5, the configuration of the arrangement of three rows is illustrated. However, the effect of reducing the circuit area is improved as the number of rows is increased, and the effect of reducing the peripheral circuit area is further increased when the arrangement is several tens of rows. It is clear that it will grow.

  As described above, when the photoelectric conversion device according to the present embodiment is applied to an AF sensor, the peripheral circuit area is reduced by reducing the number of elements, so that more pixels can be arranged with high density while maintaining the optical system specifications. It becomes possible. Therefore, it is easy to increase the number of AF distance measurement points, and it is possible to provide an AF sensor in which the number of AF distance measurement points is increased at a low cost by preventing an increase in the chip area.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed as being limited thereto. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

PD photodiode M11 to M13, M23, M31, M32 P-channel MOS transistor M21, M22, M24 N-channel MOS transistor CT transfer capacity CM frame memory capacity SC sensor cell part TC transfer circuit part MC memory cell part CL common output line 10 sensor cell part DESCRIPTION OF SYMBOLS 11 Sensor part 12 Pixel amplifier 13 Transfer circuit part 14 Memory cell part 15 Shift register

Claims (8)

A sensor cell unit that inverts and amplifies a signal obtained by photoelectric conversion; and
A memory cell unit that stores the signal, inverts and amplifies it, and outputs it;
A common output line to which the sensor cell unit and the memory cell unit are connected is connected to a first node, and the sensor cell unit has a transfer capacitor connected to the first node via a first switch, And a transfer circuit unit for transferring a signal output from the memory cell unit,
A photoelectric conversion device comprising: an interconnection point between the first switch and the transfer capacitor; and a second switch connected to a power source.   The photoelectric conversion device according to claim 1, wherein the sensor cell unit and the memory cell unit share a load element of an inverting amplifier that performs the inverting amplification. The transfer circuit unit includes a transfer amplifier having an input unit connected to the transfer capacitor,
3. The photoelectric conversion device according to claim 1, wherein an output unit of the transfer amplifier is connected to the first node via a third switch.   The sensor cell unit and the memory cell unit corresponding to the sensor cell unit are arranged adjacent to each other, and the sensor cell unit and the memory cell unit are arranged alternately. The photoelectric conversion device according to any one of the above.   The sensor cell unit array in which the sensor cell units are arranged in an array and the memory cell unit array in which the memory cell units are arranged in an array are arranged adjacent to each other. The photoelectric conversion apparatus of Claim 1.   The photoelectric conversion device according to claim 5, wherein the memory cell unit array, the sensor cell unit array, and the transfer circuit unit are arranged in this order.   6. The photoelectric conversion device according to claim 5, wherein the sensor cell unit array, the memory cell unit array, and the transfer circuit unit are arranged in this order.   8. The photoelectric device according to claim 1, wherein the second switch is a switch that resets the sensor cell unit, the memory cell unit, the transfer capacitor, and the common output line. 9. Conversion device.

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