JP2005150125A - Solid state image sensor and charge discharger - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize switching of a high resolution mode and a low resolution mode in a high speed operation CCD linear image sensor. <P>SOLUTION: In a solid state image sensor, a charge discharger 109 has a drain 110 and a discharge gate 111 for discharging a charge in the low resolution mode. A discharge channel 206 for transferring the discharging charge is formed in the lower part of the discharge gate 111. The channel width W3a of the input side of the discharge channel 206 is formed so as to become smaller than the channel width W1 of the transfer channel 205 of a second CCD register 106. The channel width W3b of the drain side is formed to become larger than the channel width W3b of the transfer electrode 203 side. Thus, since an electric field directed toward the drain side is strengthened, it prevents the charge from overflowing to the output side in a charge discharging process. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to charge discharge of charges transferred through a charge transfer unit, and more particularly, to a charge discharge unit that discharges charge of a charge transfer unit and a solid-state imaging device including the same.

  A CCD linear image sensor formed on a semiconductor substrate and having a charge transfer function converts light received by a pixel array including photodiodes into signal charges by photoelectric conversion, and sequentially converts the signal charges accumulated in each pixel. By outputting, image information is acquired. The CCD linear image sensor having such a function is widely used as a key device for an optical reading portion of a scanner or a copier.

  In a solid-state imaging device that reads an image with a two-line pixel array, a technique for speeding up reading at a low density without causing deterioration in image quality or an increase in circuit scale is known (see, for example, Patent Document 1). ). A charge discharge drain for discharging signal charges is connected to one line via a discharge gate. When reading an image at a high density, the discharge gate is turned off, and all signal charges read by two lines are transferred to the charge detection unit. When reading an image at a low density, the transfer of the signal charge at the transfer electrode at the final stage is stopped, while the gate of the discharge gate is turned on, and the signal charge read by two lines is externally output from one CCD shift register. Only the signal charge from the other CCD shift register is transferred to the charge detection unit.

  FIG. 5 is a plan view showing a schematic configuration of a conventional CCD linear image sensor 500. The CCD linear image sensor 500 includes two photodiode rows, a first photodiode row 501 and a second photodiode row 502. Charges accumulated by photoelectric conversion of the first and second photodiode rows 501 and 502 are respectively transmitted through the first readout gate 503 and the second readout gate 504 controlled by the control signal φTG. Read out to the CCD register 505 and the second CCD register 506.

  The first and second CCD registers 505 and 506 are driven by a two-phase driving method, and the registers 505 and 506 transfer charges to the output circuit unit 507 in accordance with the driving pulses φ1 and φ2. The transferred charge is output from the output circuit portion 507 to an external circuit. The CCD linear image sensor 500 has two modes, a low resolution mode and a high resolution mode. In the high resolution mode, charges from the first and second CCD registers 505 and 506 are alternately displayed. The output is sequentially output to the output circuit 507. In the low resolution mode, the charge from the first CCD register 505 is transferred to the output circuit unit 507, and the charge from the second CCD register 506 is discharged to the charge discharge unit 508. The The charge discharging unit 508 has a drain 509 for discharging charges and a gate 510 for controlling discharge of charges to the drain.

  FIG. 6 is a plan view showing a schematic configuration of the charge discharging unit 508 and the second CCD register 506 in the vicinity thereof. The second CCD register 506 includes a plurality of first transfer electrodes 601 to which a first drive pulse φ1 is applied and a second plurality of transfer electrodes 602 to which a second drive pulse φ2 is applied. (Only part of the figure is shown). The first transfer electrodes 601 and the second transfer electrodes 602 are alternately arranged.

  The charge discharging portion 508 is formed adjacent to the transfer electrode 603 that is one of the first transfer electrodes. Further, an output-side transfer electrode 604 that is one of the second transfer electrodes is formed on the output circuit portion 507 side of the charge discharging portion 508. A transfer channel 605 for transferring charges is formed below the transfer electrodes 601-604. The channel width of the transfer channel 605 is indicated by W1. In the charge discharging unit 508, a discharge channel 606 for transferring discharged charges is formed below the discharge gate 510. The channel width of the drain 509 is indicated by W2. The channel width of the discharge channel 606 is indicated by W3.

  A drive pulse φ1A is applied to the transfer electrode 603 to which the charge discharging unit 508 is connected. A discharge gate control signal φSW is applied to the discharge gate 510. In the high resolution mode, the control signal φSW is applied so that the discharge gate 510 is turned off. The channel width W3 of the discharge channel 606 is narrower than the channel width W1 of the transfer channel 605. Therefore, due to the narrow channel effect, the channel potential of the discharge channel 606 becomes shallower than the channel potential of the transfer channel 605 below the transfer electrode 603, and the transfer charge is transferred to the output circuit portion 507.

  In the low resolution mode, the discharge gate 510 is set to an ON state, and φ1A applied to the discharge gate 510 and the transfer electrode 603 is fixed at the same potential. The channel potential of the discharge channel 606 becomes shallower than the channel potential of the transfer channel 605 below the transfer electrode 603 due to the narrow channel effect. The charge transferred through the CCD register is first stored below the transfer electrode 603, and the charge stored more than the channel potential difference between the discharge gate 510 and the transfer electrode 603 is discharged to the drain 509 through the discharge channel 606. .

FIG. 7 is a plan view showing a schematic configuration of the charge discharging unit 508 and the second CCD register 506 in the vicinity thereof. A P-type impurity is implanted into the N-type silicon substrate 701 to form a P well 702. An N-type channel region 703 is formed on the P well 702, and a thermal oxide film 704, a discharge gate electrode 510 made of polycrystalline silicon, and a transfer electrode 603 are formed. An N ⁺ region 705 is provided in the periphery of the drain 509, and by applying a power supply voltage, the channel potential becomes deeper than that of the periphery, and the electric charge that has reached here is discharged. Since the drain is provided with an N ⁺ region 705 and a power supply unit for power supply voltage, the channel width W2 of this region may be larger than the channel width W3 of the discharge channel due to layout restrictions.

JP 2000-244819 A

When the N ⁺ region 705 approaches the discharge gate 510, the channel potential here becomes high due to the modulation, and even if the discharge gate 510 is turned off, it is discharged to the drain 509. Therefore, the influence of the modulation can be ignored. Need to be separated. When discharging to the drain 509, even after passing through the discharge channel 606, it takes time to discharge to the drain 509 because it passes through the high resistance N channel 703.

  In addition, the charge discharging unit 508 discharges charges to the drain 509 using the narrow channel effect of the discharge channel 606. Therefore, the channel width of the discharge channel 606 cannot be increased too much. For this reason, when discharging the charge to the drain 509, the discharge speed of the charge is limited by the speed of the charge passing through the discharge channel 606. If the charge is discharged to the drain 509 while the CCD register 506 is operating at high speed, a large amount of charge flows into the discharge channel 606, which may overflow the charge and spill out on the output circuit portion 507 side.

  The present invention has been made against the background described above, and one object of the present invention is to effectively discharge charges from the charge transfer section to the charge discharge section in the solid-state imaging device. is there. Another object of the present invention is to effectively switch between high resolution and low resolution in a solid-state imaging device that reads an image with a two-line pixel array. Another object of the present invention is to more reliably perform high-speed operation in a linear image sensor that switches between high resolution and low resolution.

  A first aspect of the present invention is a solid-state imaging device, which includes a plurality of pixels, and each of the plurality of pixels generates a charge corresponding to light received, and is generated by the charge generation unit. A charge transfer unit for transferring the charged charge, a charge detection unit for detecting the charge transferred by the charge transfer unit, and a charge discharge unit for discharging the charge not transferred to the charge detection unit from the charge transfer unit. The charge discharging unit includes a drain from which charges are discharged and a discharge gate for controlling discharge of charges to the drain, and the charge discharging unit includes a first channel at a lower portion of the discharge gate. And a second channel portion formed on the drain side of the first channel portion and having a channel width wider than that of the first channel portion. By having this configuration, charges can be effectively discharged.

  The solid-state imaging device according to the first aspect includes a plurality of pixels, and each of the plurality of pixels generates a charge corresponding to light received by the second charge generation unit and the second charge generation unit. A second charge transfer unit that transfers the generated charge, and in the high resolution mode, the charge transferred by the charge transfer unit and the second charge generation unit is transferred to the charge detection unit, In the low resolution mode, it is preferable that the charge discharging unit discharges charges not transferred to the charge detection unit from the charge transfer unit. With this configuration, selective imaging with high resolution and low resolution can be effectively performed.

  Preferably, the second channel portion includes a drain side end portion below the discharge gate, and the channel width of the second channel portion is formed so as to gradually increase toward the drain. . Furthermore, the channel width of the drain is increased on the opposite side of the charge detection portion, and the channel width of the second channel portion is gradually increased toward the drain on the opposite side of the charge detection portion. It is preferable that it is formed to be large. By having this configuration, electric charges can be discharged more effectively.

  The channel width of the first channel portion is preferably smaller than the channel width of the charge transfer portion so that the charge transfer portion transfers charges to the charge detection portion due to a narrow channel effect. With this configuration, the transfer charge can be effectively transferred to the charge detection unit.

  The charge transfer unit includes a plurality of transfer electrodes that sequentially transfer charges, and the transfer electrode is configured to transfer charges to a transfer electrode adjacent to the charge discharge unit in the process of discharging the charge by the charge discharge unit. Preferably, a drive signal is applied to the discharge gate, and a control signal is applied to the discharge gate so that the discharge gate is turned on. Thereby, electric charges can be discharged effectively.

  In the process of discharging the charge by the charge discharging unit, a drive signal is applied to the transfer electrode at the next stage of the transfer electrode adjacent to the charge discharging unit so as to prevent the transfer of the charge to the transfer electrode at the next stage. It is preferable. Thereby, it is possible to more effectively suppress the charge from being transferred to the charge detection unit side.

  According to a second aspect of the present invention, there is provided a charge discharging unit that discharges charges transferred by a charge transfer unit that sequentially transfers charges in accordance with a control signal, the drain from which charges are discharged, and the charge to the drain. A discharge gate for controlling discharge; a first channel portion having a channel width smaller than that of the channel of the charge transfer portion; and a drain side of the first channel portion at a lower portion of the discharge gate, And a second channel portion having a channel width wider than that of the first channel portion. As a result, the transfer charge from the charge transfer unit can be effectively discharged.

  According to the present invention, it is possible to effectively discharge charges from the charge transfer unit to the charge discharging unit.

  Hereinafter, embodiments to which the present invention can be applied will be described. The following description is to describe the embodiment of the present invention, and the present invention is not limited to the following embodiment. For clarity of explanation, the following description and drawings are omitted and simplified as appropriate. Moreover, those skilled in the art can easily change, add, and convert each element of the following embodiments within the scope of the present invention.

  FIG. 1 shows a schematic configuration of a CCD linear image sensor 100 according to this embodiment as an example of the present invention. In FIG. 1, reference numeral 101 denotes a first photodiode row that forms a plurality of pixels, 102 denotes a second photodiode row that forms a plurality of pixels, 103 denotes a first reading gate, 104 denotes a second reading gate, Reference numeral 105 denotes a first CCD register, 106 denotes a second CCD register, 107 denotes an output gate, and 108 denotes an output circuit unit.

  Charges accumulated by photoelectric conversion of the first and second photodiode arrays 101 and 102 are transferred to the output circuit unit 108 by the CCD registers 105 and 106 and output to an external circuit. The CCD linear image sensor 100 has two modes, a low resolution mode and a high resolution mode. In the high resolution mode, charges from the first and second CCD registers 105 and 106 are alternately displayed. The charges are sequentially output to the output circuit 108. In the low resolution mode, the charge from the first CCD register 105 is transferred to the output circuit, and the charge from the second CCD register 106 is discharged to the charge discharging unit 109.

  The configuration of the CCD linear image sensor 100 will be described in detail with reference to FIG. In each of the first and second photodiode rows 105 and 106, a plurality of photodiodes are arranged in one direction, and the arrangement pitch of the photodiodes in both photodiode rows 101 and 102 is the same. The first photodiode array 101 and the second photodiode array 102 are arranged in parallel in a positional relationship shifted by a half pitch. Light incident from the outside is received by each photodiode, and charges generated by photoelectric conversion according to the amount of incident light are accumulated in each pixel.

  The first read gate 103 controls reading of accumulated charges from the first photodiode array 105 to the first CCD register 105. Similarly, the second readout gate 104 controls reading of accumulated charges from the second photodiode array 106 to the second CCD register 106. The first and second read gates 103 and 104 are set to an ON or OFF state by a drive signal φTG, thereby controlling charge accumulation or accumulated charge readout.

  The first and second CCD registers 105 and 106 have a function of sequentially transferring charges read from the first and second photodiode arrays, respectively. In this embodiment, CCD registers 105 and 106 are two-phase drive type CCD registers. In the CCD register of the two-phase driving system, the first driving pulse φ1 and the second driving pulse φ2 are alternately applied, so that the electric charge corresponding to each pixel read out is output to the output circuit unit 108 according to the driving signal. Sequentially forward toward The first CCD register 105 and the second CCD register 106 are coupled on the output side, and output charges from the CCD registers 105 and 106 are alternately output to the output circuit unit 108 in the high resolution mode. The

  The output circuit unit 108 is formed of a floating diffusion region, and includes a signal charge detection unit that converts a signal charge into a signal voltage, and an analog circuit including a source follower, an inverter, and the like. The output charges from the CCD registers 105 and 106 are converted into a signal voltage in the floating diffusion region, and are output from the output circuit unit 108 to an external circuit via an analog circuit. The output of charges from the CCD registers 105 and 106 to the output circuit unit 108 is controlled by the output gate 107.

  The second CCD register 106 is formed with a charge discharging portion 109 for discharging charges that are not transferred to the output circuit portion 108 in the low resolution mode. The charge discharging unit 109 is formed in the vicinity of the output end of the second CCD register 106, and is branched to the side of the second CCD register 106. The charge discharging unit 109 includes a drain 110 from which charges are discharged, a channel 111 in a direction different from the output direction of the second CCD register 106, and a discharge gate 112. In the high resolution mode, the discharge gate 112 is set off, and the transfer charge of the second CCD register 106 is transferred to the output circuit unit 108 without being transferred to the drain 110. In the low resolution mode, the discharge gate 112 is set to ON, and the transfer charge of the second CCD register 106 is discharged to the drain 110 without being transferred to the output circuit unit 108.

  The operation of the CCD linear image sensor 100 will be described. FIG. 2 is a timing chart showing the timing of control signals applied to the CCD linear image sensor 100. 2A is a timing chart in the high resolution mode, and FIG. 2B is a timing chart in the low resolution mode. φ1 and φ2 are a first drive pulse and a second drive pulse that are applied to the first and second CCD registers 105 and 106 as two-phase drive pulses. φ1A and φ2A will be described later. φSW is a discharge gate control signal applied to the discharge gate 112.

  When the first and second photodiode arrays 101 and 102 receive light, each photodiode generates a charge by photoelectric conversion in accordance with the incident light intensity. The first and second readout gates 103 and 104 are turned off by the control signal φTG, and the charges generated in the first and second photodiode rows 101 and 102 are accumulated in each pixel. Next, the first and second readout gates 103 and 104 are set to the on state by the control signal φTG, and the charges accumulated in the pixels of the first and second photodiode columns 101 and 102 are the first And are simultaneously read by the second CCD registers 105 and 106.

  The operation in the high resolution mode will be described. A first drive pulse φ1 and a second drive pulse φ2 are applied to the first and second CCD registers 105 and 106 as two-phase drive pulses. The first drive pulse φ1 and the second drive pulse φ2 are applied to the plurality of first transfer electrodes and the plurality of second transfer electrodes of the first and second CCD registers 105 and 106, respectively. The transfer electrode will be described later. As shown in FIG. 2A, the first drive pulse φ1 and the second drive pulse φ2 are different in phase by 180 degrees, and the first and second CCD registers 105 are alternately switched so that their H levels are alternately switched. , 106. The first and second CCD registers 105 and 106 sequentially transfer the read charges to the output circuit unit 108 side in synchronization with the drive pulse.

  As shown in FIG. 2A, the discharge gate control signal φSW is at the L level, and the discharge gate 112 is set in the OFF state. Therefore, the transfer charge of the second CCD register 106 is transferred to the output circuit unit 108. Transfer charges from the first CCD register 105 and the second CCD register are alternately and sequentially input to the output circuit unit 108 according to the two-phase drive pulse. The output circuit unit 108 converts the input signal charge into a signal voltage and outputs it to an external circuit.

  In the low resolution mode, as shown in FIG. 2B, the discharge gate control signal φSW is at the H level, and the discharge gate 112 is set to the on state. The charge transferred through the second CCD register 106 is discharged to the drain 110. As shown in FIG. 2B, a first drive pulse φ1 and a second drive pulse φ2 are applied to each of the first and second CCD registers 105 and 106 as a two-phase drive pulse. The timing of the drive pulses φ1 and φ2 is the same as in the high resolution mode.

  In synchronization with the drive pulses φ1 and φ2, the first and second CCD registers 105 and 106 transfer the read charges to the output circuit unit 108 side. As described above, the discharge gate 112 is set to the ON state, and the transfer charge of the second CCD register 106 is discharged to the charge discharge unit 109. The transfer charge from the first CCD register 105 is input to the output circuit unit 108 in accordance with the drive pulses φ1 and φ2. As a result, a low-resolution image signal is output.

  FIG. 3 is a plan view showing a schematic configuration in the vicinity of the charge discharging unit 109 and the charge discharging unit 109 of the second CCD register 106. FIG. 4A is a cross-sectional view showing a part of the configuration related to the portion indicated by arrow a-a ′ in FIG. 3. FIG. 4B shows the channel potential of each part in the cross-sectional structure shown in FIG. Referring to FIG. 3, the second CCD register 106 includes a plurality of first transfer electrodes 201 to which the first drive pulse φ1 is applied and a plurality of second transfer electrodes to which the second drive pulse φ2 is applied. A transfer electrode 202 (a part of which is illustrated in the figure).

  The first transfer electrodes 201 and the second transfer electrodes 202 are alternately arranged. Each of the first and second transfer electrodes 201 and 202 is constituted by two layers of electrodes, and the first transfer electrode 201 is constituted by a barrier electrode (not shown) and a storage electrode 201b, and the second transfer electrode. The electrode 202 includes a barrier electrode 202a and a storage electrode 202b. In charge transfer, charges are accumulated below the storage electrode, and the lower part of the barrier electrode functions as a barrier layer.

  As shown in FIG. 3, the charge discharging unit 109 is formed adjacent to the transfer electrode 203 which is one of the first transfer electrodes. The transfer electrode 203 includes a barrier electrode 203a and a storage electrode 203b. Further, an output-side transfer electrode 204 that is one of the second transfer electrodes is formed on the output circuit unit 108 side of the charge discharging unit 109. The output transfer electrode 204 includes a barrier electrode 204a and a storage electrode 204b. A transfer channel 205 for transferring charges is formed below the transfer electrodes 201-204. The channel width of the transfer channel 205 is indicated by W1.

  The charge discharging unit 109 includes a drain 110 that discharges charges and a discharge gate 111 in the low resolution mode. A discharge channel 206 for transferring discharged charges is formed below the discharge gate 111. The channel width of the drain 110 is indicated by W2. As for the channel width of the discharge channel 206, the channel width at the discharge charge input portion on the transfer electrode 203 side is indicated by W3a, and the channel width at the drain side end is indicated by W3b. In this embodiment, the channel width W3a on the input side of the discharge channel 206 is formed to be smaller than the channel width W1 of the transfer channel 205 of the second CCD register 106. Further, the drain channel 206 is formed such that the drain side channel width W3b is larger than the channel width W3a on the transfer electrode 203 side.

  A first drive pulse φ 1 is applied to the first transfer electrode 201, and a second drive pulse φ 2 is applied to the second transfer electrode 202. However, the drive pulse φ1A is applied to the transfer electrode 203 which is the first transfer electrode to which the charge discharging unit 109 is connected. Further, the drive pulse φ2A is applied to the output transfer electrode 204 which is one of the second transfer electrodes. A discharge gate control signal φSW is applied to the discharge gate 111.

  As shown in the sectional view of FIG. 4, the structure in the vicinity of the charge discharging portion 109 and the transfer electrode 203 is formed on an N-type silicon substrate 401. On the N-type silicon substrate 401, a P-well 402 formed by injecting P-type impurities into the N-type silicon substrate is disposed. An N-type channel region 403 is formed on the P well 402, and the upper surface of the N-type channel region 403 is covered with a thermal oxide film 404. An electrode is formed of polycrystalline silicon on the thermal oxide film 404, and each of the discharge gate 111 and the transfer electrode 203 is formed on the N-type channel region 403 through the thermal oxide film 404.

On the second CCD register 106 side (opposite the drain), a P ⁺ region 406 is formed in a part of the lower portion of the transfer electrode 203. An N ⁺ region 405 is formed in the periphery of the drain 110. As shown in FIG. 4B, when a power supply voltage is applied to the drain 110, the channel potential becomes deeper than the periphery of the drain 110, and the electric charge reaching here is discharged to an external circuit.

  With reference to FIG. 4B, the channel potential in the high resolution mode and the low resolution mode, and the charge transfer process by the channel potential will be described. In FIG. 4B, 451 indicates the channel potential in the high resolution mode, and 452 indicates the channel potential in the low resolution mode. In FIG. 4B, the X-axis indicates the position on the N-type silicon substrate, and the Y-axis indicates the channel potential at each position on the N-type silicon substrate. The position shown on the X-axis corresponds to the cross-sectional view of FIG. In addition, the channel potential is described so that the channel potential increases toward the lower side of the drawing on the Y axis.

  As shown in FIG. 2A, in the high resolution mode, an L level φSW signal is given to the discharge gate 111, and the discharge gate 111 is set to an off state. Control signals φ1 and φ2 applied to the transfer electrode 203 and the output transfer electrode are the same as the two-phase drive pulses φ1 and φ2, respectively. The discharge channel 206 of the charge discharging unit 109 and the transfer channel 205 of the second CCD register 106 are formed so that the discharge channel 206 causes a narrow channel effect. The channel width W3a of the charge discharging unit 109 is formed to be smaller than the channel width W1 of the second CCD register 106.

  In the high resolution mode, the discharge gate 111 is given an L level φSW signal. The channel potential of the charge discharging unit 109 becomes lower than the channel potential below the transfer electrode 203 due to the narrow channel effect. Therefore, the charge in the second CCD register 106 is transferred to the output circuit unit 108 side. In FIG. 4, the channel potential Va of the charge discharging unit 109 when the L level φSW signal is applied and the lower part of the transfer electrode 203 of the second CCD register 106 when the L level φ1A is applied. A channel potential Vb is shown. As understood from FIG. 4, the channel potential Va of the charge discharging unit 109 is always smaller than the channel potential Vb of the second CCD register 106 due to the narrow channel effect.

  As shown in FIG. 2B, in the low resolution mode, the discharge gate 111 is supplied with the H level φSW signal, and the discharge gate 111 is set to the ON state. To the transfer electrode 203 adjacent to the charge discharging unit 111, an H level signal φ1A, which is a drive signal for transferring charges to the transfer electrode 203, is applied. Preferably, the L-level signal φ2A is applied to the output-side electrode 204. Thus, control is performed so that the accumulated charge is not transferred to the output circuit unit 108 side. In this example, an H level signal having the same potential as that of the discharge gate 111 is applied to the transfer electrode 203 and is fixed at that potential. The channel potential of the channel 206 of the charge discharging unit 109 becomes lower than the channel potential of the transfer electrode 203 of the second CCD register 106 due to the narrow channel effect.

  FIG. 4B shows the channel potential Vc of the charge discharging unit when the H level φSW signal is applied and the channel potential Vd of the second CCD register when the H level φ1A is applied. Has been. In this example, these are the same potential. As shown in FIG. 4B, the channel potential Vc of the charge discharging unit 109 is lower than the channel potential Vd of the second CCD register 106. For this reason, the charges transferred through the second CCD register 106 are first stored in the lower portion of the transfer electrode 203, and electrons accumulated more than the potential difference between the channel potential of the transfer electrode 203 and the channel potential of the discharge gate 111 are The charge is discharged to the drain 110 through the discharge channel 206 of the charge discharging unit 109.

  In this embodiment, as shown in FIG. 3, the charge discharging portion 109 has a channel portion having a wider channel width on the drain 110 side than the channel portion on the second CCD register 106 side. Specifically, the discharge channel 206 has a channel width gradually increasing from the channel portion on the second CCD register 106 side having substantially the same channel width W3a and the channel width W3b at the channel end portion on the drain 110 side. And a channel portion on the drain 110 side that is formed. Thus, the channel width W3b on the drain side is larger than the channel width W3a on the second CCD register 106 side.

  For this reason, the potential becomes higher on the drain 110 side as compared with the conventional charge discharging portion having a channel having the same channel width. In FIG. 4, the channel potential Vc ′ in the conventional charge discharging portion is illustrated for comparison. Thus, in this embodiment, since the channel width is widened near the drain 110, the potential near the drain 110 becomes deeper, and the electric field in the direction of the drain 110 with respect to the electric charge is strengthened. As a result, it is possible to substantially prevent charges from being effectively discharged to the drain 110 and transferred to the output circuit unit 108 side. In particular, in a CCD linear image sensor that operates at high speed, the charge discharging process for the low resolution mode can be effectively performed.

  On the other hand, the channel width W3a on the second CCD register side is smaller than the channel width W1 of the transfer channel, and the channel width of the charge discharging unit is not widened as a whole. For this reason, when charge is transferred to the output circuit unit 108 in the high resolution mode, the channel potential Va of the charge discharging unit becomes shallower than the transfer channel 205 due to the narrow channel effect, and the channel potential in the conventional charge discharging unit is reduced. It is not substantially different from Va ′. Thereby, in the high resolution mode, the charge is not easily discharged to the drain 110, and the charge can be transferred to the output circuit unit.

  The channel width of the discharge channel 206 is preferably formed so as to gradually increase toward the drain 110 on the drain 110 side. As a result, an undesired potential change due to a sudden channel width change can be prevented, and the electric field can be effectively strengthened. The drain 110 has a convex portion on the side opposite to the output circuit portion 108 side, and the drain channel 206 has a channel width gradually increasing toward the side opposite to the output circuit portion 108 side on the drain 110 side. It is formed to become. As a result, the layout of the power supply unit for the power supply voltage connected to the drain can be efficiently performed.

  In the low resolution mode, the drive signal φ2A at an L level is preferably applied to the output transfer electrode 204, and a drive signal is applied so as to prevent transfer of charge to the output transfer electrode 204. By applying a control signal that prevents charge transfer to the output-side transfer electrode 204 to the output-side transfer electrode 204 and fixing it to the potential, the charge of the second CCD register 106 is output in the output circuit in the low resolution mode. Spilling to the side of the portion 108 can be more effectively prevented.

  In this example, the channel width of the discharge channel 206 formed below the discharge gate 105 is formed so as to gradually increase. However, for example, there is a step where the channel width increases from W3a to W3b. It is also possible to form it. In this case, for example, the channel portion on the drain side of the discharge channel 206 is formed so as to maintain the width of W3b. In this example, the channel width is widened on the opposite side of the discharge channel 206 from the output circuit unit 108, but the channel width can be widened on both sides of the channel or in the output circuit unit 108. In the discharge channel 206, a suitable part of the channel or a part in which the channel width is widened can be selected according to the design.

1 is a plan view showing a schematic configuration of a CCD linear image sensor in the present embodiment. 6 is a timing chart showing the timing of control signals in the CCD linear image sensor in the present embodiment. It is a top view which shows schematic structure of the electric charge discharge part and its vicinity in this Embodiment. FIG. 4 is a cross-sectional view showing a schematic configuration of a charge discharging portion and its vicinity and a channel potential in the present embodiment. It is a top view which shows schematic structure of the CCD linear image sensor in a prior art. It is a top view which shows schematic structure of the electric charge discharge part and its vicinity in a prior art. It is sectional drawing which shows schematic structure of the electric charge discharging part and its vicinity in a prior art.

Explanation of symbols

100 CCD linear image sensor,
101 first photodiode row, 102 second photodiode row,
103 first read gate, 104 second read gate,
105 first CCD register, 106 second CCD register,
107 output gate, 108 output circuit section, 109 charge discharging section,
110 drain, 111 discharge channel, 112 discharge gate,
201 first transfer electrode, 202 second transfer electrode, 203 transfer electrode,
204 Output side transfer electrode, 205 transfer channel, 206 discharge channel

Claims (8)

A charge generation unit that includes a plurality of pixels, and generates a charge according to light received by each of the plurality of pixels;
A charge transfer unit that transfers the charge generated by the charge generation unit;
A charge detection unit for detecting charges transferred by the charge transfer unit;
A charge discharging unit that discharges charges not transferred to the charge detection unit from the charge transfer unit;
With
The charge discharge unit includes a drain from which charges are discharged, and a discharge gate that controls discharge of charges to the drain.
The charge discharging portion is formed at a lower portion of the discharging gate at a first channel portion and on the drain side than the first channel portion, and a second channel having a channel width wider than that of the first channel portion. Having a channel part,
Solid-state imaging device. A second charge generation unit that includes a plurality of pixels, and generates a charge according to light received by each of the plurality of pixels;
A second charge transfer unit that transfers charges generated by the second charge generation unit;
Further comprising
In the high resolution mode, the charges transferred by the charge transfer unit and the second charge generation unit are transferred to the charge detection unit,
In the low resolution mode, the charge discharging unit discharges the charge not transferred to the charge detecting unit from the charge transferring unit.
The solid-state imaging device according to claim 1. The second channel part includes a drain side end part below the discharge gate,
The solid-state imaging device according to claim 1, wherein a channel width of the second channel portion is formed so as to gradually increase toward the drain. The drain has a channel width enlarged on the opposite side of the charge detection unit,
The channel width of the second channel part is formed so that the channel width gradually increases toward the drain on the opposite side of the charge detection part.
The solid-state imaging device according to claim 3.   2. The channel width of the first channel portion is formed smaller than the channel width of the charge transfer portion so that the charge transfer portion transfers charges to the charge detection portion due to a narrow channel effect. 5. The solid-state imaging device according to any one of 1 to 4. The charge transfer unit includes a plurality of transfer electrodes for sequentially transferring charges,
In the process of discharging the charge by the charge discharging unit, a drive signal for transferring the charge to the transfer electrode is applied to the transfer electrode adjacent to the charge discharging unit, so that the discharge gate is turned on. A control signal is applied to the discharge gate,
The solid-state imaging device according to claim 1. The charge transfer unit includes a plurality of transfer electrodes for sequentially transferring charges,
In the process of discharging the charge by the charge discharging unit, a drive signal is applied to the transfer electrode at the next stage of the transfer electrode adjacent to the charge discharging unit so as to prevent the transfer of the charge to the transfer electrode at the next stage. The solid-state imaging device according to claim 1, wherein A charge discharging unit that discharges the charge transferred through the charge transfer unit that sequentially transfers the charge according to the control signal,
A drain from which charges are discharged;
A discharge gate for controlling discharge of charge to the drain;
A first channel portion having a channel width smaller than a channel of the charge transfer portion at a lower portion of the discharge gate;
A second channel portion formed on the drain side of the first channel portion and having a channel width wider than that of the first channel portion;
A charge discharging unit.

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