JP2006050403A - Solid-state imaging device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging device capable of reading signals at high speed coming from all photoelectric conversion cells. <P>SOLUTION: The solid-state imaging device comprises a photoelectric conversion cells C1 and the like, having photoelectric converters 101a and the like, which are arranged to form a line and perform photoelectric conversion. A line group is formed of a plurality of photoelectric conversion cells which are included in the same line and adjacent to each other. Transfer transistors 121a, 221a, 321a, and the like in the photoelectric cells C1, C2, C3, and the like of the same group are controlled by a common read pulse line 131a. This structure enables simultaneously reading out of three lines of signals. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a solid-state imaging device in which a plurality of photoelectric conversion units are arranged.

  An example of the configuration of a conventional MOS (Metal Oxide Semiconductor) image sensor (for example, described in Patent Document 1) is shown as a circuit diagram in FIG.

  The conventional MOS type image sensor shown in FIG. 10 has an imaging region 12 in which a plurality of photoelectric conversion cells 11 are arranged in a matrix and a vertical direction in which a vertical direction is selected from among the plurality of arranged photoelectric conversion cells 11. A shift register 13; a horizontal shift register 14 for selecting a horizontal direction from the plurality of photoelectric conversion cells 11 arranged; and a timing generation circuit 15 for supplying a pulse to the vertical shift register 13 and the horizontal shift register 14. It is provided on a substrate (not shown).

  Further, a read pulse line 21, a reset pulse line 22 and a selection pulse line 23 connected to the vertical shift register 13, a power supply line 24, and a signal line 25 connected to the horizontal shift register 14 are formed on the substrate. Yes.

  Further, each photoelectric conversion cell 11 arranged in the imaging region 12 is generated in the photoelectric conversion unit 31 composed of a photodiode, the transfer transistor 32 that transfers the charge generated in the photoelectric conversion unit 31, and the photoelectric conversion unit 31. Floating diffusion (hereinafter abbreviated as FD) unit 33 for storing charge, reset transistor 34 for sweeping out the charge accumulated in FD unit 33, and detecting the charge accumulated in FD unit 33 and outputting a signal And a selection transistor 36 that controls the timing at which the amplification transistor 35 outputs a signal.

  Here, the photoelectric conversion unit 31 has an anode grounded and a cathode connected to the source of the transfer transistor 32.

  The transfer transistor 32 has a source connected to the cathode of the photoelectric conversion unit 31, a drain connected to the FD unit 33, a source of the reset transistor 34 and the gate of the amplification transistor 35, and a gate connected to the readout pulse line 21. Yes.

  The reset transistor 34 has a source connected to the drain of the transfer transistor 32, the FD unit 33 and the gate of the amplification transistor 35, a drain connected to the power supply line 24 and the drain of the amplification transistor 35, and a gate connected to the reset pulse line 22. It is connected.

  The amplification transistor 35 has a source connected to the drain of the selection transistor 36, a drain connected to the power supply line 24 and the drain of the reset transistor 34, and a gate connected to the drain of the transfer transistor 32, the FD unit 33, and the sources of the reset transistor 34. Connected with.

  The selection transistor 36 has a source connected to the signal line 25, a drain connected to the source of the amplification transistor 35, and a gate connected to the selection pulse line 23.

  The conventional MOS image sensor described above detects light input as a signal as follows.

  In the photoelectric conversion unit 31, the input light is converted into electric charges. In a state where a predetermined voltage is applied to the signal line 25, the charge is transferred to the FD unit 33 when the transfer transistor 32 is turned on, and changes the potential of the FD unit 33. The potential of the FD section 33 is detected by the amplification transistor 35, and the amplification transistor 35 outputs a signal based on the detected potential via the signal line 25 when the selection transistor 36 is turned on.

Further, such charge reading is performed for each row by selecting individual photoelectric conversion units 31 in order by the vertical shift register 13 and the horizontal shift register 14.
USP 5471515

  However, since the conventional solid-state imaging device reads the signals from the arranged photoelectric conversion units for each row, there is a difference in the time at which each photoelectric conversion unit is read. Become. As a result, when shooting an object that moves at high speed, the position of the object changes while reading of the charge corresponding to one screen is completed, so that the captured image is distorted.

  In view of the above problems, an object of the present invention is to provide a solid-state imaging device capable of reading charges at high speed.

  In order to achieve the above object, a solid-state imaging device of the present invention is a solid-state imaging device that includes a plurality of photoelectric conversion cells that are arranged to form a matrix and each have a photoelectric conversion unit that performs photoelectric conversion. Among the plurality of photoelectric conversion cells, a plurality of column groups are configured for each set of photoelectric conversion cells included in the same column and arranged in adjacent rows, and connected to the plurality of photoelectric conversion units. And a plurality of floating diffusion portions to which charges are transferred from the plurality of photoelectric conversion portions, and a plurality of floating diffusion portions provided between the plurality of photoelectric conversion portions and the plurality of floating diffusion portions. Read pulse line for commonly controlling a plurality of transfer transistors for transferring charges to and a plurality of transfer transistors in a plurality of column groups Includes detecting the potentials of the floating diffusion portion, and a plurality of pixel amplifier transistor for outputting a signal, and a plurality of signal lines for a plurality of pixel amplifier transistor outputs a signal.

  According to the solid-state imaging device of the present invention, a plurality of transfer transistors belonging to one column group are simultaneously controlled by one readout pulse line, and output signals output from a plurality of pixel amplifier transistors belonging to the column group are respectively output. A plurality of signal lines formed individually can be output simultaneously. As a result, charges can be read from a plurality of rows at the same time, so that charges can be read from all the photoelectric conversion cells at high speed.

  In the solid-state imaging device of the present invention, among the plurality of photoelectric conversion cells, a plurality of row groups are formed for each of the plurality of adjacent photoelectric conversion cells included in the same row. A common floating diffusion unit to which charges are transferred from each photoelectric conversion unit included in the group, and a plurality of readout pulse lines are formed separately for a plurality of transfer transistors included in each row group. A pulse line is preferred.

  In this way, since a common floating diffusion part (FD part) is formed for a plurality of photoelectric conversion cells in the row group, the number of FD parts per photoelectric conversion part is reduced. From this, in addition to the effect of speeding up the reading of charges from all the photoelectric conversion units, the area of the FD unit with respect to the photoelectric conversion cells is reduced. As a result, the area of the photoelectric conversion unit with respect to the photoelectric conversion cells (the aperture ratio) ) And miniaturization of the photoelectric conversion cell can be realized.

  Further, since the readout pulse line is a plurality of readout pulse lines formed individually for a plurality of transfer transistors included in one row group, the charges of the plurality of photoelectric conversion units can be individually read out. it can.

  In the solid-state imaging device of the present invention, it is preferable that the plurality of pixel amplifier transistors and the plurality of signal lines are formed in common for each row group.

  In this way, since the pixel amplifier transistors and the signal lines are shared by the plurality of photoelectric conversion cells in the row group, the number of pixel amplifier transistors and signal lines per photoelectric conversion cell is reduced. Accordingly, the area of the pixel amplifier transistor and the signal line with respect to the photoelectric conversion cell is reduced. As a result, improvement in the aperture ratio of the photoelectric conversion unit and miniaturization of the photoelectric conversion cell can be realized.

  The solid-state imaging device of the present invention includes a plurality of switching transistors that are formed in common for each row group and that control timings at which a plurality of pixel amplifier transistors output signals, and a plurality of switching transistors that control the plurality of switching transistors. It is preferable to further include a selection pulse line.

  In this case, the switching transistor controlled by the selection pulse line can be used to control the timing at which the pixel amplifier transistor outputs a signal. In the solid-state imaging device having such a configuration, since the switching transistors and the selection pulse lines are shared by a plurality of photoelectric conversion cells in the row group, the number of the switching transistors and the selection pulse lines per photoelectric conversion cell. Has been reduced. Accordingly, the area of the switching transistor and the selection pulse line with respect to the photoelectric conversion cell is reduced. As a result, improvement in the aperture ratio of the photoelectric conversion unit and miniaturization of the photoelectric conversion cell can be realized.

  The solid-state imaging device of the present invention preferably further includes a plurality of reset means for resetting the potentials of the plurality of rotating diffusion portions.

  In this way, the potential of the floating diffusion part to which charges are transferred from the photoelectric conversion part can be adjusted.

  The reset means preferably includes a plurality of reset transistors for discharging the charges of the respective floating diffusion portions and a plurality of reset pulse lines for controlling the plurality of reset transistors, which are formed in common for each row group.

  In this way, the potential of the floating diffusion portion can be reliably adjusted, and the reset transistor and the reset pulse line are shared by a plurality of photoelectric conversion cells in the row group. The number of transistors and reset pulse lines is reduced. Accordingly, the areas of the reset transistor and the reset pulse line with respect to the photoelectric conversion cell are reduced, and as a result, improvement in the aperture ratio of the photoelectric conversion unit and miniaturization of the photoelectric conversion cell can be realized.

  The reset means preferably includes a plurality of reset transistors for discharging the charges of each floating diffusion portion and a plurality of reset pulse lines for controlling the plurality of reset transistors, which are formed in common for each column group.

  In this way, the potential of the floating diffusion portion can be reliably adjusted, and the reset transistor and the reset pulse line are shared by a plurality of photoelectric conversion cells in the column group, so that reset per photoelectric conversion cell is possible. The number of transistors and reset pulse lines is reduced. Accordingly, the areas of the reset transistor and the reset pulse line with respect to the photoelectric conversion cell are reduced, and as a result, improvement in the aperture ratio of the photoelectric conversion unit and miniaturization of the photoelectric conversion cell can be realized.

  In the solid-state imaging device of the present invention, it is preferable that at least the pitch between the plurality of photoelectric conversion units is formed at an equal pitch in at least one of the horizontal direction and the vertical direction.

  In this way, a high-quality image can be obtained based on signals detected using the photoelectric conversion units formed at an equal pitch.

  Moreover, it is preferable that the solid-state imaging device of the present invention further includes a signal processing circuit that processes signals output from the plurality of photoelectric conversion cells.

  In this way, an image can be obtained by processing the signal output by the photoelectric conversion cell.

  The solid-state imaging device of the present invention further includes a plurality of power supply lines for supplying potentials to the plurality of photoelectric conversion cells, and the plurality of power supply lines serve as a light-shielding film that prevents light from entering the floating diffusion portion. It preferably has a function.

  In this way, since the plurality of power supply lines are formed in a layer different from other wirings such as signal lines, further improvement of the aperture ratio of the photoelectric conversion unit and miniaturization of the photoelectric conversion cell can be realized.

  In the solid-state imaging device of the present invention, the output transistors from the plurality of photoelectric conversion cells are controlled by controlling the transfer transistors included in the plurality of adjacent photoelectric conversion cells in the same column by a common readout pulse line. Can be read simultaneously. Thereby, since a plurality of rows can be read out simultaneously, signals from all the photoelectric conversion cells can be read out at a higher speed as compared with the conventional solid-state imaging device that reads out one row at a time.

(First embodiment)
Hereinafter, a solid-state imaging device according to a first embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is a diagram illustrating an example of an array of photoelectric conversion cells of the solid-state imaging device according to the first embodiment.

  As shown in FIG. 1, in the solid-state imaging device of the first embodiment, photoelectric conversion cells C having a function of photoelectrically converting incident light according to intensity are arranged on a substrate S to form a matrix. is doing. In addition, a column group CG is formed by three photoelectric conversion cells C included in the same column and adjacent to each other.

  Next, FIG. 2 shows a circuit configuration of an imaging region in the solid-state imaging device according to the first embodiment. In FIG. 2, three photoelectric conversion cells of 3 rows and 1 column, in other words, three photoelectric conversion cells C1, C2, and C3 included in one column group are shown in an enlarged manner.

  First, the configuration of the photoelectric conversion cell C1 will be described.

  In the photoelectric conversion cell C1, the photoelectric conversion unit 101a, the transfer transistor 121a that transfers charges from the photoelectric conversion cell 101a, the FD unit 111 to which charges are transferred from the photoelectric conversion unit 101a, and the charges of the FD unit 111 are discharged. In other words, a reset transistor 122 that resets the potential of the FD portion 111 is formed.

  In the photoelectric conversion cell C1, the pixel amplifier transistor 123 that detects the potential of the FD unit 111 and outputs a signal corresponding to the detected potential, and the switching transistor 124 that controls the timing at which the pixel amplifier transistor 123 outputs a signal, Is formed.

  Further, a readout pulse line (READ) 131a corresponding to the photoelectric conversion cell C1, a signal line 132a for transmitting a signal output from the pixel amplifier transistor 123, a load transistor 125a for driving the pixel amplifier transistor 123, and a load transistor A load gate line (LGCELL) 133 for controlling 125a and a source power supply line (SCELL) 134 for the load transistor 125a are formed. Although not shown in the drawing, a reset pulse line 135 for controlling the reset transistor 122, a selection pulse line 136 for controlling the switching transistor 124, and a cell power line (VDDCELL) for supplying power to the photoelectric conversion cell. vdd is also formed.

  Here, the photoelectric conversion unit 101a is made of, for example, a photodiode, and the anode is grounded and the cathode is connected to the source of the transfer transistor 121a.

  The transfer transistor 121a has a source connected to the cathode of the photoelectric conversion unit 101a, a drain connected to the FD unit 111, a source of the reset transistor 122, and a gate of the pixel amplifier transistor 123, and a gate connected to the readout pulse line 131a. ing.

  The reset transistor 122 has a source connected to the drain of the transfer transistor 121a, the FD unit 111 and the gate of the pixel amplifier transistor 123, a drain connected to the cell power supply line vdd and the drain of the pixel amplifier transistor 123, and a gate connected to the reset pulse. Connected to line 135.

  The pixel amplifier transistor 123 has a source connected to the drain of the switching transistor 124, a drain connected to the cell power supply line vdd and the drain of the transfer transistor, and a gate connected to the drain of the transfer transistor 121 a, the FD unit 111, and the reset transistor 122. Connected with the source.

  The switching transistor 124 has a source connected to the signal line 132 a, a drain connected to the source of the pixel amplifier transistor 123, and a gate connected to the selection pulse line 136.

  Further, the photoelectric conversion cell C2 has the same configuration as the photoelectric conversion cell C1. In other words, the photoelectric conversion unit 201a, the transfer transistor 221a, the FD unit 211, the reset transistor 222, the pixel amplifier transistor 223, and the switching transistor 224 are provided. Further, in the photoelectric conversion cell C2, the read pulse line 131a, the signal line 132b, the reset pulse line 235, the selection pulse line 236, and the cell power line vdd are connected to predetermined positions, respectively, and the load transistor 125b is connected to the signal line 132b. Has been. Since these structures are the same as that of the photoelectric conversion cell C1, detailed description is abbreviate | omitted.

  The photoelectric conversion cell C3 has the same configuration as the photoelectric conversion cell C1. In other words, the photoelectric conversion unit 301 a, the transfer transistor 321 a, the FD unit 311, the reset transistor 322, the pixel amplifier transistor 323, and the switching transistor 324 are provided. Further, in the photoelectric conversion cell C3, the read pulse line 131a, the signal line 132c, the reset pulse line 335, the selection pulse line 336, and the cell power supply line vdd are respectively connected to predetermined positions, and the load transistor 125c is connected to the signal line 132c. ing. Since these structures are the same as that of the photoelectric conversion cell C1, detailed description is abbreviate | omitted.

  As described above, in the three photoelectric conversion cells C1, C2, and C3 included in the same column group in the solid-state imaging device of the present embodiment, the transfer transistors 121a, 221a, and 321a have the same gate. The read pulse line 131a is connected to and is collectively controlled by the read pulse line 131a. In addition, the switching transistors 124, 224, and 324 have their sources connected in order to the signal lines 132a, 132b, and 132c, respectively, so that the three photoelectric conversion cells C1, C2, and C3 can individually output signals. ing.

  By adopting such a configuration, signals can be simultaneously read out from the three photoelectric conversion cells C1, C2, and C3 included in the same column group. As a result, signals can be read out simultaneously for three rows, and signals are read out three times faster than conventional solid-state imaging devices that read out signals for each photoelectric conversion cell, that is, one row at a time. Can do.

  If the cell power supply line vdd for supplying a potential to the photoelectric conversion cell serves as a light shielding film for preventing light from entering the FD portion, the photoelectric conversion cell can be reduced and the aperture ratio can be improved. For example, the aperture ratio is 8%. For example, the cell power line vdd may be arranged at a position that is in a different plane from the signal line 132a and the like and covers the FD portion. When the aperture ratio is not set in this way, the aperture ratio is about 5%, so that an aperture ratio improvement of 3% is realized.

  Next, FIG. 3 shows an example of a layout that specifically realizes the circuit configuration shown in FIG. Here, each component in FIG. 3 is denoted by the same reference numeral corresponding to the component of the circuit configuration shown in FIG. However, the load transistors 125a, 125b and 125c, the load gate line 133, the source power supply line 134, the reset pulse lines 135, 235 and 335, and the selection pulse lines 136, 236 and 336 are omitted.

  With such a layout, the pitches of the photoelectric conversion units can be equally spaced in the horizontal direction and the vertical direction. This facilitates obtaining a high-quality image. However, the layout is not limited to this.

  Next, the operation of the solid-state imaging device according to the first embodiment will be described with reference to the drawings.

  FIG. 4 is a timing chart showing potential changes in the switching transistor, reset transistor, and transfer transistor and changes in the output signal output from the photoelectric conversion cell.

  In the initial state of operation, the switching transistor, the reset transistor, and the transfer transistor are all in the off state.

  In the solid-state imaging device of the present embodiment, signals are simultaneously read out from three rows by simultaneously reading out signals from three photoelectric conversion cells included in one column group.

  Further, since a series of operations are completed within the horizontal blanking period, the operation during one horizontal blanking period in which charges are detected for the three photoelectric conversion cells shown in FIG. 2 will be described.

  In order to transfer the charges of the photoelectric conversion units 101a, 201a, and 301a, a predetermined constant charge is applied to the load transistors 125a, 125b, and 125c. A constant voltage is always applied to the cell power line vdd. In this embodiment, since the power supply voltage is 3.3V, a voltage of 3.3V is applied to the cell power supply line vdd.

In this state, the switching transistors 124, 224, and 324 are turned on using the selection pulse lines 136, 236, and 336, respectively (time T ₁ ), and the reset transistors 122, 235, and 335 are used to reset the reset transistors 122, 222 and 322 are turned on (time T ₂ ). As a result, the charges of the FD units 111, 211, and 311 are swept out, and the FD units 111, 211, and 311 are reset. At the same time, signal levels at the time of resetting the FD units 111, 211, and 311 are detected by the pixel amplifier transistors 123, 223, and 323, respectively, and further output through the switching transistors 124, 224, and 324 and the signal lines 132a, 132b, and 132c. Then, they are clamped as reference levels in a noise cancellation circuit (not shown).

Next, after the reset transistors 122, 222, and 322 are turned off, a pulse voltage is supplied to the read pulse line 131a common to the three photoelectric conversion cells C1, C2, and C3, and all of the transfer transistors 121a, 221a, and 321a are supplied. The device is turned on (time T ₃ ). As a result, charges accumulated in the photoelectric conversion units 101a, 201a, and 301a are transferred to the FD units 111, 211, and 311, respectively. At the same time, the charges transferred to the FD units 111, 211, and 311 are detected by the pixel amplifier transistors 123, 223, and 323, respectively, and the signals are further transmitted through the switching transistors 124, 224, and 324 and the signal lines 132a, 132b, and 132c, respectively. Are output and sampled as accumulated signal levels in the noise cancellation circuit. In this way, by taking the difference between the reference level and the signal level, it is possible to detect an output signal from which the threshold variation and noise components of the pixel amplifier transistor 124 and the like are removed.

Next, the switching transistors 124, 224, and 324 are turned off (time T ₄ ) so that the pixel amplifier transistors 123, 223, and 323 do not output signals.

  Thus, the operation of detecting the charge of the photoelectric conversion unit for the three photoelectric conversion cells C1, C2, and C3 is completed.

  Thereafter, until the next three rows including the three photoelectric conversion cells C1, C2, and C3 are selected, the photoelectric conversion units included in the three rows are in a non-selected state and do not operate.

  In addition, the output signals are detected at the same time for each of the three and subsequent rows as well as the three rows.

  As described above, since the solid-state imaging device according to the present embodiment can simultaneously read out the output signal for every three rows, compared with the conventional solid-state imaging device that reads out the output signal for every row, there are 3 Signals from all photoelectric conversion cells can be read out at double the speed.

  In the solid-state imaging device of the present embodiment, the three photoelectric conversion cells C1, C2, and C3 included in the same column group have reset transistors 122, 222, and 322, respectively, and reset pulse lines 135, 235, and 335 is connected. Further, the FD sections 111, 211, and 311 are individually reset by the three reset transistors 122, 222, and 322, respectively.

  However, one reset transistor shared in one column group may be formed, and the three FD sections 111, 211, and 311 may be reset by the one reset transistor.

  Thus, the number of reset transistors can be reduced, the size of the photoelectric conversion cell can be reduced, and the aperture ratio of the photoelectric conversion unit can be improved.

  Further, in the solid-state imaging device of the present embodiment, one column group includes three photoelectric conversion cells, so that output signals are read simultaneously for every three rows. However, the number of photoelectric conversion cells included in one column group is not limited to three, and may be two or more. For example, if there are two, two rows can be read simultaneously, and the reading speed is doubled. Here, the same number of signal lines as the number of rows to be read simultaneously are required.

(Modification of the first embodiment)
Next, a modification of the first embodiment will be described.

  In the solid-state imaging device according to the first embodiment, each photoelectric conversion cell includes a switching transistor, thereby controlling the timing of outputting an output signal.

  On the other hand, in the modification of the first embodiment, the circuit configuration does not use a switching transistor. Specifically, the circuit configuration shown in FIG. 2 is obtained by removing all the switching transistors 124, 224, and 324. Here, in the first embodiment, the sources of the pixel amplifier transistors 123, 223, and 323 connected to the drains of the switching transistors 124, 224, and 324 are connected to the signal lines 132a, 132b, and 132c, respectively. To do.

  The operation in one horizontal blanking period in the case of such a circuit configuration will be described using FIG. 5 and comparing with FIG.

  FIG. 5 is a timing chart showing potential changes in the cell power line vdd, the reset transistor and the transfer transistor, and changes in the output signal output from the photoelectric conversion cell.

  In an initial state of operation, a low voltage is supplied to the cell power supply line vdd, and both the reset transistor and the transfer transistor are off.

In the case of the first embodiment, at the time T ₁ (see FIG. 4), which is the time when the switching transistor is turned on, in the case of this modification, the cell power supply line vdd that has been supplying the low voltage until then. Supply high voltage to

At time T _2, like the first embodiment, and turn on the reset transistor is also in this modification. As a result, as in the first embodiment, the FD unit is reset and the reference level signal is clamped in the noise cancellation circuit. Thereafter, the reset transistor returns to the off state.

Next, at time T ₃ , the transfer transistor is turned on to transfer charges from the photoelectric conversion unit to the FD unit. At the same time, the accumulated signal level is sampled by the noise cancellation circuit. Thereafter, the transfer transistor is returned to the OFF state, and thereafter, a low voltage is supplied to the cell power supply line vdd.

Subsequently, in the first embodiment at time T ₄ in which the selection transistor turned off, in this modification, the reset transistor is turned on. As a result, the FD portion has the same low voltage as that of the cell power supply line vdd, so that the pixel amplifier transistor does not operate. Thereafter, the reset transistor is returned to the off state.

  As described above, even in the solid-state imaging device having a circuit configuration that does not use the switching transistor in the modification of the first embodiment, the output signal can be appropriately read.

(Second Embodiment)
Next, a solid-state imaging device according to a second embodiment of the present invention will be described with reference to the drawings.

  FIG. 6 is a diagram for explaining an example of the arrangement of photoelectric conversion cells of the solid-state imaging device according to the second embodiment.

  As shown in FIG. 6, in the solid-state imaging device of the second embodiment, photoelectric conversion cells C having a function of photoelectrically converting incident light according to intensity are arranged on a substrate S to form a matrix. is doing. A column group CG is formed by three photoelectric conversion cells C included in the same column and adjacent to each other, and a row group RG is formed by two photoelectric conversion cells C included in the same row and adjacent to each other. Yes.

  Next, FIG. 7 shows a circuit configuration of an imaging region in the solid-state imaging device according to the second embodiment. In FIG. 7, six photoelectric conversion cells belonging to three rows and two columns, in other words, three row groups RG1, RG2, and RG3 are enlarged. Further, these six photoelectric conversion cells belong to two column groups although the column groups are not shown.

  The circuit configuration of the imaging region in the solid-state imaging device according to the second embodiment shown in FIG. 7 is the same as that shown in FIG. 2 in that a part of the circuit configuration is shared by a plurality of photoelectric conversion cells included in the same row group. This is different from the circuit configuration in the case of the first embodiment shown. This will be specifically described below.

  The row group RG1 is a row group including two photoelectric conversion cells included in the same column and adjacent to each other. Here, similarly to the photoelectric conversion cell C1 of the solid-state imaging device according to the first embodiment, the row group RG1 includes the photoelectric conversion unit 101a, the transfer transistor 121a, the FD unit 111, the reset transistor 122, and the pixel amplifier. A transistor 123 and a switching transistor 124 are provided. Further, in the row group RG1, the read pulse line 131a, the signal line 132a, the reset pulse line 135, the selection pulse line 136, and the cell power supply line vdd are connected to predetermined positions, respectively, and the load transistor 125a is connected to the signal line 132a. ing. Since these configurations are the same as those of the photoelectric conversion cell C1 of the solid-state imaging device according to the first embodiment, detailed description thereof is omitted.

  In addition to the above configuration, the row group RG1 includes a photoelectric conversion unit 101b and a transfer transistor 121b, and a read pulse line 131b is connected. Here, as in the photoelectric conversion unit 101a, the photoelectric conversion unit 101b has an anode grounded and a cathode connected to the source of the transfer transistor 121b. The transfer transistor 121b has a source connected to the cathode of the photoelectric conversion unit 101b, a drain connected to the FD unit 111, a source of the reset transistor 122, and a gate of the pixel amplifier transistor 123, and a gate connected to the readout pulse line 131a. ing.

  As described above, the two photoelectric conversion cells included in the row group RG1 share the FD unit 111, the reset transistor 122, the pixel amplifier transistor 123, the switching transistor 124, the signal line 123a, the reset pulse line 135, and the switching pulse line 136. is doing.

  Next, the row group RG2 has the same configuration as the row group RG1. That is, in addition to the same configuration as the photoelectric conversion cell C2 according to the first embodiment (the description is omitted by attaching the same reference numerals as in FIG. 2), the row group RG2 includes the photoelectric conversion unit 201b and the transfer transistor 221b. And a read pulse line 131b is connected. Since these have the same configuration as the row group RG1, detailed description thereof will be omitted.

  The row group RG3 has the same configuration as the row group RG1. That is, in addition to the same configuration as the photoelectric conversion cell C3 according to the first embodiment (the description is omitted by attaching the same reference numerals as in FIG. 2), the row group RG3 includes the photoelectric conversion unit 301b and the transfer transistor 321b. And a read pulse line 131c is connected. Since these have the same configuration as the row group RG1, detailed description thereof will be omitted.

  In the above configuration, the three photoelectric conversion cells each including the photoelectric conversion units 101a, 201a, and 301a are included in the same column group, and the three photoelectric conversion cells including the photoelectric conversion units 101b, 201b, and 301b, respectively. Included in the same column group.

  As described above, in the circuit configuration of the imaging region according to the solid-state imaging device of the second embodiment, the transfer transistors 121a, 221a, and 321a included in the three photoelectric conversion cells included in the same column group are In either case, the gates are connected to the common readout pulse line 131a and are collectively controlled by the readout pulse line 131a. Similarly, all of the transfer transistors 121b, 221b, and 321b included in three photoelectric conversion cells included in the same column group different from the previous one have gates connected to a common read pulse line 131b and read pulse lines. It is collectively controlled by 131b.

  The switching transistors 124, 224, and 324 have sources connected to signal lines 132a, 132b, and 132c in order, so that the three row groups RG1, RG2, and RG3 can individually output signals.

  In this way, signals can be read out simultaneously in three rows as in the case of the first embodiment, and signals can be read out at a higher speed than conventional solid-state imaging devices.

  At the same time, by sharing some components among a plurality of photoelectric conversion cells included in the same row group, the number of components such as transistors and wirings can be reduced, and the photoelectric conversion units in the photoelectric conversion cells occupy. The ratio (opening ratio) can be increased. Specifically, in this embodiment, the FD portion, the reset transistor, the pixel amplifier transistor, the switching transistor, the reset pulse line, the selection pulse line, and the like are shared in one row group. Accordingly, for example, when the area of the photoelectric conversion cell is 4.1 μm × 4.1 μm and the design is performed with the rule of 0.35 μm, in the circuit configuration of the solid-state imaging device of the present embodiment, the photoelectric conversion unit The aperture ratio is about 25%. In the case of the solid-state imaging device according to the first embodiment, the aperture ratio is about 5%, which is improved by about 20%.

  If the cell power supply line vdd for supplying a potential to the photoelectric conversion cell serves as a light-shielding film that prevents light from entering the FD portion, the photoelectric conversion cell can be further reduced and the aperture ratio can be reduced. Improvements can be realized. For this reason, the aperture ratio is improved to 28%, for example. In order to do this, the cell power supply line vdd may be disposed at a position in a plane different from the signal line 132a and the like and covering the FD portion.

  Next, FIG. 8 shows an example of a layout that specifically realizes the circuit configuration shown in FIG. Here, each component in FIG. 8 is denoted by the same reference numeral corresponding to the component of the circuit configuration shown in FIG. However, the load transistors 125a, 125b, and 125c, the load gate line 133, the source power supply line 134, the reset pulse lines 135, 235, and 335, and the selection pulse lines 136, 236, and 336 are omitted.

  With such a layout, the pitches of the photoelectric conversion units can be equally spaced in the horizontal direction and the vertical direction. This facilitates obtaining a high-quality image. However, the layout is not limited to this.

  Next, the operation of the solid-state imaging device according to the second embodiment will be described with reference to the drawings.

  FIG. 9 is a timing chart showing potential changes in a switching transistor, a reset transistor, an odd-numbered transfer transistor, and an even-numbered transfer transistor and changes in an output signal output from the photoelectric conversion cell.

  Here, a series of operations are completed within the horizontal blanking period. In this embodiment, three photoelectric conversion cells included in the same column and adjacent to each other are made one column group, and signals are read for each column group, so that three rows are read simultaneously. become. Further, in the present embodiment, the odd-numbered photoelectric conversion cells and the even-numbered photoelectric conversion cells are alternately read.

  From the above, the output signal is detected for the photoelectric conversion cells included in the first to third rows and included in the odd-numbered columns in a certain horizontal blanking period, and the first to third in the next horizontal blanking period. Output signals are detected for photoelectric conversion cells included in rows and in even columns. Similarly, in the fourth and subsequent rows, output signals are detected alternately for the odd-numbered and even-numbered photoelectric conversion cells in three rows at a time.

  Here, the horizontal blanking period in which detection is performed for the odd-numbered photoelectric conversion cells is referred to as horizontal blanking 1, and the horizontal blanking period in which detection is performed for the even-numbered photoelectric conversion cells is referred to as horizontal blanking 2. FIG. The timing for the period during which horizontal blanking 1 and horizontal blanking 2 are performed once is shown.

  Further, in the circuit configuration illustrated in FIG. 7, the row groups CG1, CG2, and CG2 are included in the first row, the second row, and the third row of the matrix composed of photoelectric conversion cells in order. In addition, the photoelectric conversion cells including the photoelectric conversion units 101a, 201a, and 301a are included in the odd columns, and the photoelectric conversion cells including the photoelectric conversion units 101b, 201b, and 301b are included in the even columns.

  First, an operation (corresponding to horizontal blanking 1) of detecting charges of photoelectric conversion units (here, photoelectric conversion units 101a, 201a, and 301a) included in the first to third rows and included in the odd-numbered columns. explain.

  In the horizontal blanking 1, first, in order to transfer charges of photoelectric conversion units (here, photoelectric conversion units 101a, 201a, and 301a) included in the first to third rows and included in the odd-numbered columns, the load transistors 125a, A predetermined constant charge is applied to 125b and 125c. Further, during the horizontal blanking 1, the transfer transistors 121b, 221b, and 321b are turned off. In the present embodiment, a constant voltage of 3.3 V is applied to the cell power line vdd.

  In this way, the horizontal blanking 1 can be performed in the same manner as the charge detection in the circuit configuration of the solid-state imaging device according to the first embodiment shown in FIG.

That is, in the state, the switching transistors 124, 224 and 324 is turned on (time T _21), further to turn on the reset transistor 122, 222 and 322 (time T _22). As a result, the FD units 111, 211, and 311 are reset. In addition, signal levels at the time of resetting the FD units 111, 211, and 311 are output through the signal lines 132a, 132b, and 132c, respectively, and are clamped as reference levels in the noise cancellation circuit.

Next, after the reset transistors 122, 222, and 322 are turned off, a pulse voltage is supplied to the readout pulse line 131a common to the three photoelectric conversion cells C1, C2, and C3, and the three transfer transistors 121a, 221a, and 321a are supplied. Are turned on (time T ₂₃ ). As a result, charges accumulated in the photoelectric conversion units 101a, 201a, and 301a are transferred to the FD units 111, 211, and 311, respectively. In addition, the charges of the FD units 111, 211, and 311 are detected and sampled as the accumulated signal level in the noise cancellation circuit. In this manner, output signals from the photoelectric conversion units 101a, 201a, and 301a can be individually detected as in the first embodiment.

Next, the switching transistors 124, 224 and 324 are turned off (time T ₂₄ ) so that the pixel amplifier transistors 123, 223 and 323 do not output signals.

  Thus, the operation (horizontal blanking 1) for detecting the charges of the photoelectric conversion units included in the first to third rows and included in the odd-numbered columns is completed.

  Next, an operation (corresponding to horizontal blanking 2) of detecting charges of photoelectric conversion units (here, photoelectric conversion units 101b, 201b, and 301b) included in the first to third rows and included in even columns. explain.

  In order to detect the charges of the photoelectric conversion units 101b, 201b, and 301b, a predetermined constant charge is applied to the load transistors 125a, 125b, and 125c in the same manner as in the horizontal blanking 1. Further, during the horizontal blanking 1, the transfer transistors 121a, 221a, and 321a are kept off.

In this state, the switching transistors 124, 224, and 324 are turned on (time T ₂₅ ) and the reset transistors 122, 222, and 322 are turned on (time T ₂₆ ) as in the case of horizontal blanking 1. Then, the charge of the FD unit 111 is swept out and reset. At the same time, as in the case of horizontal blanking 1, the signal levels at the time of resetting of the FD units 111, 211, and 311 are respectively output and clamped as reference levels in the noise cancellation circuit.

Next, after turning off the reset transistors 122, 222 and 322, a pulse voltage is supplied to the read pulse line 131b which is different from that in the horizontal blanking 1 and which is common to the three row groups RG1, RG2 and RG3. Three transfer transistors 121b, 221b and 321b different from those in the blanking 1 are turned on (time T ₂₇ ). Thus, charges accumulated in the photoelectric conversion units 101b, 201b, and 301a different from those in the horizontal blanking 1 are transferred to the same FD units 111, 211, and 311 as in the horizontal blanking 1, respectively. In addition, the charges of the FD units 111, 211, and 311 are detected and sampled as the accumulated signal level in the noise cancellation circuit. In this manner, output signals from the photoelectric conversion units 101b, 201b, and 301b can be individually detected as in the first embodiment.

Next, the switching transistors 124, 224 and 324 are turned off (time T ₂₈ ) so that the pixel amplifier transistors 123, 223 and 323 do not output signals.

  Thus, the operation (horizontal blanking 2) for detecting the charges of the photoelectric conversion units included in the first to third rows and included in the even-numbered columns ends.

  Thereafter, until the next row from the first row to the third row is selected, the photoelectric conversion units included in the first row to the third row are in a non-selected state and do not operate.

  In addition, for the three and subsequent rows, the output signals are detected at the same time for every three rows and alternately between the odd and even columns in the same manner as the three rows.

  As described above, in the solid-state imaging device according to the second embodiment, by simultaneously detecting signals for a plurality of photoelectric conversion cells (column groups) included in the same column and adjacent to each other, a plurality of rows of signals can be read simultaneously. This makes it possible to speed up signal readout from all photoelectric conversion cells. Further, by sharing a part of the constituent elements among a plurality of adjacent photoelectric conversion cells (row groups) included in the same row, the number of constituent elements is reduced and the aperture ratio of the photoelectric conversion unit is improved. . As a result, the odd-numbered columns and the even-numbered columns are alternately read out and three rows are read out at the same time. Therefore, the solid-state imaging device of the present embodiment reads the signals one by one for the photoelectric conversion cells and does not share the components. Compared with a solid-state imaging device, signals can be read from all photoelectric conversion cells at a speed 1.5 times higher.

  In the second embodiment, each photoelectric conversion cell includes a switching transistor, which controls the timing of outputting an output signal. However, as in the modification of the first embodiment, the circuit configuration does not use a switching transistor, and the voltage of the cell power supply line vdd is controlled and the timing of signal output is controlled using the reset transistor. Also good.

  Further, in the solid-state imaging device of the present embodiment, one column group includes three photoelectric conversion cells, so that output signals are read simultaneously for every three rows. However, the number of photoelectric conversion cells included in one column group is not limited to three, and may be two or more. Here, the same number of signal lines as the number of rows to be read simultaneously are required.

  The solid-state imaging device of the present invention can read signals simultaneously in a plurality of rows, and is useful as a solid-state imaging device that can read signals from all photoelectric conversion cells at high speed.

It is a figure which shows typically the arrangement | sequence of the photoelectric conversion cell in the solid-state imaging device which concerns on the 1st Embodiment of this invention. It is a figure which shows typically the circuit structure of the imaging region in the solid-state imaging device which concerns on the 1st Embodiment of this invention. It is a figure which shows an example of the layout which implement | achieves concretely the circuit structure of the imaging region in the solid-state imaging device which concerns on the 1st Embodiment of this invention. 3 is a timing chart illustrating an operation of a circuit in an imaging region in the solid-state imaging device according to the first embodiment of the present invention. It is a timing chart which shows operation | movement of the circuit of the imaging region in the solid-state imaging device which concerns on the modification of the 1st Embodiment of this invention. It is a figure which shows typically the arrangement | sequence of the photoelectric conversion cell in the solid-state imaging device which concerns on the 2nd Embodiment of this invention. It is a figure which shows typically the circuit structure of the imaging region in the solid-state imaging device which concerns on the 2nd Embodiment of this invention. It is a figure which shows an example of the layout which implement | achieves concretely the circuit structure of the imaging region in the solid-state imaging device which concerns on the 2nd Embodiment of this invention. 6 is a timing chart illustrating an operation of a circuit in an imaging region in a solid-state imaging device according to a second embodiment of the present invention. It is a figure which shows typically the circuit structure of the imaging area in the conventional solid-state imaging device.

Explanation of symbols

101a, 101b, 201a, 201b, 301a, 301b Photoelectric conversion units 111, 211, 311 Floating diffusion units 121a, 121b, 221a, 221b, 321a, 321b Transfer transistors 122, 222, 322 Reset transistors 123, 223, 323 Pixel amplifier transistors 124, 224, 324 Switching transistor 125a, 125b, 125c Load transistor 131a, 131b Read pulse line 132a, 132b, 132c Signal line 133 Load gate line 134 Source power supply line 135, 235, 335 Reset pulse line 136, 236, 336 Select pulse Line C, C1, C2, C3 Photoelectric conversion cell CG Column group RG, RG1, RG2, RG3 Row group S Substrate

Claims (10)

A solid-state imaging device including a plurality of photoelectric conversion cells arranged to form a matrix and each having a photoelectric conversion unit that performs photoelectric conversion,
Among the plurality of photoelectric conversion cells, a plurality of column groups are configured for each set of the photoelectric conversion cells included in the same column and arranged in adjacent rows,
A plurality of floating diffusion units connected to the plurality of photoelectric conversion units and to which charges are transferred from the plurality of photoelectric conversion units;
A plurality of transfer transistors provided between the plurality of photoelectric conversion units and the plurality of floating diffusion units and transferring charges from the plurality of photoelectric conversion units to the plurality of floating diffusion units;
A plurality of read pulse lines for commonly controlling the plurality of transfer transistors in the plurality of column groups;
A plurality of pixel amplifier transistors for detecting potentials of the plurality of floating diffusion portions and outputting the signals as signals;
A solid-state imaging device comprising: a plurality of signal lines for the plurality of pixel amplifier transistors to output signals. Among the plurality of photoelectric conversion cells, a plurality of row groups are formed for each of the plurality of photoelectric conversion cells included in and adjacent to the same row,
The plurality of floating diffusion portions are common floating diffusion portions to which charges are transferred from the photoelectric conversion units included in the row groups,
2. The solid-state imaging device according to claim 1, wherein the plurality of readout pulse lines are a plurality of readout pulse lines formed individually for the plurality of transfer transistors included in each row group.   The solid-state imaging device according to claim 2, wherein the plurality of pixel amplifier transistors and the plurality of signal lines are formed in common for each row group. Formed in common for each row group,
A plurality of switching transistors for controlling the timing at which the plurality of pixel amplifier transistors output signals;
The solid-state imaging device according to claim 2, further comprising a plurality of selection pulse lines that control the plurality of switching transistors.   5. The solid-state imaging device according to claim 1, further comprising: a plurality of reset units that reset the plurality of floating diffusion portions.   The plurality of reset means include a plurality of reset transistors that are formed in common for each row group and discharge the electric charges of the floating diffusion portions, and a plurality of reset pulse lines that control the plurality of reset transistors. The solid-state imaging device according to claim 5.   The plurality of reset means include a plurality of reset transistors that are formed in common for each column group and discharge the electric charges of the floating diffusion portions, and a plurality of reset pulse lines that control the plurality of reset transistors. The solid-state imaging device according to claim 5.   The pitch between at least the plurality of photoelectric conversion units is formed at an equal pitch in at least one of a horizontal direction and a vertical direction. Solid-state imaging device.   The solid-state imaging device according to claim 1, further comprising a signal processing circuit that processes signals output from the plurality of photoelectric conversion cells. A plurality of power supply lines for supplying a potential to the plurality of photoelectric conversion cells;
The solid-state imaging device according to claim 1, wherein the plurality of power supply lines have a function as a light-shielding film that prevents light from entering the floating diffusion portion.

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