JP2010171348A - Wiring board and stacked ceramic capacitor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring board for obtaining a low-loss and small-delay signal wiring using a through-hole conductor of a built-in component built in the wiring board as a signal wiring. <P>SOLUTION: The wiring board 10 includes a semiconductor chip 200 (mounting component) is mounted. A core material 11 whose accommodation hole section 11a is opened, a condenser 100 (built-in component) that is accommodated in the accommodation hole section 11a and in which a through-hole conductor 60 is formed, and wiring lamination sections 12 and 13 in which an insulation layer and a conductor layer are laminated and formed at the upper and lower sides of the core material 11. The through-hole conductor 60 is used as the signal wiring that is connected with the semiconductor chip 200 via a first wiring lamination section 12, and its inside area is filled with a choke object 62 (material) while its outside neighboring area is filled with a choke object 63 (material). The choke objects 62 and 63 have lower dielectric constants than the material of the capacitor 100. Thus, the signal wiring having high-conductivity and low-dielectric constant is configured and low-loss, small-delay, and excellent transmission performance is obtained. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a wiring board that houses a built-in component in a housing hole that is opened in a core material, and a multilayer ceramic capacitor as a built-in component that can be housed in a housing hole of the wiring board.

  Conventionally, a package for mounting a semiconductor chip on which a large number of circuit elements are formed has been widely used. As a package structure, for example, a wiring board is known in which a core material is disposed and a wiring laminated portion in which conductor layers and insulating layers are alternately laminated above and below the core material is formed. Such a wiring board needs to be provided with a wiring structure such as a power supply wiring for supplying power to the semiconductor chip to be mounted, a ground wiring, and a signal wiring for transmitting and receiving data and control signals. The wiring board on which the semiconductor chip is placed is mounted on an external base material such as a printed board, and a large number of terminals of the semiconductor chip and the external base material are electrically connected via the wiring structure of the wiring board.

  On the other hand, in order to stabilize the power supplied to the semiconductor chip, it is desirable to place a capacitor in the package and connect it to the power supply wiring. In this case, in the configuration in which the capacitor is mounted on the wiring board, the degree of freedom of placement of other mounted parts is reduced to secure the capacitor placement area, and the wiring distance from the capacitor and the semiconductor chip is reduced to other wiring. To be limited to become longer. As a result, the wiring resistance and inductance of the signal wiring increase, leading to characteristics deterioration such as a drop in power supply voltage supplied to the semiconductor chip, and the manufacturing process is complicated because it is necessary to mount a capacitor after the wiring board is completed. Become. In order to correct these drawbacks, a method of incorporating a capacitor inside the wiring board has been proposed (see, for example, Patent Document 1). If the capacitor is built in the wiring board in this way, the capacitor can be arranged closer to the mounted component than when mounted on the wiring board.

  However, when a capacitor is built in the wiring board, the signal wiring extended from the signal terminal of the semiconductor chip placed at the upper center of the wiring board must be arranged to avoid the area of the capacitor immediately below. For this reason, the signal wiring is extended from the semiconductor chip via the peripheral region and connected in the stacking direction with via conductors, so that the degree of freedom of wiring is reduced and the package size is further increased.

  On the other hand, when a via array type capacitor is built in a wiring board, it is conceivable to add a wiring structure used as a signal wiring in addition to a positive wiring and a negative wiring. Generally, in a via array type capacitor composed of multilayer ceramic, when some via conductors are used as signal wiring, the dielectric constant of the capacitor material is relatively large, which increases signal line transmission delay and impedance. There are concerns about inconsistencies. Therefore, a method has been proposed in which a low dielectric constant portion surrounding the capacitor portion is provided, and a signal wiring is formed in the low dielectric constant portion (see, for example, Patent Document 2).

JP 2004-228190 A JP 2005-39006 A

  In the method disclosed in Patent Document 2, the signal wiring that penetrates the low dielectric constant portion is formed with the same structure as the positive and negative via conductors that penetrate the capacitor portion. When using a multilayer ceramic capacitor, assuming a ceramic sintered body with a high sintering temperature, the material of the signal wiring and the material of each via conductor for the positive electrode and the negative electrode are made of a metal having a relatively low conductivity such as nickel. Used. On the other hand, a ceramic sintered body having a low sintering temperature generally has a low dielectric constant, and it is difficult to increase the capacitance of the capacitor. Therefore, there is a problem that the resistance component of the signal wiring formed in the capacitor portion is increased, leading to an increase in transmission signal loss, thereby causing a signal transmission error, heat generation, and the like.

  The present invention has been made to solve these problems, and in a wiring board that accommodates a built-in component in a region immediately below the mounted component, a semiconductor chip and an external substrate are avoided without avoiding the region of the built-in component. Providing a wiring board suitable for miniaturization by arranging signal wiring with high conductivity between the materials and providing low-permittivity material around it to realize signal wiring with low loss and small delay Objective.

  In order to solve the above problems, a wiring board according to the present invention is a wiring board on which a mounting component is placed and electrically connected between the mounting component and an external base material, and penetrates through an upper surface and a lower surface. Insulated on the upper surface side of the core material, the core material having an opening in the housing hole, the built-in component accommodated in the housing hole portion and formed with one or more first through-hole conductors penetrating the upper surface and the lower surface A first wiring laminated portion in which layers and conductor layers are alternately laminated; and a second wiring laminated portion in which insulating layers and conductor layers are alternately laminated on the lower surface side of the core material; Is used as a signal wiring connected to the mounting component via the first wiring laminated portion, and a material having a dielectric constant lower than the dielectric constant of the material of the built-in component in the region inside the first through-hole conductor And the first through-hole conductor It has a structure covering the area near the side of a material having a dielectric constant lower than that of the internal parts of the material.

  In this specification, the term “through-hole conductor” is used to mean a tubular conductor that conducts between layers of a wiring board or a built-in component.

  According to the wiring board of the present invention, the built-in component is housed in the housing hole of the core material, the first through-hole conductor penetrating the built-in component vertically is formed, and this is used as the signal wiring connected to the mounted component. Realized the structure. As a result, when the signal wiring is extended from the mounting member to the external base material, it is possible to use the path immediately below without being restricted by the placement of the capacitor, and to form the material around the signal wiring with a low dielectric constant. . Therefore, it is possible to prevent the delay of the transmission signal input / output to / from the mounted component and ensure good transmission characteristics while realizing a reduction in the size of the wiring board package.

  In the present invention, the first through-hole conductor is preferably formed using a metal having a conductivity higher than that of the inner conductor of the built-in component. Accordingly, the signal wiring using the first through-hole conductor is formed of a material having a high conductivity in addition to the surrounding material having a low dielectric constant, so that the loss of the signal wiring is reduced. At the same time, the delay of the transmission signal can be further suppressed.

  In the present invention, a capacitor configured using a ceramic sintered body can be used as the built-in component. In this case, a second through-hole conductor for shielding the signal wiring is formed in the built-in component so as to surround a side surface of the first through-hole conductor, and the first through-hole conductor and the second through-hole are formed. A region sandwiched between the conductors may be filled with a material having a dielectric constant lower than that of the material of the built-in component. Furthermore, the first through-hole conductor and the second through-hole conductor may be formed at a position directly below the center portion of the mounting component. Here, when the mounting component has a predetermined planar shape (for example, a square), the “central portion” is a shape portion having a size approximately half the planar shape from the center of the planar shape of the mounting component. It is desirable to be within the range.

  In order to solve the above-mentioned problems, a multilayer ceramic capacitor according to the present invention is a multilayer ceramic capacitor in which ceramic dielectric layers and internal electrode layers are alternately stacked, and a plurality of via conductors connected to the internal electrode layers are arranged in an array. A ceramic capacitor, which is formed using a metal that penetrates an upper surface and a lower surface of a region where the plurality of via conductors are not disposed and has a conductivity higher than that of the internal electrode layer and the via conductor. One or a plurality of first through-hole conductors, a material having a dielectric constant lower than a dielectric constant of the ceramic dielectric layer is filled in a region inside the first through-hole conductor, and the first through-hole conductor The region near the outside is covered with a material having a dielectric constant lower than that of the material of the built-in component.

  The multilayer ceramic capacitor of the present invention further includes a second through-hole conductor formed so as to surround a side surface of the first through-hole conductor, and is sandwiched between the first through-hole conductor and the second through-hole conductor. The region may be filled with a material having a dielectric constant lower than that of the ceramic dielectric layer. In this case, the first through-hole conductor and the second through-hole conductor may be formed by copper plating. Furthermore, the second through-hole conductor may be connected to the same potential as the positive electrode or the negative electrode of the internal electrode layer.

  According to the present invention, when a built-in component such as a capacitor is accommodated in a wiring board on which the mounted component is placed, one or a plurality of first through-hole conductors penetrating the built-in component are formed, and this is used as a signal wiring. Since the inner region and the region near the outer side are formed using a low dielectric constant material, the signal wiring is routed on the wiring board without avoiding the capacitor directly below, and is input via the signal wiring. The transmission performance can be improved by preventing the delay of the output transmission signal. In addition, since the first through-hole conductor is made of a metal with high conductivity and a low dielectric constant material can be provided around the first through-hole conductor, a signal wiring that can further reduce transmission loss and reduce transmission loss can be configured. A wiring board that can prevent problems such as errors and heat generation can be realized.

It is a figure which shows the general | schematic cross-section of the wiring board of this embodiment. It is sectional drawing of the capacitor | condenser of FIG. FIG. 2 is a top view of the capacitor of FIG. 1. It is a 1st figure explaining the manufacturing method of the wiring board of this embodiment. It is a 2nd figure explaining the manufacturing method of the wiring board of this embodiment. It is a 3rd figure explaining the manufacturing method of the wiring board of this embodiment. It is a 4th figure explaining the manufacturing method of the wiring board of this embodiment. It is a 5th figure explaining the manufacturing method of the wiring board of this embodiment. It is a 6th figure explaining the manufacturing method of the wiring board of this embodiment. It is a figure which shows the general | schematic cross-section of a wiring board at the time of changing the formation method of a through-hole conductor and a closure as a modification of this embodiment.

  Hereinafter, a preferred embodiment of a wiring board to which the present invention is applied will be described with reference to the drawings.

  FIG. 1 is a diagram showing a schematic cross-sectional structure of the wiring board of the present embodiment. The wiring board 10 shown in FIG. 1 has a structure including a core material 11, a first wiring laminated portion 12 on the upper surface side of the core material 11, and a second wiring laminated portion 13 on the lower surface side of the core material 11. Yes. The wiring board 10 of the present embodiment includes a capacitor 100 as a built-in component therein, and a semiconductor chip 200 as a mounted component mounted thereon.

The core material 11 is made of an epoxy resin containing a filler material such as SiO ₂ , for example. A conductor layer 21 is formed on the upper surface of the core material 11, and a conductor layer 22 is formed on the lower surface of the core material 11. The core material 11 has an accommodation hole 11a that passes through the center in a rectangular shape, and is accommodated in a state in which the capacitor 100 is embedded in the accommodation hole 11a. A resin filler 50 is filled in a gap between the accommodation hole 11 a of the core material 11 and the side surface of the capacitor 100. As the resin filler 50, for example, a thermosetting resin made of a polymer material is used. The resin filler 50 has a role of fixing the capacitor 100 and acts so that the resin filler 50 absorbs deformation of the capacitor 100 and the core material 11.

  The capacitor 100 is a via array type multilayer ceramic capacitor, and is characterized in that a signal wiring and a shield structure are formed at the center thereof. That is, a plurality of double-hole through-hole conductors 60 and 61 are formed in the central portion of the capacitor 100 so as to penetrate predetermined locations in the stacking direction. The inside of each through-hole conductor 60 is filled with a closing body 62, and the region sandwiched between the through-hole conductors 60 and 61 is filled with a closing body 63. The inner peripheral side through-hole conductor 60 (first through-hole conductor of the present invention) is used as signal wiring between the semiconductor chip 200 and an external substrate (not shown), and the outer peripheral side through-hole conductor 61 (the present invention). The second through-hole conductor) is used as a shield structure surrounding the signal wiring. Each through-hole conductor 60, 61 is formed by, for example, copper plating, and each closing body 62, 63 is made of a material having a dielectric constant lower than that of the capacitor 100, such as a low dielectric constant epoxy resin. . The detailed structure of the capacitor 100 will be described later.

  The core material 11 is formed with a plurality of through-hole conductors 30 penetrating predetermined portions in the stacking direction. The inside of the through-hole conductor 30 is filled with a closing body 31 made of, for example, an epoxy resin. The through-hole conductor 30 has a role of connecting and conducting an arbitrary wiring pattern in each of the conductor layers 21 and 22 in the stacking direction.

  The first wiring laminated portion 12 is formed on the resin insulating layers 14 and 16 formed on the upper surface side of the core material 11, the conductor layer 23 formed on the upper surface of the resin insulating layer 14, and the upper surface of the resin insulating layer 16. The plurality of terminal pads 25 and a solder resist layer 18 covering the top surface of the resin insulating layer 16 are provided. A plurality of via conductors 32 are provided at predetermined positions on the resin insulating layer 14 to connect and conduct the conductor layers 21 and 23 in the laminating direction. The conductor layers 23 and the terminal pads 25 are provided at predetermined positions on the resin insulating layer 16. A plurality of via conductors 34 that are conductively connected in the stacking direction are provided. The solder resist layer 18 is opened at a plurality of locations to expose a plurality of terminal pads 25, and a plurality of solder bumps 40 are formed there. Each solder bump 40 is connected to each pad 201 of the semiconductor chip 200 placed on the wiring substrate 10.

  The second wiring laminated portion 13 is formed on the lower surface of the resin insulating layer 17, the resin insulating layers 15 and 17 formed on the lower surface side of the core material 11, the conductor layer 24 formed on the lower surface of the resin insulating layer 15. The plurality of BGA pads 26 and a solder resist layer 19 covering the lower surface of the resin insulating layer 17 are provided. A plurality of via conductors 33 are provided at predetermined positions of the resin insulating layer 15 to connect and conduct the conductor layers 22 and 24 in the laminating direction. At predetermined positions of the resin insulating layer 17, the conductor layer 24 and the BGA pad 26 are provided. A plurality of via conductors 35 are provided which are connected in the laminating direction. The solder resist layer 19 is opened at a plurality of locations to expose a plurality of BGA pads 26 to which a plurality of solder balls 41 are connected. When the wiring board 10 is used as a BGA package, the external base material and each part of the wiring board 10 can be electrically connected via the plurality of solder balls 41.

  As described above, the structural feature of the wiring board 10 of the present embodiment is that the through-hole conductor 60 penetrating the built-in capacitor 100 is used as the signal wiring. Originally, in the capacitor 100, only via conductors for supplying power and ground to the internal electrode layer are formed as wiring in the stacking direction. However, according to the structure of this embodiment, signal wiring that is not supplied to the capacitor 100 itself. Can be arranged in the central region of the wiring board 10. Therefore, the signal path from the pad 201 of the semiconductor chip 200 to the solder ball 41 can form the shortest path including the through-hole conductor 60. In addition, the closing conductors 62 and 63 near the through-hole conductor 60 are compared to the material of the capacitor 100 (for example, barium titanate), compared to the via conductor formed in the capacitor 100 surrounded by ceramic having a high dielectric constant. Thus, the dielectric constant can be lowered. Further, nickel having a relatively low conductivity is used for the via conductor of the capacitor 100, whereas a metal material having a high conductivity such as copper can be used for the through-hole conductor 60. Therefore, since the signal wiring of this embodiment can constitute a transmission path with high conductivity and low dielectric constant, it is possible to prevent signal delay and ensure good transmission performance, as well as signal transmission errors and heat generation due to increased resistance components. And other problems can be prevented.

  In addition, since the capacitor 100 is provided with a through-hole conductor 61 having a shield structure around the through-hole conductor 60 serving as a signal wiring with a closing body 63 interposed therebetween, electromagnetic interference with the signal wiring is effectively prevented. Can be suppressed. In this case, in addition to the effect of suppressing the electromagnetic interference between the signal wiring and the outside, the shield structure is individually formed for each of the plurality of signal wirings, so the effect of suppressing the electromagnetic interference between the signal wirings There is. Further, it is possible to strengthen the signal wiring ground by connecting the through-hole conductor 61 to the ground, thereby further suppressing signal delay.

  In the present embodiment, for the sake of simplicity, a case where four signal wires (2 × 2) are passed through the capacitor 100 will be described as an example. However, the number of signal wires can be changed as appropriate. In this case, the invention is not limited to the formation of four shield structures that surround the four signal wirings, and a structure in which the four signal wirings are surrounded by one shield structure may be employed. Further, it is possible to adopt a structure in which only the through-hole conductor 60 serving as the signal wiring and the closed body 62 inside thereof are formed in the capacitor 100 and the through-hole conductor 61 serving as the shield structure and the closed body 63 inside thereof are not provided. it can.

  Next, the structure of the capacitor 100 of FIG. 1 will be described with reference to FIGS. FIG. 2 shows a cross-sectional view of the capacitor 100, and FIG. 3 shows a top view of the capacitor 100. The capacitor 100 of the present embodiment is a via array type capacitor as described above, and has a structure in which a plurality of ceramic dielectric layers 102 are laminated using a ceramic sintered body 101. The ceramic sintered body 101 is made of a high dielectric constant ceramic such as barium titanate. Between the ceramic dielectric layers 102, the first internal electrode layers 110a and the second internal electrode layers 110b are alternately arranged. The first internal electrode layer 110a functions as an electrode for power supply, the second internal electrode layer 110b functions as an electrode for ground, and both electrodes are disposed to face each other with each ceramic dielectric layer 102 being an insulator interposed therebetween. Thus, a predetermined capacity is formed.

  As shown in FIG. 3, a plurality of first terminal electrodes 107 a and a plurality of second terminal electrodes 107 b are arranged in an array in the peripheral region on the upper surface of the ceramic sintered body 101. On the other hand, in the central region of the ceramic sintered body, four terminal electrodes 107c are arranged at the upper end positions of the above-described four through-hole conductors 60, and each of these terminal electrodes 107c is closed by a closing body 62 (FIG. 1). Is surrounded by four through-hole conductors 61. A plurality of first terminal electrodes 108a, a plurality of second terminal electrodes 108b, and four terminal electrodes 108c are formed on the lower surface of the ceramic sintered body 101 in the same arrangement as in FIG.

  Further, the ceramic sintered body 101 is formed with a plurality of first via conductors 109 a and a plurality of second via conductors 109 b in which a large number of via holes penetrating all the ceramic dielectric layers 102 are embedded. Each first via conductor 109a connects and connects the upper first terminal electrode 107a and the lower first terminal electrode 108a in the stacking direction. In addition, each second via conductor 109b connects and connects the upper second terminal electrode 107b and the lower second terminal electrode 108b in the stacking direction.

  1 and 2, the power supply pad 201 in the semiconductor chip 200 includes a solder bump 40, a terminal pad 25, a via conductor 34, a conductor layer 23, a via conductor 32, a first terminal electrode 107a, and a first via conductor 109a. And connected to the first internal electrode layer 110a via the first terminal electrode 108a, the via conductor 33, the conductor layer 24, the via conductor 35, and the BGA pad 26 to the power supply solder ball 41. Connected. Further, the ground pad 201 in the semiconductor chip 200 is connected to the second terminal electrode 107b, the second via conductor 109b, and the second internal electrode layer 110b through the above-described path, and finally, the ground solder. Connected to the ball 41.

  In the capacitor 100 of the present embodiment, it is more advantageous in terms of transmission performance than using a via conductor to configure a signal wiring using the through-hole conductor 60. That is, generally, the dielectric constant of the closures 62 and 63 made of epoxy resin is sufficiently lower than that of the capacitor 100 such as barium titanate. Compared with via conductors, transmission signal delay can be suppressed. In addition, the via conductors must be formed using a material such as nickel due to restrictions when the capacitors 100 are fired simultaneously, but the through-hole conductors 60 can be formed using copper plating with high conductivity. The resistance component of the wiring can be reduced.

  Note that the size and interval of the first via conductor 109a and the second via conductor 109b formed in the capacitor 100 can be changed as appropriate, and accordingly, the first terminal electrodes 107a and 108a and the second terminal electrodes 107b and 108b can be changed. The arrangement also changes. In addition, the number and position of the through-hole conductors 60 and 61 used as signal wirings can be changed as appropriate. Note that the positions of the through-hole conductors 60 and 61 in the capacitor 100 are not necessarily limited to the center, but are preferably near the center of the capacitor 100 from the viewpoint of increasing the degree of freedom in routing signal wiring.

  In the capacitor 100, it is desirable that the through-hole conductor 61 having a shield structure is kept at the same potential as the positive electrode or the negative electrode. For example, in FIG. 3, a wiring pattern may be provided for connecting between the through-hole conductor 61 and the nearby second terminal electrode 107b for ground. Thereby, the effect of the shield with respect to signal wiring improves. The through-hole conductor 61 may be kept in a floating state without being connected to other wiring.

  Next, the manufacturing method of the wiring board 10 of this embodiment is demonstrated with reference to FIGS. First, as shown in FIG. 4, the core material 11 having the accommodation hole 11a is prepared and prepared. When producing the core material 11, for example, a copper-clad laminate in which a copper foil is attached to both sides of a square planar shape having a side of about 400 mm and a base material having a thickness of about 0.8 mm is prepared. Then, the copper-clad laminate is subjected to drilling using a router, and a through hole that becomes the accommodation hole portion 11a is formed in advance at a predetermined position.

  On the other hand, the capacitor 100 built in the wiring board 10 is prepared and prepared. In manufacturing the capacitor 100, nickel paste is screen-printed on a ceramic green sheet to form a coating film to be the first internal electrode layer 110a and a coating film to be the second internal electrode layer 110b. And the green sheet in which the coating film used as the 1st internal electrode layer 110a and the green sheet formed in the coating film used as the 2nd internal electrode layer 110b are laminated | stacked alternately, and pressing force is given to the lamination direction. The green sheets are integrated to form a laminate. Subsequently, a plurality of via holes are formed through the laminate using a laser processing machine, and a nickel paste is filled in each via hole to form a filler that becomes the first via conductor 109a and a filler that becomes the second via conductor 109b. To do. Then, a paste is printed on the upper surface of the stacked body to form a metallized layer of the first terminal electrode 107a and the second terminal electrode 107b. Similarly, a paste is printed on the lower surface of the multilayer body to form a metallized layer of the first terminal electrode 108a and the second terminal electrode 108b.

  Next, a through-hole (for example, a diameter of 0.6 mm) is formed at a position where the through-hole conductor 61 serving as a shield structure is formed by drilling using a drill machine. In addition, you may form a through-hole using a laser processing machine and a punching machine instead of a drill machine. When the laminated body is dried and degreased, and the laminated body is fired at a predetermined temperature for a predetermined time, barium titanate and nickel in the paste are simultaneously sintered to obtain a ceramic sintered body 101. Thereafter, the through-hole conductor 61 is formed by performing electroless copper plating and electrolytic copper plating on the through hole. Alternatively, the through-hole conductor 61 may be formed by performing through-hole printing of a paste such as nickel and firing after forming the through-hole. Furthermore, after the paste which has an epoxy resin as a main component is printed in the cavity part of the through-hole conductor 61, the obstruction | occlusion body 63 is formed by hardening. Then, each of the first terminal electrodes 107a and 108a and the second terminal electrodes 107b and 108b of the ceramic sintered body 101 is subjected to, for example, electrolytic copper plating with a thickness of about 10 μm to form a copper plating layer, and the capacitor 100 Is completed.

  Next, as shown in FIG. 5, a peelable adhesive tape 70 is placed in close contact with the bottom of the accommodation hole 11 a. This adhesive tape 70 is supported by a support base 71. Then, using the mounting device, the capacitor 100 is accommodated in the accommodation hole 11a, and the capacitor 100 is attached to the adhesive tape 70 and temporarily fixed. FIG. 5 shows a state in which the upper surfaces of the core material 11 and the capacitor 100 in FIG. 1 are directed downward (the same applies to FIG. 6).

  Subsequently, as shown in FIG. 6, the resin filler 50 is filled into the gap between the accommodation hole 11 a and the side surface of the capacitor 100 using a dispenser device. Since the resin filler 50 is made of a thermosetting resin, it is cured by heat treatment. The capacitor 100 is fixed inside the accommodation hole 11 a by the cured resin filler 50 and integrated with the core material 11. At this time, since the conductor layer 21 of the core material 11 and the first terminal electrode 107a and the second terminal electrode 107b of the capacitor 100 are in contact with the adhesive tape 70, they are formed on a flat surface whose positions are aligned in the stacking direction. The method of filling the resin filler 50 is not limited to the dispenser device, and for example, a method of pressing and filling a film-like insulating resin material may be used.

  Next, the adhesive tape 70 is peeled after the capacitor 100 is fixed. Thereafter, the upper surface of the core material 11 and the upper surface of the capacitor 100 are subjected to solvent cleaning by acid degreasing and then polished, whereby the remaining adhesive of the peeled adhesive tape 70 is removed. Subsequently, the surface of the copper plating layer above the first terminal electrode 107 a and the second terminal electrode 107 b is roughened, and the surface of the conductor layer 21 above the core material 11 is roughened. After finishing the roughening, the core material 11 and the capacitor 100 are washed.

  Thereafter, as shown in FIG. 7, a through hole is formed in the formation position of the through hole conductor 30 of the core material 11 by drilling using a drill machine, and a through hole in the vicinity of the center of the closing body 63 of the capacitor 100. A through hole (for example, a diameter of 0.3 mm) is formed at the position where the conductor 60 is formed. Through-hole conductors 30 and 60 are formed by applying electroless copper plating and electrolytic copper plating to the respective through-holes that become through-hole conductors 30 and 60. In addition, the plugs 31 and 62 are formed by printing a paste mainly composed of an epoxy resin in the hollow portions of the through-hole conductors 30 and 60 and then curing the paste.

  Further, the copper foils on both surfaces of the core material 11 integrated with the capacitor 100 are etched, and the upper and lower conductor layers 21 and 22 and the terminal electrodes 107c and 108c are formed by using, for example, a subtractive method. Specifically, after electroless copper plating is performed and the portion is subjected to electrolytic copper plating as a common electrode, a dry film having a predetermined pattern is formed by laminating a dry film and performing exposure and development. In this state, unnecessary electrolytic copper plating layers, electroless copper plating layers, and copper foils are removed by etching, and then the dry film is peeled off.

  Next, film-like insulating resin materials mainly composed of epoxy resin are laminated on the upper and lower surfaces of the core material 11 and the capacitor 100, respectively. Then, the insulating resin material is cured by applying pressure under vacuum to form a resin insulating layer 14 on the upper surface side and a resin insulating layer 15 on the lower surface side as shown in FIG. Subsequently, as shown in FIG. 9, a plurality of via conductors 32 are formed in the resin insulating layer 14, and a plurality of via conductors 33 are formed in the resin insulating layer 15. At this time, a plurality of via holes are formed in the resin insulating layers 14 and 15 by laser processing, and after desmear processing for removing smears therein, via conductors 32 and 33 are formed in the via holes. 7 to 9 show states in which the upper surfaces of the core material 11 and the capacitor 100 are directed upward.

  Thereafter, as shown in FIG. 1, the surfaces of the resin insulating layers 14 and 15 are patterned to form conductor layers 23 and 24, respectively. Next, the above-described film-like insulating resin materials are laminated on the upper surface of the resin insulating layer 14 and the lower surface of the resin insulating layer 15, respectively, and the insulating resin material is cured by applying pressure and heating under vacuum, whereby the resin insulating layer 16 , 17 are formed. Then, a plurality of via conductors 34 and 35 are formed in the resin insulating layers 16 and 17 by the same method as the above-described via conductors 32 and 33. Subsequently, a plurality of terminal pads 25 are formed on the top of the resin insulating layer 16, and a plurality of BGA pads 26 are formed on the bottom of the resin insulating layer 17. Next, solder resist layers 18 and 19 are formed by applying and curing a photosensitive epoxy resin on the upper surface of the resin insulating layer 16 and the lower surface of the resin insulating layer 17, respectively. Thereafter, openings are patterned in the solder resist layer 18 to form a plurality of solder bumps 40 connected to the plurality of terminal pads 25. Also, openings are patterned in the solder resist layer 19 to form a plurality of solder balls 41 connected to the plurality of BGA pads 26. The wiring board 10 of this embodiment is completed by the above procedure.

  Note that the method of manufacturing the wiring board 10 based on FIGS. 4 to 9 is an example, and the wiring board 10 can be manufactured according to different procedures. For example, in the above-described example, the capacitor 100 before being accommodated in the accommodation hole portion 11a of the wiring board 10 is formed with only the through-hole conductor 61 and the closing body 63 having a shield structure in advance. The through-hole conductor 60 and the closing body 62 may be formed in advance. For example, when a shield structure is unnecessary around the signal wiring, the capacitor 100 in which only the through-hole conductor 60 and the closing body 62 are formed in advance may be used.

  The contents of the present invention have been specifically described above based on the present embodiment, but the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the present invention. FIG. 10 shows a schematic cross-sectional structure of the wiring board 10 when the method of forming the through-hole conductors 30 and 60 and the closing bodies 31 and 62 in FIG. 1 is changed as a modification of the present embodiment. The wiring substrate 10 shown in FIG. 10 has through-hole conductors 30a and 60a extending in the laminating direction and penetrating the upper and lower resin insulation layers 14 and 15 as compared to the through-hole conductors 30 and 60 and the closing bodies 31 and 62 of FIG. And the point which formed the obstruction | occlusion bodies 31a and 62a differs. Therefore, when manufacturing the wiring substrate 10, it is necessary to form the through-hole conductors 30 a and 60 a and the closing bodies 31 a and 62 a after forming the resin insulating layers 14 and 15 on and under the core material 11. In the wiring board 10 of FIG. 10, the structure other than the through-hole conductors 30a and 60a and the closing bodies 31a and 62a is the same as that of FIG.

DESCRIPTION OF SYMBOLS 10 ... Wiring board 11 ... Core material 11a ... Accommodating hole part 12 ... 1st wiring laminated part 13 ... 2nd wiring laminated part 14, 15, 16, 17 ... Resin insulation layers 18, 19 ... Solder resist layers 21, 22, 23 24 ... conductor layer 25 ... terminal pad 26 ... BGA pads 30, 30a, 60, 60a, 61 ... through-hole conductors 31, 31a, 62, 62a, 63 ... closed bodies 32, 33, 34, 35 ... via conductors 40 ... Solder bump 41 ... Solder ball 50 ... Resin filler 100 ... Capacitor 200 ... Semiconductor chip 201 ... Pad

Claims (9)

A wiring board for placing a mounting component and electrically connecting the mounting component and an external base material,
A core material in which an accommodation hole penetrating the upper surface and the lower surface is opened;
A built-in component that is housed in the housing hole and in which one or a plurality of first through-hole conductors penetrating the upper surface and the lower surface are formed;
A first wiring laminated portion in which insulating layers and conductor layers are alternately laminated on the upper surface side of the core material;
A second wiring laminated portion in which insulating layers and conductor layers are alternately laminated on the lower surface side of the core material;
The first through-hole conductor is used as a signal wiring connected to the mounting component via the first wiring laminated portion, and a material of the built-in component is disposed in an area inside the first through-hole conductor. A material having a dielectric constant lower than that of the first through-hole conductor is filled with a material having a dielectric constant lower than that of the built-in component. A wiring board characterized by.   The wiring board according to claim 1, wherein the first through-hole conductor is formed using a metal having a conductivity higher than that of an internal conductor of the built-in component.   The wiring board according to claim 1, wherein the built-in component is a capacitor configured using a ceramic sintered body.   In the built-in component, a second through-hole conductor for shielding the signal wiring is formed so as to surround a side surface of the first through-hole conductor, and the first through-hole conductor and the second through-hole conductor are connected to each other. 4. The wiring board according to claim 1, wherein the sandwiched region is filled with a material having a dielectric constant lower than that of the material of the built-in component.   The wiring board according to claim 4, wherein the first through-hole conductor and the second through-hole conductor are located immediately below a central portion of the mounting component. A multilayer ceramic capacitor in which ceramic dielectric layers and internal electrode layers are alternately stacked, and a plurality of via conductors connected to the internal electrode layers are arranged in an array,
One or a plurality of first electrodes formed using a metal having a conductivity higher than the conductivity of the internal electrode layer and the via conductor, penetrating the upper surface and the lower surface of the region where the plurality of via conductors are not disposed. With through-hole conductors,
A region inside the first through-hole conductor is filled with a material having a dielectric constant lower than that of the ceramic dielectric layer, and a region near the outside of the first through-hole conductor is a material of the built-in component. A multilayer ceramic capacitor characterized in that it is covered with a material having a dielectric constant lower than that of the multilayer ceramic capacitor.   The ceramic dielectric layer is further provided in a region sandwiched between the first through-hole conductor and the second through-hole conductor, further comprising a second through-hole conductor formed so as to surround a side surface of the first through-hole conductor. The multilayer ceramic capacitor according to claim 6, which is filled with a material having a dielectric constant lower than that of the multilayer ceramic capacitor.   The multilayer ceramic capacitor according to claim 7, wherein the first through-hole conductor and the second through-hole conductor are formed by copper plating.   The multilayer ceramic capacitor according to claim 7, wherein the second through-hole conductor is connected to the same potential as the positive electrode or the negative electrode of the internal electrode layer.

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